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FilesPCBEDU-XILINXProyectoKicad
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Bank14.bak
Bank14.sch
Bank15.bak
Bank15.sch
Bank35.bak
Bank35.sch
EduCiaaX-cache.lib
EduCiaaX.bak
EduCiaaX.csv
EduCiaaX.erc
EduCiaaX.net
EduCiaaX.pro
EduCiaaX.sch
EduCiaaX.xls
EduCiaaX.xlsx
EduCiaaX.xml
EduCiaaXSchLibrary.bak
EduCiaaXSchLibrary.bck
EduCiaaXSchLibrary.dcm
EduCiaaXSchLibrary.lib
FPGAConfig.bak
FPGAConfig.sch
FPGAPower.bak
FPGAPower.sch
Power.bak
Power.sch
Usb.bak
Usb.sch
XilinxArtix7.bak
XilinxArtix7.bck
XilinxArtix7.dcm
XilinxArtix7.lib
ft2232h.dcm
ft2232h.lib
r_small.bak
r_small.bck
r_small.dcm
r_small.lib
EduCiaaX.erc
ERC report (25/09/2015 04:34:40 p.m.) ***** Hoja / ***** Hoja /Power/ ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (3.500 in,1.350 in): Pin 1 (passive) of component JP2 is unconnected. ***** Hoja /FPGAPower/ ***** Hoja /FPGAConfig/ ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (8.500 in,3.350 in): Pin 2 (BiDi) of component U6 is unconnected. ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (8.500 in,3.550 in): Pin 3 (BiDi) of component U6 is unconnected. ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (9.750 in,3.750 in): Pin 4 (passive) of component U6 is unconnected. ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (8.500 in,3.150 in): Pin 5 (BiDi) of component U6 is unconnected. ErrType(2): Pin not connected (and no connect symbol found on this pin) @ (8.500 in,3.750 in): Pin 7 (BiDi) of component U6 is unconnected. >> Errores ERC: 0
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