Mosfets.md
Selection of mosfets

Most losses in a dcdc converter happens in the switches and the coil. Higher switching frequency increase switching
losses, but reduces coil loss, because smaller inductivity is needed thus less coil wire loss.

In a sync buck topology the HS-Switch (aka control, switch fet) and the LS (sync fet) operate
in quite different conditions.

In CCM mode the current through the LS switch always flow from source to drain in the
direction of the body diode, whereas on the HS switch conducts current the opposite way from drain to source.

Consequently, the LS suffers from self turn-on caused by HS and the HS suffers from LS's reverse recovery
charge.

Reducing switching times does not necesarilly steer to optimum efficiency, because it can cause self turn-on.
Poor performance of one switch can heat up the other.
With that having in mind, let's take a closer look into the losses in the mosfet.

Conduction Loss

This is straightforward, lower Rds_on will have lower conduction loss.
The average loss is R_ds_on * I² * D where D is the duty cycle.

R_ds_on generally has a positve temperature coefficient so parallel mosfets will share the load equally.

Switching loss (HS)

Current that flows during turn-on, until Rds reaches Rds_on, causes significant power loss in the switch.
Faster on and off switching reduces this loss. Mosfets datasheet specify rise time (tr) for turn-on and fall time (tf)
for turn-off. Choose low gate drive resistor and mosfet with low Qg (Qsw). Note that low gate resistors can cause
instabilities due to ringing gate and LS self-turn on (see below).
Faster switching poses more stress on the input capacitors on increases loss in their ESR.
Note that parellel mosfets doesn't share switching loss well. Due to production variations one switch will always be
faster than others

Switching loss at the LS are negligible because it switches with powered body diode.

<![CDATA[]]>This rohm AN<![CDATA[]]> presents calculations for power loss estimations.

![](img/mosfet qg.webp)

^ Composition of
Qg [<![CDATA[]]>src<![CDATA[]]>]

<![CDATA[]]>https://techweb.rohm.com/product/power-device/si/4955/<![CDATA[]]>

Output Capacitance Loss

<![CDATA[]]>https://www.onelectrontech.com/power-mosfet-capacitance-coss-and-switchi...<![CDATA[]]>
<![CDATA[]]>https://community.infineon.com/t5/Knowledge-Base-Articles/FAQ-MOSFET-Out...<![CDATA[]]>.
(eff energy related Coss)

Self turn-on loss (caused by LS)

The LS is prone to self-turn-on caused by high du/dt from short HS switching times. Note that this loss is dissipated in
both HS and LS switch depending on there current R_ds. Most of the heat goes to HS.

<![CDATA[]]>https://www.onsemi.com/download/application-notes/pdf/an-9010.pdf#page=14<![CDATA[]]>


false turn-on, risk increases with higher temperature as Vgs_th falls.
parasitic transistor turn-on


At the HS there is no self-turn-on because parasitic gate capacitances Cgd/Cgs are charged inversely (
see <![CDATA[]]>this EETimes article<![CDATA[]]>).



*^ Waveform of LS gate voltage, HS gate voltage and LS drain current.

Qrr loss (caused by LS)

High reverse recovery charge Qrr in the HS body-diode causes ringing. Higher gate drive resistors RC-Snubbers help
here.

Reverse recovery in the LS is discussed in
the <![CDATA[]]>eetimes article<![CDATA[]]> and in
a <![CDATA[]]>nexperia article<![CDATA[]]>. Note that this loss is dissipated in the HS switch during its turn-on.

Qrr depends on
di/dit <![CDATA[]]>https://www.st.com/resource/en/application_note/dm00380483-calculation-o...<![CDATA[]]>

ringing wave form <![CDATA[]]>https://www.ti.com/lit/an/slpa010/slpa010.pdf#page=2<![CDATA[]]>
Causes Voltage peak V_sw and EMI.

Using a cascode to reduce reverse recovery <![CDATA[]]>https://ieeexplore.ieee.org/document/10147632<![CDATA[]]>

<![CDATA[]]>https://www.onsemi.com/download/application-notes/pdf/an-9010.pdf#page=15<![CDATA[]]>

<![CDATA[]]>https://www.electronicdesign.com/technologies/power/article/21800964/mos...<![CDATA[]]>
<![CDATA[]]>https://electronics.stackexchange.com/questions/641280/how-to-model-reve...<![CDATA[]]>
<![CDATA[]]>https://electronics.stackexchange.com/questions/494817/how-does-ltspice-...<![CDATA[]]>
<![CDATA[]]>https://www.st.com/content/ccc/resource/technical/document/application_n...<![CDATA[]]>
<![CDATA[]]>https://www.microsemi.com/document-portal/doc_download/14617-rectifier-r...<![CDATA[]]>
<![CDATA[]]>https://electronics.stackexchange.com/questions/432744/reverse-recovery-...<![CDATA[]]>
<![CDATA[]]>https://rocelec.widen.net/view/pdf/605ozlfwbi/ONSM-S-A0003584030-1.pdf?t...<![CDATA[]]>

TODO ringing the bell pcb test circuit

![](img/mosfet qrr.webp)

^ Diode Reverse
recovery [<![CDATA[]]>src<![CDATA[]]>]

<![CDATA[]]>TI Video on Reverse Recovery<![CDATA[]]>


[<![CDATA[]]>src<![CDATA[]]>]

Figuring the FET

Now lets think about what properties good HS and LS FETs should have.

Remember these losses:


HS switching loss
HS and LS conduction loss (R_ds * I²), distribution depends on the duty cycle D.
LS self turn-on (cause shoot-through current and losses in both HS and LS)


See <![CDATA[]]>Toshibas Mosfet Guide<![CDATA[]]>
for a visualization of these losses in a timing chart.
It features the TPCA8028-H.

Fast HS switching conflicts with LS self turn-on, so the shortest HS rise time will not nececarilly

TODO happily article, nesesarally FOM best, mosfet selection

self-turn on

LS:


low body diode forward voltage (most fets have ~1V)
low Qgd/Qgs ratio to avoid sell-turn on
Low r_g


HS:


Low Q_SW
Low Q_rr
Low r_g
high V_gs_th (usually increases Rds_on)


EMI:
LS self turn-on loss and any



[<![CDATA[]]>src<![CDATA[]]>]

Step-by-Step guide


use fetlib to find suitable mosfets
acquire SPICE models the selected parts
run a spice simulation and tweak gate drive resistors
order sample parts and do a real test.


compare real waveforms to the ones from the simulation. take a close look at the switch node ringing.
compute parasitic shoot-through path inductance from di/dt during reverse recovery or ringing frequency
use thermal camera to check which mosfets get warmer and compare to simulation
adjust the simulation if needed
measure efficenncy of the real dcdc converter (consider coil loss)
if real results are very different from simulation, review simulation. take a closer look to parisitic inductances
in the shoot-through path. inspect RC snubber circuits. consider ESR of capacitors.





SPICE

-

ltspice <![CDATA[]]>add mosfet model<![CDATA[]]>


replacing the LS with a schottky diode (MBR30100CT) helps evaluating the HS performance, since a diode has no self
turn-on and does not suffer from reverse recovery (see <![CDATA[]]>ti video<![CDATA[]]>)
you can find SPICE models on the manufacturer
website (<![CDATA[]]>onsemi<![CDATA[]]>)
V(Vi,Vsw)Ix(U2:1)+V(VgH,Vsw)Ix(U2:2)


<![CDATA[]]>https://forum.qorvo.com/t/mos-simulation-issues/18832/6<![CDATA[]]>

Losses

TODO <![CDATA[]]>https://www.infineon.com/dgdl/Infineon-Buck_converters_negative_spike_at...<![CDATA[]]>

40khz, 500ms DT,
inspection of power plots using the integration tool:

uJ
                self-turn-on  sw-on   sw-off   RDS    RR      BD   BD turn on, charge up?
CSD19506KCS H  ~2.6           20       21      30     TODO                    uJ
AONS66811   L   2.6           1.2      0       12             11   2.6        uJ


Mosfet Picks:

Vds Rds Qg tRise tFall Qrr




  
MPN
  
Vds
  
Rds_max_25
  
Qg_max
  
tRise
  
tFall
  
Qrr
  
trr
  
Vsd
  
comment




  
STP110N8F6
  
80
  
6.5
  
150
  
61
  
48
  
34
  

  

  
very low Qrr, SPICE model buggy


  
TK2R4A08QM
  
80
  
2.4
  
179
  
91
  
95
  
100
  

  

  
good HS , LS


  
TK3R2A08QM
  
80
  
3.2
  
102
  
78
  
79
  
69
  

  

  
good LS


  
FDP027N08B
  
80
  
2.7
  
178
  
66
  
41
  
112
  
80
  
1.3
  
good LS    VGS = 0 V, VDD = 40 V, ISD = 100 A,dIF/dt = 100 A/μs


  

  

  

  

  

  

  

  

  

  



  
IPA050N10NM5S
  

  

  

  

  

  

  

  

  
good HS


  
CSD19506KCS
  

  

  

  

  

  

  

  

  
good HS but high Qg


  
NTMFS4D0N08XT1G
  
80
  
3.5
  
33
  

  

  

  

  

  



  
FDP8D5N10C
  

  

  

  

  

  

  

  

  





IPP040N08NF2SAKMA1 HS
IPP022N12NM6AKSA1 LS # pricy!
IPA052N08NM5S # 80v, 1€
,

in this case CSD19506KCS switching loss is 41 and RDS 30

Takeaways


self-turn-on loss is low
LS Rds loss is ~ Body diode Loss during dead time -> fit dead time
ratio of HS sw/Rds loss is 4:3


TODO

<![CDATA[]]>MOSFET power losses and how they affect power-supply efficiency<![CDATA[]]>


<![CDATA[]]>https://eepower.com/technical-articles/rethinking-the-power-mosfet-figur...<![CDATA[]]>

Parallel Switches

Parallel HS:
Due to variations from the manufacturing process, one switch will take all the switching loss.
RDson loss is 1/4. Adds to gate drive current. (FOM)

Parallel LS:
Adds to gate drive current. (FOM)
Adds Qrr loss. (FOMrr)

Placing a second LS of the same model in parallel will reduce conduction loss to a half but doubles the reverse
recovery loss (in the HS switch).

Advancded Optimizations


Cascode against reverse
recovery <![CDATA[]]>https://ieeexplore.ieee.org/document/10147632<![CDATA[]]> <![CDATA[]]>https://www.researchgate.net/figure/Reverse-recovery-current-of-cascodes...<![CDATA[]]>


<![CDATA[]]>https://www.qorvo.com/products/d/da008868<![CDATA[]]>

TO220 reduce parasitic
inductance <![CDATA[]]>https://research-information.bris.ac.uk/ws/portalfiles/portal/164064092/...<![CDATA[]]>


IRFS4228PBF datasheet with D & S inductances:
4.5nH/7.5nH. notice that these might not simply add up

reverse recovery

reverse recovery of sync fet's (buck LS) body diode can cause server EMI and power loss.

During reverse recovery the mosfet is like a capacitor. In a half-bridge, imagine the HS switch
being a resistor and the LS a capacitor that is inversingly charged. current will flow until this capacitor
is fully discharged (Vds=0) and then the body diode interrupts. this can cause significant loss, because of the voltage
drop at HS is equal to the input voltage.

The current peaks at I_RM, which can be quite high. It takes the low resistance path across both switches.
Parasitic inductances in this path will cause ringing of the switching node voltage.

<![CDATA[]]>https://www.onsemi.com/download/application-notes/pdf/an-9010.pdf#page=15<![CDATA[]]>

Recovering
<![CDATA[]]>https://sci-hub.se/10.1007/978-3-642-15739-4_12<![CDATA[]]>

Schottky diode can reduce rr?


AUIRFS/SL4115


<![CDATA[]]>https://www.mouser.com/datasheet/2/268/mscos08164_1-2275581.pdf#page=6<![CDATA[]]>
<![CDATA[]]>https://labs.ece.uw.edu/pemodels/papers/simpforeverse.pdf<![CDATA[]]>

Gan


very low Qg, very fast
only 5V Vgs
no Qrr -> no reverse recovery loss
full potential of GaN needs >2 PCB layers


Strip Lines

GaN assembly needs hot-air gun and
IR-lamp <![CDATA[]]>https://epc-co.com/epc/Portals/0/epc/documents/application-notes/How2App...<![CDATA[]]>
thermal resistance is a bit worth, but that probably doesnt matter
<![CDATA[]]>https://epc-co.com/epc/design-support/part-cross-reference-search<![CDATA[]]>