LMB.sch-bak
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 22
Title "Laser Monitoring Board"
Date "2020-04-09"
Rev "1"
Comp "Irfu/DphP"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 1375 675  0    118  ~ 0
ADC Side
$Sheet
S 4175 4850 750  825 
U 571914DE
F0 "GTX links" 50
F1 "sch/FPGA_Gb.sch" 50
F2 "SFP_Tx+" I L 4175 4925 39 
F3 "SFP_Tx-" I L 4175 5000 39 
F4 "SFP_Rx+" I L 4175 5100 39 
F5 "SFP_Rx-" I L 4175 5175 39 
F6 "sData1_P[0..3]" I L 4175 5275 50 
F7 "sData1_N[0..3]" I L 4175 5350 50 
$EndSheet
$Sheet
S 4650 950  1700 2375
U 57195CF6
F0 "IO banks" 50
F1 "sch/Convert.sch" 50
F2 "SFP_Present" I R 6350 1525 39 
F3 "SFP_LOS" I R 6350 1600 39 
F4 "SFP_Tx_Fault" I R 6350 1675 39 
F5 "SFP_SCL" O R 6350 1750 39 
F6 "SFP_SDA" B R 6350 1825 39 
F7 "CLK_in+" I L 4650 2625 39 
F8 "CLK_in-" I L 4650 2700 39 
F9 "I2C_SCL_CATIA" O L 4650 1450 39 
F10 "I2C_SDA_CATIA" B L 4650 1525 39 
F11 "TP_trigger" O L 4650 1900 39 
F12 "LED[0..7]" O R 6350 1925 39 
F13 "SB_in_P[1..7]" I L 4650 1175 39 
F14 "SB_in_N[1..7]" I L 4650 1250 39 
F15 "GPIO[0..10]" B R 6350 2000 39 
F16 "SB_out_P[1..7]" O R 6350 1175 39 
F17 "SB_out_N[1..7]" O R 6350 1250 39 
F18 "I2C_SCL_DTU" O L 4650 1600 39 
F19 "I2C_SDA_DTU" B L 4650 1675 39 
F20 "PiN_out_P[0..7]" O R 6350 1025 39 
F21 "PiN_out_N[0..7]" O R 6350 1100 39 
F22 "SPI_ADC_CLK" O L 4650 2075 39 
F23 "SPI_ADC_DIO" B L 4650 2150 39 
F24 "SPI_ADC_CSb" O L 4650 2225 39 
F25 "I2C_SCL_Clk" O R 6350 2100 39 
F26 "I2C_SDA_Clk" B R 6350 2175 39 
F27 "Clk_Rstb" O R 6350 2250 39 
F28 "Clk_OK" O R 6350 2325 39 
F29 "Clk_LoL" O R 6350 2400 39 
F30 "Loc_Rstb" O L 4650 1750 39 
F31 "Calib_ADC" O L 4650 1825 39 
F32 "ADC_GPIO[1..2]" B L 4650 2350 39 
F33 "Dum_out_P[1..2]" O R 6350 1325 39 
F34 "Dum_out_N[1..2]" O R 6350 1400 39 
F35 "PllLock_in[1..7]" O L 4650 2425 39 
F36 "PllLock_out[1..7]" O R 6350 2475 39 
F37 "Pg[1..6]" O R 6350 2550 39 
F38 "En[1..2]" O R 6350 2625 39 
F39 "ReSync_in_P" O R 6350 2700 39 
F40 "ReSync_in_N" O R 6350 2775 39 
F41 "ReSync_out_P" O L 4650 2775 39 
F42 "ReSync_out_N" O L 4650 2850 39 
F43 "Laser_trigger[1..8]" O L 4650 2925 39 
F44 "FB_PIN[1..2]" I L 4650 3000 39 
$EndSheet
Text Label 4025 1175 0    39   ~ 0
Dout_SB_P[1..7]
Wire Bus Line
	4025 1175 4650 1175
$Sheet
S 975  4825 1125 1175
U 571000A8
F0 "SFP" 60
F1 "sch/SFP.sch" 60
F2 "SFP_Present" O R 2100 5350 39 
F3 "SFP_LOS" O R 2100 5450 39 
F4 "SFP_Tx_Fault" O R 2100 5550 39 
F5 "SFP_SCL" I R 2100 5800 39 
F6 "SFP_SDA" B R 2100 5900 39 
F7 "SFP_Rx+" O R 2100 5100 39 
F8 "SFP_Tx+" I R 2100 4925 39 
F9 "SFP_Rx-" O R 2100 5175 39 
F10 "SFP_Tx-" I R 2100 5000 39 
$EndSheet
Text Label 4025 1450 0    39   ~ 0
I2C_SCL_CATIA
Text Label 4025 1525 0    39   ~ 0
I2C_SDA_CATIA
Wire Wire Line
	4650 1450 4025 1450
Wire Wire Line
	4650 1525 4025 1525
Text Label 2225 5350 0    50   ~ 0
SFP_Present
Text Label 2225 5450 0    50   ~ 0
SFP_LOS
Text Label 2225 5550 0    50   ~ 0
SFP_Tx_Fault
Text Label 2225 5800 0    50   ~ 0
SFP_SCL
Text Label 2225 5900 0    50   ~ 0
SFP_SDA
Wire Wire Line
	2100 5350 2550 5350
Wire Wire Line
	2100 5450 2550 5450
Wire Wire Line
	2100 5550 2550 5550
Wire Wire Line
	2100 5800 2550 5800
Wire Wire Line
	2100 5900 2550 5900
Text Label 6975 1525 2    39   ~ 0
SFP_Present
Text Label 6975 1600 2    39   ~ 0
SFP_LOS
Text Label 6975 1750 2    39   ~ 0
SFP_SCL
Text Label 6975 1825 2    39   ~ 0
SFP_SDA
$Sheet
S 5125 4850 775  825 
U 572B8C2E
F0 "Programming" 60
F1 "sch/prog.sch" 60
$EndSheet
$Sheet
S 6100 4850 775  825 
U 572C0D81
F0 "Power bank" 60
F1 "sch/FPGA_power.sch" 60
$EndSheet
Wire Notes Line
	3700 500  3700 6100
Wire Notes Line
	3700 6100 7300 6100
Wire Notes Line
	7300 6100 7300 500 
Wire Notes Line
	625  500  2950 500 
Wire Notes Line
	7300 500  3700 500 
Text Notes 4100 750  0    120  ~ 0
KINTEX 7: xc7k70t-fbg676-2
Text Label 4025 1750 0    39   ~ 0
PwupRstb
Wire Wire Line
	4025 1750 4650 1750
$Comp
L power:GNDD #PWR0102
U 1 1 579C24C0
P 1550 7025
F 0 "#PWR0102" H 1550 6775 50  0001 C CNN
F 1 "GNDD" H 1550 6875 50  0000 C CNN
F 2 "" H 1550 7025 50  0000 C CNN
F 3 "" H 1550 7025 50  0000 C CNN
	1    1550 7025
	1    0    0    -1  
$EndComp
$Comp
L power:PWR_FLAG #FLG0101
U 1 1 579C2F52
P 1850 6825
F 0 "#FLG0101" H 1850 6920 50  0001 C CNN
F 1 "PWR_FLAG" H 1850 7005 50  0000 C CNN
F 2 "" H 1850 6825 50  0000 C CNN
F 3 "" H 1850 6825 50  0000 C CNN
	1    1850 6825
	1    0    0    -1  
$EndComp
Wire Wire Line
	1450 6825 1450 6925
Wire Wire Line
	1350 6825 1450 6825
$Comp
L Connector_Generic:Conn_01x04 P101
U 1 1 57B4ABF0
P 1150 7025
F 0 "P101" H 1150 7250 50  0000 C CNN
F 1 "PINS_1x4" H 950 7025 50  0001 C CNN
F 2 "MDJ_mod:Molex-172310-1204" V 1325 7025 50  0000 C CNN
F 3 "" H 950 7025 50  0000 C CNN
F 4 "Digi-key" H 1150 7025 50  0001 C CNN "Supplier"
F 5 "WM11841-ND" H 1150 7025 50  0001 C CNN "Supplier P/N"
F 6 "Please buy mating connector" H 1150 7025 50  0001 C CNN "notes"
	1    1150 7025
	-1   0    0    1   
$EndComp
Wire Wire Line
	1450 6925 1350 6925
Connection ~ 1450 6825
Wire Wire Line
	1350 7125 1450 7125
Wire Wire Line
	1450 7125 1450 7025
Connection ~ 1450 7025
Wire Wire Line
	1350 7025 1450 7025
$Sheet
S 9775 4975 850  800 
U 57B6569D
F0 "GPIOs" 60
F1 "sch/GPIO.sch" 60
F2 "GPIO[0..10]" B L 9775 5175 39 
F3 "LED[0..7]" I L 9775 5075 39 
$EndSheet
Text Label 7000 1925 2    39   ~ 0
LED[0..7]
Text Label 7000 2000 2    39   ~ 0
GPIO[0..10]
Text Label 9250 5075 0    50   ~ 0
LED[0..7]
Text Label 9250 5175 0    50   ~ 0
GPIO[0..10]
Wire Bus Line
	9250 5075 9775 5075
Wire Bus Line
	9250 5175 9775 5175
Wire Wire Line
	1450 7025 1550 7025
$Sheet
S 1250 875  1200 775 
U 57059335
F0 "ADC_1280" 60
F1 "sch/ADC_1280.sch" 60
F2 "sData_P[0..3]" O R 2450 925 39 
F3 "sData_N[0..3]" O R 2450 1000 39 
F4 "Clk_1280_P" I L 1250 925 39 
F5 "Clk_1280_N" I L 1250 1000 39 
F6 "CSb" I L 1250 1600 39 
F7 "SDIO" B L 1250 1525 39 
F8 "SCLK" I L 1250 1450 39 
F9 "GPIO[1..2]" O R 2450 1125 39 
F10 "SyncIn_P" I L 1250 1100 39 
F11 "SyncIn_N" I L 1250 1175 39 
F12 "SysRef_N" I L 1250 1325 39 
F13 "SysRef_P" I L 1250 1250 39 
$EndSheet
Wire Bus Line
	2450 925  2925 925 
Text Label 2925 925  2    39   ~ 0
sData1_P[0..3]
Wire Bus Line
	2450 1000 2925 1000
Text Label 4025 1250 0    39   ~ 0
Dout_SB_N[1..7]
Wire Bus Line
	4025 1250 4650 1250
Text Label 650  1000 0    39   ~ 0
CLK_for_ADC_N
Text Label 650  925  0    39   ~ 0
CLK_for_ADC_P
Text Label 8275 3500 0    39   ~ 0
CLK_for_SB_N
Text Label 8275 3425 0    39   ~ 0
CLK_for_SB_P
Text Label 4025 1825 0    39   ~ 0
Calib_ADC
Wire Wire Line
	4650 1900 4025 1900
Text Label 4025 1900 0    39   ~ 0
TP_trigger
Wire Wire Line
	4650 1825 4025 1825
Wire Wire Line
	8275 3875 8975 3875
Wire Wire Line
	8275 3950 8975 3950
Text Label 8275 3875 0    39   ~ 0
CLK_for_FPGA_P
Text Label 8275 3950 0    39   ~ 0
CLK_for_FPGA_N
$Sheet
S 8975 3250 975  875 
U 5BAC43A6
F0 "Clock" 50
F1 "sch/clock.sch" 50
F2 "CLK_for_SB_P" O L 8975 3425 39 
F3 "CLK_for_SB_N" O L 8975 3500 39 
F4 "CLK_to_FPGA_P" O L 8975 3875 39 
F5 "Clk_from_FE_P" I R 9950 3425 39 
F6 "Clk_from_FE_N" I R 9950 3500 39 
F7 "CLK_for_ADC_P" O L 8975 3650 39 
F8 "CLK_for_ADC_N" O L 8975 3725 39 
F9 "Clk_OK" O R 9950 3700 39 
F10 "LoL" O R 9950 3750 39 
F11 "PwupRstb" O R 9950 3800 39 
F12 "I2C_SCL" O R 9950 3900 39 
F13 "I2C_SDA" B R 9950 3950 39 
F14 "CLK_to_FPGA_N" O L 8975 3950 39 
$EndSheet
Wire Wire Line
	2100 4925 4175 4925
Wire Wire Line
	4175 5000 2100 5000
Wire Wire Line
	2100 5100 4175 5100
Wire Wire Line
	4175 5175 2100 5175
Wire Wire Line
	8975 3425 8275 3425
Wire Wire Line
	8975 3500 8275 3500
Text Label 4025 1600 0    39   ~ 0
I2C_SCL_LVR
Text Label 4025 1675 0    39   ~ 0
I2C_SDA_LVR
Wire Wire Line
	4650 1600 4025 1600
Wire Wire Line
	4650 1675 4025 1675
Wire Wire Line
	650  1000 1250 1000
Wire Wire Line
	650  925  1250 925 
Text Label 650  1450 0    39   ~ 0
SPI_ADC_CLK
Wire Wire Line
	1250 1450 650  1450
Text Label 650  1525 0    39   ~ 0
SPI_ADC_DIO
Wire Wire Line
	1250 1525 650  1525
Text Label 650  1600 0    39   ~ 0
SPI_ADC_CSb
Wire Wire Line
	1250 1600 650  1600
$Comp
L power:GNDD #PWR0103
U 1 1 5E701421
P 2075 7025
F 0 "#PWR0103" H 2075 6775 50  0001 C CNN
F 1 "GNDD" H 2075 6875 50  0000 C CNN
F 2 "" H 2075 7025 50  0000 C CNN
F 3 "" H 2075 7025 50  0000 C CNN
	1    2075 7025
	1    0    0    -1  
$EndComp
$Comp
L power:GNDA #PWR0104
U 1 1 5E701432
P 2375 7025
F 0 "#PWR0104" H 2375 6775 50  0001 C CNN
F 1 "GNDA" H 2380 6852 50  0000 C CNN
F 2 "" H 2375 7025 50  0001 C CNN
F 3 "" H 2375 7025 50  0001 C CNN
	1    2375 7025
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W101
U 1 1 5D515915
P 5400 7075
F 0 "W101" H 5458 7195 50  0000 L CNN
F 1 "Hole" H 5458 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 5600 7075 50  0001 C CNN
F 3 "" H 5600 7075 50  0000 C CNN
	1    5400 7075
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W102
U 1 1 5D51598B
P 5675 7075
F 0 "W102" H 5733 7195 50  0000 L CNN
F 1 "Hole" H 5733 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 5875 7075 50  0001 C CNN
F 3 "" H 5875 7075 50  0000 C CNN
	1    5675 7075
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W103
U 1 1 5D5159AD
P 5925 7075
F 0 "W103" H 5983 7195 50  0000 L CNN
F 1 "Hole" H 5983 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 6125 7075 50  0001 C CNN
F 3 "" H 6125 7075 50  0000 C CNN
	1    5925 7075
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W104
U 1 1 5D5159D9
P 6175 7075
F 0 "W104" H 6233 7195 50  0000 L CNN
F 1 "Hole" H 6233 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 6375 7075 50  0001 C CNN
F 3 "" H 6375 7075 50  0000 C CNN
	1    6175 7075
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W105
U 1 1 5D515A0B
P 6425 7075
F 0 "W105" H 6483 7195 50  0000 L CNN
F 1 "Hole" H 6483 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 6625 7075 50  0001 C CNN
F 3 "" H 6625 7075 50  0000 C CNN
	1    6425 7075
	1    0    0    -1  
$EndComp
$Comp
L MDJ_compo:Hole W106
U 1 1 5D515A43
P 6675 7075
F 0 "W106" H 6733 7195 50  0000 L CNN
F 1 "Hole" H 6733 7104 50  0000 L CNN
F 2 "MDJ_mod:1pin_2.7" H 6875 7075 50  0001 C CNN
F 3 "" H 6875 7075 50  0000 C CNN
	1    6675 7075
	1    0    0    -1  
$EndComp
$Comp
L power:GNDA #PWR0105
U 1 1 5D53DF47
P 5400 7175
F 0 "#PWR0105" H 5400 6925 50  0001 C CNN
F 1 "GNDA" H 5405 7002 50  0000 C CNN
F 2 "" H 5400 7175 50  0001 C CNN
F 3 "" H 5400 7175 50  0001 C CNN
	1    5400 7175
	1    0    0    -1  
$EndComp
Wire Wire Line
	5400 7175 5400 7075
Wire Wire Line
	5400 7075 5675 7075
Connection ~ 5400 7075
Wire Wire Line
	5675 7075 5925 7075
Connection ~ 5675 7075
Wire Wire Line
	5925 7075 6175 7075
Connection ~ 5925 7075
Wire Wire Line
	6675 7075 6425 7075
Wire Notes Line
	10650 525  10650 2675
Wire Notes Line
	10650 2675 8350 2675
Wire Notes Line
	8300 2675 8300 525 
Wire Notes Line
	8325 525  10625 525 
Text Notes 9025 750  0    118  ~ 0
FE Side
$Sheet
S 9000 825  1050 1200
U 5D2A5AA9
F0 "FE_connect" 50
F1 "sch/FE_connect.sch" 50
F2 "PiN2_out_P[0..7]" I L 9000 1000 39 
F3 "PiN2_out_N[0..7]" I L 9000 1050 39 
F4 "I2C_SCL" B L 9000 1625 39 
F5 "I2C_SDA" B L 9000 1675 39 
F6 "Pg[1..6]" I L 9000 1500 39 
F7 "En[1..2]" I L 9000 1550 39 
F8 "1V2P" I R 10050 875 39 
F9 "2V5P" I R 10050 925 39 
F10 "SB_out_P[1..7]" I L 9000 1125 39 
F11 "SB_out_N[1..7]" I L 9000 1175 39 
F12 "Clk_160_P" O R 10050 1450 39 
F13 "Clk_160_N" O R 10050 1500 39 
F14 "PiN1_out_P[0..7]" I L 9000 875 39 
F15 "PiN1_out_N[0..7]" I L 9000 925 39 
F16 "ReSync_P" O R 10050 1075 39 
F17 "ReSync_N" O R 10050 1125 39 
F18 "Dum_out_P[1..2]" I L 9000 1250 39 
F19 "Dum_out_N[1..2]" I L 9000 1300 39 
F20 "PwupRstb" O R 10050 1000 39 
F21 "PllLock[1..7]" I L 9000 1375 39 
$EndSheet
Wire Bus Line
	2450 1125 2925 1125
Text Label 650  1175 0    39   ~ 0
SyncIn_N
Text Label 650  1100 0    39   ~ 0
SyncIn_P
Wire Wire Line
	650  1175 1250 1175
Wire Wire Line
	650  1100 1250 1100
Text Label 650  1325 0    39   ~ 0
SysRef_N
Text Label 650  1250 0    39   ~ 0
SysRef_P
Wire Wire Line
	650  1325 1250 1325
Wire Wire Line
	650  1250 1250 1250
Wire Wire Line
	2075 7025 2375 7025
Wire Wire Line
	6175 7075 6425 7075
Connection ~ 6175 7075
Connection ~ 6425 7075
Text Label 2925 1000 2    39   ~ 0
sData1_N[0..3]
Text Label 2925 1125 2    39   ~ 0
ADC_GPIO1[1..2]
Wire Notes Line
	625  500  625  2700
Wire Notes Line
	2950 500  2950 2700
Wire Notes Line
	2950 2700 625  2700
Wire Bus Line
	4175 5275 3700 5275
Text Label 3700 5275 0    39   ~ 0
sData1_P[0..3]
Wire Bus Line
	4175 5350 3700 5350
Text Label 3700 5350 0    39   ~ 0
sData1_N[0..3]
Wire Bus Line
	2450 2000 2925 2000
Text Label 2925 2000 2    39   ~ 0
Dout_SB_P[1..7]
Wire Bus Line
	2450 2050 2925 2050
Text Label 2925 2050 2    39   ~ 0
Dout_SB_N[1..7]
Text Label 650  2050 0    39   ~ 0
CLK_for_SB_N
Text Label 650  2000 0    39   ~ 0
CLK_for_SB_P
Text Label 650  2325 0    39   ~ 0
Calib_ADC
Wire Wire Line
	1250 2325 650  2325
Text Label 650  2450 0    39   ~ 0
I2C_SCL_CATIA
Wire Wire Line
	1250 2450 650  2450
Text Label 650  2500 0    39   ~ 0
I2C_SDA_CATIA
Wire Wire Line
	1250 2500 650  2500
Text Label 650  2200 0    39   ~ 0
ReSync_out_P
Wire Wire Line
	1250 2200 650  2200
Text Label 650  2250 0    39   ~ 0
ReSync_out_N
Wire Wire Line
	1250 2250 650  2250
Text Label 650  2125 0    39   ~ 0
PwupRstb
Wire Wire Line
	1250 2125 650  2125
$Sheet
S 1250 1950 1200 600 
U 5EA90FAE
F0 "Spy_box" 50
F1 "sch/Spy_box.sch" 50
F2 "Dout_SB_P[1..7]" O R 2450 2000 39 
F3 "Dout_SB_N[1..7]" O R 2450 2050 39 
F4 "PwupRstb" I L 1250 2125 39 
F5 "ReSync+" I L 1250 2200 39 
F6 "ReSync-" I L 1250 2250 39 
F7 "Calib_ADC" I L 1250 2325 39 
F8 "I2C_SCL_CATIA" I L 1250 2450 39 
F9 "I2C_SDA_CATIA" B L 1250 2500 39 
F10 "I2C_SCL_DTU" I R 2450 2400 39 
F11 "I2C_SDA_DTU" B R 2450 2450 39 
F12 "Clk_for_SB_P" I L 1250 2000 39 
F13 "Clk_for_SB_N" I L 1250 2050 39 
F14 "TP_trigger" I L 1250 2375 39 
F15 "PllLock[1..7]" O R 2450 2125 39 
$EndSheet
Text Label 2900 2400 2    39   ~ 0
I2C_SCL_DTU
Wire Wire Line
	2450 2400 2900 2400
Text Label 2900 2450 2    39   ~ 0
I2C_SDA_DTU
Wire Wire Line
	2450 2450 2900 2450
Wire Wire Line
	4650 2225 4025 2225
Text Label 4025 2225 0    39   ~ 0
SPI_ADC_CSb
Wire Wire Line
	4650 2150 4025 2150
Text Label 4025 2150 0    39   ~ 0
SPI_ADC_DIO
Wire Wire Line
	4650 2075 4025 2075
Text Label 4025 2075 0    39   ~ 0
SPI_ADC_CLK
Wire Wire Line
	4025 2625 4650 2625
Wire Wire Line
	4025 2700 4650 2700
Text Label 4025 2625 0    39   ~ 0
CLK_for_FPGA_P
Text Label 4025 2700 0    39   ~ 0
CLK_for_FPGA_N
$Sheet
S 7925 4975 850  800 
U 5787D549
F0 "FPGA_Power" 60
F1 "sch/power.sch" 60
$EndSheet
Text Label 6975 1175 2    39   ~ 0
SB_out_P[1..7]
Wire Bus Line
	6975 1175 6350 1175
Text Label 6975 1250 2    39   ~ 0
SB_out_N[1..7]
Wire Bus Line
	6975 1250 6350 1250
Text Label 6975 1025 2    39   ~ 0
PiN_out_P[0..7]
Wire Bus Line
	6975 1025 6350 1025
Text Label 6975 1100 2    39   ~ 0
PiN_out_N[0..7]
Wire Bus Line
	6975 1100 6350 1100
Text Label 8275 3725 0    39   ~ 0
CLK_for_ADC_N
Text Label 8275 3650 0    39   ~ 0
CLK_for_ADC_P
Wire Wire Line
	8275 3725 8975 3725
Wire Wire Line
	8275 3650 8975 3650
Wire Wire Line
	650  2000 1250 2000
Wire Wire Line
	1250 2050 650  2050
Text Label 10650 3500 2    39   ~ 0
CLK_from_FE_N
Text Label 10650 3425 2    39   ~ 0
CLK_from_FE_P
Wire Wire Line
	10650 3500 9950 3500
Wire Wire Line
	10650 3425 9950 3425
Text Label 10600 1500 2    39   ~ 0
CLK_from_FE_N
Text Label 10600 1450 2    39   ~ 0
CLK_from_FE_P
Wire Wire Line
	10600 1500 10050 1500
Wire Wire Line
	10600 1450 10050 1450
Text Label 8375 1125 0    39   ~ 0
SB_out_P[1..7]
Wire Bus Line
	8375 1125 9000 1125
Text Label 8375 1175 0    39   ~ 0
SB_out_N[1..7]
Wire Bus Line
	8375 1175 9000 1175
Text Label 8375 875  0    39   ~ 0
PiN_out_P[0..7]
Wire Bus Line
	8375 875  9000 875 
Text Label 8375 925  0    39   ~ 0
PiN_out_N[0..7]
Wire Bus Line
	8375 925  9000 925 
Text Label 10650 3950 2    39   ~ 0
I2C_SDA_Clk
Text Label 10650 3900 2    39   ~ 0
I2C_SCL_Clk
Wire Wire Line
	10650 3950 9950 3950
Wire Wire Line
	10650 3900 9950 3900
Text Label 10650 3750 2    39   ~ 0
Clk_LoL
Text Label 10650 3700 2    39   ~ 0
Clk_OK
Wire Wire Line
	10650 3750 9950 3750
Wire Wire Line
	10650 3700 9950 3700
Text Label 10650 3800 2    39   ~ 0
Clk_Rstb
Wire Wire Line
	10650 3800 9950 3800
Text Label 7000 2175 2    39   ~ 0
I2C_SDA_Clk
Text Label 7000 2100 2    39   ~ 0
I2C_SCL_Clk
Text Label 7000 2400 2    39   ~ 0
Clk_LoL
Text Label 7000 2325 2    39   ~ 0
Clk_OK
Text Label 7000 2250 2    39   ~ 0
Clk_Rstb
Wire Notes Line
	625  3025 2975 3025
Wire Notes Line
	2975 3025 2975 4600
Wire Notes Line
	2975 4600 650  4600
Wire Notes Line
	625  4600 625  3025
Text Notes 1375 3200 0    118  ~ 0
Laser Side
$Sheet
S 1250 3375 1175 850 
U 5EAC3343
F0 "trigger_laser" 50
F1 "trigger_laser.sch" 50
F2 "FB_PIN[1..2]" O R 2425 3550 39 
F3 "Laser_trigger[1..8]" I L 1250 3550 39 
$EndSheet
Text Label 10600 1000 2    39   ~ 0
PwupRstb
Wire Wire Line
	10600 1000 10050 1000
Text Label 650  2375 0    39   ~ 0
TP_trigger
Wire Wire Line
	1250 2375 650  2375
Wire Wire Line
	1450 6825 1550 6825
$Comp
L power:+6V #PWR0101
U 1 1 5F053C39
P 1550 6825
F 0 "#PWR0101" H 1550 6675 50  0001 C CNN
F 1 "+6V" H 1525 7000 50  0000 C CNN
F 2 "" H 1550 6825 50  0001 C CNN
F 3 "" H 1550 6825 50  0001 C CNN
	1    1550 6825
	1    0    0    -1  
$EndComp
Connection ~ 1550 6825
Wire Wire Line
	1550 6825 1850 6825
Wire Bus Line
	4650 2350 4025 2350
Text Label 4025 2350 0    39   ~ 0
ADC_GPIO1[1..2]
Text Label 6975 1325 2    39   ~ 0
Dum_out_P[1..2]
Wire Bus Line
	6975 1325 6350 1325
Text Label 6975 1400 2    39   ~ 0
Dum_out_N[1..2]
Wire Bus Line
	6975 1400 6350 1400
Wire Wire Line
	7000 2250 6350 2250
Wire Wire Line
	7000 2325 6350 2325
Wire Wire Line
	7000 2400 6350 2400
Wire Wire Line
	7000 2100 6350 2100
Wire Wire Line
	7000 2175 6350 2175
Wire Bus Line
	6350 2000 7000 2000
Wire Bus Line
	6350 1925 7000 1925
Wire Wire Line
	6350 1825 6975 1825
Wire Wire Line
	6350 1750 6975 1750
Wire Wire Line
	6350 1675 6975 1675
Wire Wire Line
	6350 1600 6975 1600
Wire Wire Line
	6350 1525 6975 1525
Text Label 6975 1675 2    39   ~ 0
SFP_Tx_Fault
Text Label 8375 1250 0    39   ~ 0
Dum_out_P[1..2]
Wire Bus Line
	8375 1250 9000 1250
Text Label 8375 1300 0    39   ~ 0
Dum_out_N[1..2]
Wire Bus Line
	8375 1300 9000 1300
Text Label 8375 1375 0    39   ~ 0
PllLock_out[1..7]
Wire Bus Line
	8375 1375 9000 1375
Wire Bus Line
	2450 2125 2925 2125
Text Label 2925 2125 2    39   ~ 0
PllLock_in[1..7]
Wire Bus Line
	4650 2425 4025 2425
Text Label 4025 2425 0    39   ~ 0
PllLock_in[1..7]
Wire Bus Line
	6350 2475 6975 2475
Text Label 6975 2475 2    39   ~ 0
PllLock_out[1..7]
Text Label 7000 2550 2    39   ~ 0
Pg[1..6]
Wire Bus Line
	6350 2550 7000 2550
Text Label 8375 1500 0    39   ~ 0
Pg[1..6]
Wire Bus Line
	9000 1500 8375 1500
Text Label 7000 2625 2    39   ~ 0
En[1..2]
Wire Bus Line
	6350 2625 7000 2625
Text Label 8375 1550 0    39   ~ 0
En[1..2]
Wire Bus Line
	9000 1550 8375 1550
Wire Wire Line
	10600 1075 10050 1075
Text Label 10600 1125 2    39   ~ 0
ReSync_in_N
Wire Wire Line
	10600 1125 10050 1125
Text Label 10600 1075 2    39   ~ 0
ReSync_in_P
Wire Wire Line
	7000 2700 6350 2700
Text Label 7000 2775 2    39   ~ 0
ReSync_in_N
Wire Wire Line
	7000 2775 6350 2775
Text Label 7000 2700 2    39   ~ 0
ReSync_in_P
Text Label 4025 2775 0    39   ~ 0
ReSync_out_P
Wire Wire Line
	4650 2775 4025 2775
Text Label 4025 2850 0    39   ~ 0
ReSync_out_N
Wire Wire Line
	4650 2850 4025 2850
Text Label 650  3550 0    39   ~ 0
Laser_trigger[1..8]
Text Label 4025 2925 0    39   ~ 0
Laser_trigger[1..8]
Text Label 4025 3000 0    39   ~ 0
FB_PIN[1..2]
Text Label 2875 3550 2    39   ~ 0
FB_PIN[1..2]
Wire Bus Line
	4650 2925 4025 2925
Wire Bus Line
	4025 3000 4650 3000
Wire Bus Line
	2875 3550 2425 3550
Wire Bus Line
	1250 3550 650  3550
$EndSCHEMATC