oddr_x2.v
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2 */
/* Module Version: 5.8 */
/* /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n oddr_x2 -lang verilog -synth lse -bus_exp 7 -bb -arch sa5p00 -type iol -mode Transmit -io_type LVCMOS18 -width 5 -freq_in 125 -gear 4 -del -1 -fdc /home/greg/projects/diamond_test/pll/oddr_x2/oddr_x2.fdc  */
/* Sun Feb 17 16:01:30 2019 */


// ============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2013 Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement 
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation      TEL  : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                           408-826-6000 (other locations)
// Hillsboro, OR 97124                    web  : http://www.latticesemi.com/
// U.S.A                                  email: techsupport@latticesemi.com
// =============================================================================
// Module     : gddr_sync.v
// Description: 
//   - Code for bus synchronization
//   - Needed to tolerate large skew between stop and ddr and clkdiv reset
// =============================================================================

`timescale 1ns/1ps

module oddr_x2gddr_sync (
  // inputs
  rst,             // Asynchronous reset
  sync_clk,        // oscillator clk or other constant running low speed clk.
                   // note that this clk should not be coming from clk sources 
                   // that this module will stop or reset (e.g. ECLKSYNC, CLKDIV)
  start,           // Initialize the sync process

  // outputs
  stop,            // ECLKSYNC.stop signal
  ddr_reset,       // DDR and CLKDIV reset signal
  ready            // READY signal; clock sync is done.
);

//-----------------------------------------------------------------------------
// PORTS DECLARATIONS
//----------------------------------------------------------------------------- 
// input ports
input       rst;
input       sync_clk;
input       start;

// output ports
output      stop;
output      ddr_reset;
output      ready;

//-----------------------------------------------------------------------------
// PARAMETERS
//-----------------------------------------------------------------------------        
// Local parameters: States
localparam INIT   = 3'b000;
localparam STOP   = 3'b001;
localparam RESET  = 3'b011;
localparam READY  = 3'b100;

//----------------------------------------------------------------------------- 
// SIGNAL DECLARATIONS
//-----------------------------------------------------------------------------  
wire        rst;
wire        sync_clk;
wire        start;
wire        ddr_reset;     
wire        stop;
wire        ready;

reg         ddr_reset_d;
reg   [3:0] ctrl_cnt;                                    // control counter
reg   [2:0] stop_assert;                                 // stop signal counter
reg   [2:0] cs_gddr_sync /*synthesis syn_preserve=1*/ ;  // current state
reg   [2:0] ns_gddr_sync;                                // next state
reg         reset_flag;                                  // flag signal that 
                                                         // indicates that RESET 
                                                         // is already done
  
//----------------------------------------------------------------------------- 
//  WIRE ASSIGNMENTS
//-----------------------------------------------------------------------------       
assign stop      = cs_gddr_sync[0];              
assign ddr_reset = cs_gddr_sync[1] | ddr_reset_d;
assign ready     = cs_gddr_sync[2];

//----------------------------------------------------------------------------- 
//  REGISTER ASSIGNMENTS
//-----------------------------------------------------------------------------  
always @(posedge sync_clk or posedge rst) begin
  if (rst==1'b1)
  begin
    cs_gddr_sync  <= INIT;
    ctrl_cnt      <= 4'd0;
    stop_assert   <= 3'd0;
    reset_flag    <= 1'b0;
    ddr_reset_d   <= 1'b1;
  end
  else
  begin
    cs_gddr_sync  <= ns_gddr_sync;
    ddr_reset_d   <= 1'b0;

    // CTRL_CNT for state machines        
    if (((cs_gddr_sync==INIT)&&(reset_flag==1'b0))||((ctrl_cnt == 3)
         &&(cs_gddr_sync!=INIT)))    
    begin          
      ctrl_cnt <= 'd0;
    end
    else if (ctrl_cnt < 8)
    begin          
      ctrl_cnt <= ctrl_cnt + 1;
    end
        
    // STOP signal will then be asserted 4T after rstn
    if ((!rst)&&(start)&&(stop_assert<4)&&(reset_flag==1'b0))               
    begin            
      stop_assert <= stop_assert + 1;
    end

    // Asserts the reset_flag after RESET state
    if ((cs_gddr_sync==RESET)&&(ns_gddr_sync == STOP))    
    begin
      reset_flag <= 1'b1;            
    end

    // Deasserts the reset_flag after READY state            
    if ((cs_gddr_sync==READY)&&(ns_gddr_sync == INIT))    
    begin
      reset_flag <= 1'b0;            
    end                    
  end
end

// GDDR_SYNC State machine    
always @(*) begin
  
  case (cs_gddr_sync)  /* synthesis full_case parallel_case */
    INIT:  // INIT state 0
    begin
      if ((start)&&(stop_assert==3)&&(reset_flag==1'b0))
      begin
        ns_gddr_sync = STOP;
      end
      else if ((reset_flag==1'b1)&&(ctrl_cnt == 7)&&(start))
      begin
        ns_gddr_sync = READY;
      end
      else
      begin
        ns_gddr_sync = INIT;
      end
    end
    
    STOP:  //STOP state 1
    begin
      if (ctrl_cnt == 3)
      begin
        if (reset_flag ==1'b1)
        begin
          ns_gddr_sync  = INIT;
        end
        else
        begin
          ns_gddr_sync  = RESET;
        end
      end
      else
      begin
        ns_gddr_sync = STOP;
      end
    end    
    
    RESET:  // RESET state 2
    begin
      if (ctrl_cnt == 3)
      begin
        ns_gddr_sync = STOP;
      end
      else
      begin
        ns_gddr_sync = RESET;
      end
    end
    
    READY:  // READY state 5
    begin
      if ((!start))
      begin
        ns_gddr_sync = INIT;
      end
      else
      begin
        ns_gddr_sync = READY;
      end
    end
    
    default:
    begin
      ns_gddr_sync = cs_gddr_sync;
    end
    
  endcase
end
  
endmodule // oddr_x2gddr_sync


`timescale 1 ns / 1 ps
module oddr_eth_x2 (clkop, clkos, clkout, ready, sclk, start, sync_clk, 
    sync_reset, data, dout, ctrl, ctrlout)/* synthesis NGD_DRC_MASK=1 */;
    input wire clkop;
    input wire clkos;
    input wire start;
    input wire sync_clk;
    input wire sync_reset;
    input wire [15:0] data;
    output wire clkout;
    output wire ready;
    output wire sclk;
    output wire [3:0] dout;

    input wire [3:0] ctrl;
    output wire ctrlout;

    wire ctrl_a4;
    wire ctrl_b4;
    wire ctrl_c4;
    wire ctrl_d4;
    wire da3;
    wire db3;
    wire dc3;
    wire dd3;
    wire da2;
    wire db2;
    wire dc2;
    wire dd2;
    wire da1;
    wire db1;
    wire dc1;
    wire dd1;
    wire da0;
    wire db0;
    wire dc0;
    wire dd0;
    wire scuba_vhi;
    wire sclk_t;
    wire scuba_vlo;
    wire reset;
    wire eclko;
    wire ecsout;
    wire stop;
    wire buf_clkout;
    wire buf_clkout_t0;
    wire buf_douto4;
    wire buf_douto3;
    wire buf_douto2;
    wire buf_douto1;
    wire buf_douto0;

    oddr_x2gddr_sync Inst_gddr_sync (.rst(sync_reset), .sync_clk(sync_clk), 
        .start(start), .stop(stop), .ddr_reset(reset), .ready(ready));

    ODDRX2F Inst6_ODDRX2F4 (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(ctrl_d4), 
        .D2(ctrl_c4), .D1(ctrl_b4), .D0(ctrl_a4), .Q(buf_ctrlouto4_t0));

    ODDRX2F Inst6_ODDRX2F3 (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(dd3), 
        .D2(dc3), .D1(db3), .D0(da3), .Q(buf_douto3_t0));

    ODDRX2F Inst6_ODDRX2F2 (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(dd2), 
        .D2(dc2), .D1(db2), .D0(da2), .Q(buf_douto2_t0));

    ODDRX2F Inst6_ODDRX2F1 (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(dd1), 
        .D2(dc1), .D1(db1), .D0(da1), .Q(buf_douto1_t0));

    ODDRX2F Inst6_ODDRX2F0 (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(dd0), 
        .D2(dc0), .D1(db0), .D0(da0), .Q(buf_douto0_t0));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    ODDRX2F Inst5_ODDRX2F (.SCLK(sclk_t), .ECLK(eclko), .RST(reset), .D3(scuba_vlo), 
        .D2(scuba_vhi), .D1(scuba_vlo), .D0(scuba_vhi), .Q(buf_clkout_t0));

    defparam udel_douto5.DEL_VALUE = 65 ;
    defparam udel_douto5.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto5 (.A(buf_clkout_t0), .Z(buf_clkout));

        //ODDRX1F Inst5_ODDRX1F (.SCLK(clkos), .RST(reset), .D1(scuba_vhi), .D0(scuba_vlo), .Q(buf_clkout));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam Inst4_CLKDIVF.DIV = "2.0" ;
    CLKDIVF Inst4_CLKDIVF (.CLKI(eclko), .RST(reset), .ALIGNWD(scuba_vlo), 
        .CDIVX(sclk_t));

    ECLKSYNCB Inst3_ECLKSYNCB (.ECLKI(ecsout), .STOP(stop), .ECLKO(eclko));

    ECLKBRIDGECS Inst_ECLKBRIDGECS (.CLK0(clkop), .CLK1(scuba_vlo), .SEL(scuba_vlo), 
        .ECSOUT(ecsout));

    OB Inst2_OB (.I(buf_clkout), .O(clkout))
             /* synthesis IO_TYPE="LVCMOS18" */;

    defparam udel_douto4.DEL_VALUE = 0 ;
    defparam udel_douto4.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto4 (.A(buf_ctrlouto4_t0), .Z(buf_ctrlouto4));

    OB Inst1_OB4 (.I(buf_ctrlouto4), .O(ctrlout))
             /* synthesis IO_TYPE="LVCMOS18" */;

    defparam udel_douto3.DEL_VALUE = 40 ;
    defparam udel_douto3.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto3 (.A(buf_douto3_t0), .Z(buf_douto3));

    OB Inst1_OB3 (.I(buf_douto3), .O(dout[3]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    defparam udel_douto2.DEL_VALUE = 40 ;
    defparam udel_douto2.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto2 (.A(buf_douto2_t0), .Z(buf_douto2));

    OB Inst1_OB2 (.I(buf_douto2), .O(dout[2]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    defparam udel_douto1.DEL_VALUE = 40 ;
    defparam udel_douto1.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto1 (.A(buf_douto1_t0), .Z(buf_douto1));

    OB Inst1_OB1 (.I(buf_douto1), .O(dout[1]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    defparam udel_douto0.DEL_VALUE = 40 ;
    defparam udel_douto0.DEL_MODE = "USER_DEFINED" ;
    DELAYG udel_douto0 (.A(buf_douto0_t0), .Z(buf_douto0));

    OB Inst1_OB0 (.I(buf_douto0), .O(dout[0]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    assign sclk = sclk_t;
    assign dd3 = data[15];
    assign dd2 = data[14];
    assign dd1 = data[13];
    assign dd0 = data[12];
    assign dc3 = data[11];
    assign dc2 = data[10];
    assign dc1 = data[9];
    assign dc0 = data[8];
    assign db3 = data[7];
    assign db2 = data[6];
    assign db1 = data[5];
    assign db0 = data[4];
    assign da3 = data[3];
    assign da2 = data[2];
    assign da1 = data[1];
    assign da0 = data[0];


    assign ctrl_d4 = ctrl[3];
    assign ctrl_c4 = ctrl[2];
    assign ctrl_b4 = ctrl[1];
    assign ctrl_a4 = ctrl[0];

    // exemplar begin
    // exemplar attribute Inst2_OB IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB4 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB3 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB2 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB1 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB0 IO_TYPE LVCMOS18
    // exemplar end

endmodule