Files
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hardware / ButterStick_r0.1 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.1 / ButterStick.sch
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hardware / ButterStick_r0.1 / fileEthernet.sch
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hardware / ButterStick_r0.1 / fileFPGA.sch
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hardware / ButterStick_r0.1 / fileHyperRAM.sch
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hardware / ButterStick_r0.1 / fileIO.sch
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hardware / ButterStick_r0.1 / filePower.sch
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hardware / ButterStick_r0.1 / fileSDMMC.sch
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hardware / ButterStick_r0.1 / SmartVIO.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.1 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.2 / ButterStick.sch
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hardware / ButterStick_r0.2 / fileEthernet.sch
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hardware / ButterStick_r0.2 / fileFPGA.sch
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hardware / ButterStick_r0.2 / fileHyperRAM.sch
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hardware / ButterStick_r0.2 / fileIO.sch
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hardware / ButterStick_r0.2 / filePower.sch
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hardware / ButterStick_r0.2 / fileSDMMC.sch
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hardware / ButterStick_r0.2 / PCBSpecs.sch
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hardware / ButterStick_r0.2 / SmartVIO.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.2 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / TestPonts.sch
Last update 5 years 7 months
by
Greg Davill
| FilesgatewareGigEeth | |
|---|---|
| .. | |
| verilog | |
| ecp5rgmii.py | |
| rgmii.py | |
| rgmii_x2.py |