oddr_x1.v
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2 */
/* Module Version: 5.8 */
/* /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n oddr_1x -lang verilog -synth lse -bus_exp 7 -bb -arch sa5p00 -type iol -mode Transmit -io_type LVCMOS18 -width 5 -freq_in 125 -gear 2 -aligned -del -1 -fdc /home/greg/projects/diamond_test/pll/oddr_1x/oddr_1x.fdc  */
/* Tue Jan 29 22:20:21 2019 */


`timescale 1 ns / 1 ps
module oddr_1x (clkout, refclk, reset, data, dout)/* synthesis NGD_DRC_MASK=1 */;
    input wire refclk;
    input wire reset;
    input wire [9:0] data;
    output wire clkout;
    output wire [4:0] dout;

    wire db4;
    wire da4;
    wire db3;
    wire da3;
    wire db2;
    wire da2;
    wire db1;
    wire da1;
    wire db0;
    wire da0;
    wire scuba_vlo;
    wire scuba_vhi;
    wire sclk_t;
    wire clkos;
    wire clkop;
    wire buf_clkout;
    wire buf_douto4;
    wire buf_douto3;
    wire buf_douto2;
    wire buf_douto1;
    wire buf_douto0;

    ODDRX1F Inst4_ODDRX1F4 (.SCLK(sclk_t), .RST(reset), .D0(da4), .D1(db4), 
        .Q(buf_douto4));

    ODDRX1F Inst4_ODDRX1F3 (.SCLK(sclk_t), .RST(reset), .D0(da3), .D1(db3), 
        .Q(buf_douto3));

    ODDRX1F Inst4_ODDRX1F2 (.SCLK(sclk_t), .RST(reset), .D0(da2), .D1(db2), 
        .Q(buf_douto2));

    ODDRX1F Inst4_ODDRX1F1 (.SCLK(sclk_t), .RST(reset), .D0(da1), .D1(db1), 
        .Q(buf_douto1));

    ODDRX1F Inst4_ODDRX1F0 (.SCLK(sclk_t), .RST(reset), .D0(da0), .D1(db0), 
        .Q(buf_douto0));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    ODDRX1F Inst3_ODDRX1F (.SCLK(clkos), .RST(reset), .D0(scuba_vhi), .D1(scuba_vlo), 
        .Q(buf_clkout));

    OB Inst2_OB (.I(buf_clkout), .O(clkout))
             /* synthesis IO_TYPE="LVCMOS18" */;

    OB Inst1_OB4 (.I(buf_douto4), .O(dout[4]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    OB Inst1_OB3 (.I(buf_douto3), .O(dout[3]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    OB Inst1_OB2 (.I(buf_douto2), .O(dout[2]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    OB Inst1_OB1 (.I(buf_douto1), .O(dout[1]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    OB Inst1_OB0 (.I(buf_douto0), .O(dout[0]))
             /* synthesis IO_TYPE="LVCMOS18" */;

    assign db4 = data[9];
    assign da4 = data[8];
    assign db3 = data[7];
    assign db2 = data[6];
    assign db1 = data[5];
    assign db0 = data[4];
    assign da3 = data[3];
    assign da2 = data[2];
    assign da1 = data[1];
    assign da0 = data[0];
    assign sclk_t = clkop;
    assign clkos = refclk;
    assign clkop = refclk;


    // exemplar begin
    // exemplar attribute Inst2_OB IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB4 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB3 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB2 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB1 IO_TYPE LVCMOS18
    // exemplar attribute Inst1_OB0 IO_TYPE LVCMOS18
    // exemplar end

endmodule