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FilesPCBEDU-FSLEDU_CIAA_K60
..
Datasheets
doc
footprints.3dshapes
footprints.pretty
kicadlibs
EDU_CIAA_K60.cmp
EDU_CIAA_K60.csv
EDU_CIAA_K60.kicad_pcb	view raw
EDU_CIAA_K60.kicad_pcb-bak
EDU_CIAA_K60.lst
EDU_CIAA_K60.net
EDU_CIAA_K60.pro
EDU_CIAA_K60.sch	view raw
EDU_CIAA_K60.xml
JTAG.sch	view raw
cpu.sch	view raw
fuente.sch	view raw
gpio.sch	view raw
on_board_io.sch	view raw
rsS485.sch	view raw
usb_otg.sch	view raw

EDU_CIAA_K60.proupdate=19/07/2016 8:22:24
version=1
last_client=kicad
[general]
version=1
[cvpcb]
version=1
NetIExt=net
[pcbnew]
version=1
LastNetListRead=EDU_CIAA_K60.net
UseCmpFile=0
PadDrill=0.825000000000
PadDrillOvalY=0.825000000000
PadSizeH=1.225000000000
PadSizeV=1.900000000000
PcbTextSizeV=1.000000000000
PcbTextSizeH=1.000000000000
PcbTextThickness=0.200000000000
ModuleTextSizeV=0.800000000000
ModuleTextSizeH=0.800000000000
ModuleTextSizeThickness=0.120000000000
SolderMaskClearance=0.025400000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.508000000000
ModuleOutlineThickness=0.150000000000
[pcbnew/libraries]
LibDir=footprints.pretty
LibName1=edu-ciaa-fsl
[eeschema]
version=1
LibDir=kicadlibs
[eeschema/libraries]
LibName1=edu-ciaa-fsl

schneider / test - Files

Files

PCB / ACC / CIAA_ACC / BANK_0.sch

PCB / ACC / CIAA_ACC / BANK_112.sch

PCB / ACC / CIAA_ACC / BANK_500.sch

PCB / ACC / CIAA_ACC / BANK_501.sch

PCB / ACC / CIAA_ACC / BANK_502.sch

PCB / ACC / CIAA_ACC / BANKS_HP.sch

PCB / ACC / CIAA_ACC / BANKS_HR.sch

PCB / ACC / CIAA_ACC / ciaa_acc.kicad_pcb

PCB / ACC / CIAA_ACC / ciaa_acc.sch

PCB / ACC / CIAA_ACC / Digital_IO.sch

PCB / ACC / CIAA_ACC / Expansion.sch

PCB / ACC / CIAA_ACC / FMC-Power.sch

PCB / ACC / CIAA_ACC / FPGA-Power.sch

PCB / ACC / CIAA_ACC / OneBank.sch

PCB / ACC / CIAA_ACC / PMIC.sch

PCB / ACC / CIAA_ACC / Principal.sch

PCB / ACC / CIAA_ACC / RTC-HDMI.sch

PCB / EDU-FSL / EDU_CIAA_K60 / cpu.sch

PCB / EDU-FSL / EDU_CIAA_K60 / EDU_CIAA_K60.kicad_pcb

PCB / EDU-FSL / EDU_CIAA_K60 / EDU_CIAA_K60.sch

PCB / EDU-FSL / EDU_CIAA_K60 / fuente.sch

PCB / EDU-FSL / EDU_CIAA_K60 / gpio.sch

PCB / EDU-FSL / EDU_CIAA_K60 / JTAG.sch

PCB / EDU-FSL / EDU_CIAA_K60 / on_board_io.sch

PCB / EDU-FSL / EDU_CIAA_K60 / rsS485.sch

PCB / EDU-FSL / EDU_CIAA_K60 / usb_otg.sch

PCB / EDU-INTEL / cpu.sch

PCB / EDU-INTEL / edk.kicad_pcb

PCB / EDU-INTEL / edk.sch

PCB / EDU-INTEL / power.sch

PCB / EDU-INTEL / sd_card.sch

PCB / EDU-INTEL / usb.sch

PCB / EDU-NXP / cpu.sch

PCB / EDU-NXP / edu-ciaa-nxp.kicad_pcb

PCB / EDU-NXP / edu-ciaa-nxp.sch

PCB / EDU-NXP / fuente.sch

PCB / EDU-NXP / gpio.sch

PCB / EDU-NXP / ON_BOARD_IO.sch

PCB / EDU-NXP / rsS485_can.sch

PCB / EDU-NXP / usb.sch

PCB / EDU-XILINX / ProyectoKicad / Bank14.sch

PCB / EDU-XILINX / ProyectoKicad / Bank15.sch

PCB / EDU-XILINX / ProyectoKicad / Bank35.sch

PCB / EDU-XILINX / ProyectoKicad / EduCiaaX.sch

PCB / EDU-XILINX / ProyectoKicad / FPGAConfig.sch

PCB / EDU-XILINX / ProyectoKicad / FPGAPower.sch

PCB / EDU-XILINX / ProyectoKicad / Power.sch

PCB / EDU-XILINX / ProyectoKicad / Usb.sch

PCB / FSL-MINI / CIAA_FSL_MINI.kicad_pcb

PCB / FSL-MINI / CIAA_FSL_MINI.sch

PCB / FSL-MINI / cpu.sch

PCB / FSL-MINI / ethernet.sch

PCB / FSL-MINI / fuente.sch

PCB / FSL-MINI / IO.sch

PCB / FSL-MINI / memories.sch

PCB / FSL-MINI / usb_otg.sch

PCB / FSL / CIAA_K60 / analog.sch

PCB / FSL / CIAA_K60 / analog_out.sch

PCB / FSL / CIAA_K60 / CIAA_K60.kicad_pcb

PCB / FSL / CIAA_K60 / CIAA_K60.sch

PCB / FSL / CIAA_K60 / cpu.sch

PCB / FSL / CIAA_K60 / din.sch

PCB / FSL / CIAA_K60 / dout.sch

PCB / FSL / CIAA_K60 / ethernet.sch

PCB / FSL / CIAA_K60 / fuente.sch

PCB / FSL / CIAA_K60 / gpio.sch

PCB / FSL / CIAA_K60 / JTAG.sch

PCB / FSL / CIAA_K60 / memories.sch

PCB / FSL / CIAA_K60 / rsS485_rs232_can.sch

PCB / FSL / CIAA_K60 / usb_otg.sch

PCB / NXP / .kicad_pcb.kicad_pcb

PCB / NXP / analog.sch

PCB / NXP / analog_out.sch

PCB / NXP / ciaa-nxp.kicad_pcb

PCB / NXP / ciaa-nxp.sch

PCB / NXP / cpu.sch

PCB / NXP / din.sch

PCB / NXP / dout.sch