Files
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded.PcbDoc
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded_panel.PcbDoc
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hardware / 1v0 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v0 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v0 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v0 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v0 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v0 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v0 / Schematics / 07_FPGA.SchDoc
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hardware / 1v0 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v0 / Schematics / 09_Misc.SchDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_panel.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_soldermask.PcbDoc
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hardware / 1v1 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v1 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v1 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v1 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v1 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v1 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v1 / Schematics / 07_FPGA.SchDoc
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hardware / 1v1 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v1 / Schematics / 09_Misc.SchDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded.PcbDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded_panel.PcbDoc
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hardware / 1v2 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v2 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v2 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v2 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v2 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v2 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v2 / Schematics / 07_FPGA.SchDoc
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hardware / 1v2 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v2 / Schematics / 09_Misc.SchDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_old.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_panel.PcbDoc
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hardware / 1v3 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v3 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v3 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v3 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v3 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v3 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v3 / Schematics / 07_FPGA.SchDoc
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hardware / 1v3 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v3 / Schematics / 09_Misc.SchDoc
Last update 1 year 8 months
by
usama.bashir.cowlar@gmail.com
Status Report.TxtOutput: Electrical Rules Check Type : ERC From : Project [LimeSDR_Mini_1v0.PrjPcb] Generated File[LimeSDR_Mini_1v0.html] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 12:20:39 On 2017-09-22