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JARS 2_0
JARS_receiver-cache.lib
JARS_receiver-rescue.lib
JARS_receiver.csv
JARS_receiver.kicad_pcb
JARS_receiver.kicad_pcb-bak
JARS_receiver.net
JARS_receiver.pro
JARS_receiver.rpt
JARS_receiver.sch
JARS_receiver.sch-bak
README.md
fp-info-cache
fp-lib-table
sym-lib-table
README.md

PCB JARS 2.0

The latest data acquisition system running at the Jicamarca Radio Observatory for the main radar has been used for more than five years now. Although there are no major inconveniences on the performance there have been some problems with internal interferences which are usually unpredictable and related to the PCB design, the noise floor can be different between channels too. So there are some chances of improvement developing a new approach. We propose a new design based on a high-speed JESD204B data interface; the digital signal processing and custom acquisition logic will be implemented inside an FPGA capable of managing the JESD204B high-speed interface. This will give us the flexibility of implementing digital blocks inside the FPGA to improve the performance of the receivers, we will gain scalability to perform on a much higher bandwidth and the PCB will be very much simplified which will reduce the manufacturing costs, design time, and development time.

The poster has been presented in 2021 CEDAR Virtual Workshop

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