revC3: Adjusted button footprint to reflect selected tact switch.

revC3: Updated resistor pack footprint. This change is based on battle proven footprint used in 1BitSquared board designs. This makes the gaps between pads consistent 0.22mm to pass PCB manufacturer automated DRC and receive solder stop between pads decreasing solder bridging probability during assembly.

revC3: Updated to the new stable KiCad V6. This includes updating the KiCad system 3D model library path variable.

revC3: Decreased LVDS connector alignment hole to 0.76mm We noticed that the selected alignment hole size allowed for too much movement of the LVDS connector. The alignment pin is 0.65mm diameter and Samtec recommends a hole of 0.76mm diameter.

revC3: Updated LEDs and current limiting resistors. * New status LED color scheme: PWR/GRN, FX2/WHT, ICE/BLU, ACT/ORA, ERR/RED * Updated LED part numbers and the corresponding resistor values. * All LED sourcable from LCSC.

revC3: add an 4.7µF capacitor to VIO_AUX for improved decoupling VIO_AUX is the IO voltage for the LVDS connector. If it is used with high speed signals (like for example connecting to fast RAM), the existing 100n decoupling may not be enough. Also add some more vias to the VIO_AUX trace for lower inductance. Unfortunately placing the capacitor nearer to the FPGA would require major rerouting. This is not done here for fear of adding new issues.

revC3: add pin 1 marker to silkscreen for LVDS header

revC3: connect the 3v3 pin of the LVDS connector with a second via Power traces should be connected with at least two vias for lower impedance and improved reliability. On the other instances this was already addressed in revC2, this one was missed. Without this improvement the planned Hyperram addon for the LVDS connector could get a power problem because 2 active Hyperram ICs draw in the order of 100 mA through the 3v3 pin.

revC3: change URL on back silkscreen to https

revC3: add URL to back silkscreen, resize VDAC labels on back silkscreen