Gregory Davill / ButterStick - Files

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    Last update 4 years 11 months
    FileshardwareButterStick_r0.2
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    bom
    output
    ButterStick-cache.lib
    ButterStick.kicad_pcb
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    ButterStick.pro
    ButterStick.sch
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    PCBSpecs.sch
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    SYZYGY_PORT0.sch
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    SYZYGY_PORT1.sch
    view raw
    SYZYGY_PORT2.sch
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    SmartVIO.sch
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    SyzygyStandard.sch
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    TestPonts.sch
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    fileEthernet.sch
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    fileFPGA.sch
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    fileHyperRAM.sch
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    fileIO.sch
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    filePower.sch
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    fileSDMMC.sch
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    fp-info-cache
    fp-lib-table
    sym-lib-table
    		 
    ButterStick.pro
    update=Fri 31 May 2019 21:36:18 ACST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=plot/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=6
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.08889999999999999
MinViaDiameter=0.45
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1
TrackWidth2=0.0889
TrackWidth3=0.1
TrackWidth4=0.10033
TrackWidth5=0.1016
TrackWidth6=0.10414
TrackWidth7=0.12
TrackWidth8=0.15
TrackWidth9=0.2
TrackWidth10=0.25
TrackWidth11=0.254
TrackWidth12=0.3
TrackWidth13=0.4
ViaDiameter1=0.45
ViaDrill1=0.2
ViaDiameter2=0.45
ViaDrill2=0.2
ViaDiameter3=0.53
ViaDrill3=0.25
dPairWidth1=0.1
dPairGap1=0.1
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=0
SilkTextSizeH=0
SilkTextSizeThickness=0
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.09999999999999999
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.035
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.035
SolderPasteRatio=-0
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=1
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=1
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=ETHERNET_LM0.125
Clearance=0.08895
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1
dPairGap=0.08895
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=HYPERBUS_LM0.2
Clearance=0.08895
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1
dPairGap=0.08895
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=SYZYGY_0_DP0.05/0.10
Clearance=0.08895
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1
dPairGap=0.2032
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=SYZYGY_1_DP0.05/0.10
Clearance=0.08895
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1
dPairGap=0.2032
dPairViaGap=0.25
[pcbnew/Netclasses/5]
Name=SYZYGY_2_DP0.05/0.10
Clearance=0.1
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1
dPairGap=0.2032
dPairViaGap=0.25
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