Files
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hardware / ButterStick_r0.1 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.1 / ButterStick.sch
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hardware / ButterStick_r0.1 / fileEthernet.sch
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hardware / ButterStick_r0.1 / fileFPGA.sch
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hardware / ButterStick_r0.1 / fileHyperRAM.sch
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hardware / ButterStick_r0.1 / fileIO.sch
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hardware / ButterStick_r0.1 / filePower.sch
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hardware / ButterStick_r0.1 / fileSDMMC.sch
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hardware / ButterStick_r0.1 / SmartVIO.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.1 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.2 / ButterStick.sch
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hardware / ButterStick_r0.2 / fileEthernet.sch
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hardware / ButterStick_r0.2 / fileFPGA.sch
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hardware / ButterStick_r0.2 / fileHyperRAM.sch
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hardware / ButterStick_r0.2 / fileIO.sch
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hardware / ButterStick_r0.2 / filePower.sch
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hardware / ButterStick_r0.2 / fileSDMMC.sch
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hardware / ButterStick_r0.2 / PCBSpecs.sch
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hardware / ButterStick_r0.2 / SmartVIO.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.2 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / TestPonts.sch
Last update 4 years 10 months
| Files | |
|---|---|
| documentation | |
| gateware | |
| hardware | |
| lib | |
| .gitignore | |
| .gitmodules | |
| README.md |
.gitmodules[submodule "lib/gkl"] path = lib/gkl url = https://github.com/gregdavill/gsd-kicad-libs [submodule "lib/pkl"] path = lib/pkl url = https://github.com/esden/pretty-kicad-libs [submodule "lib/kicad-length-matching-checks"] path = lib/kicad-length-matching-checks url = https://github.com/mithro/kicad-length-matching-checks