lpc54102j512bd64.lib
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# LPC54102J512BD64
#
DEF LPC54102J512BD64 U 0 40 Y Y 1 F N
F0 "U" -2400 2150 60 H V C CNN
F1 "LPC54102J512BD64" -2000 -2150 60 H V C CNN
F2 "" -700 300 60 H V C CNN
F3 "" -700 300 60 H V C CNN
DRAW
S -2450 2100 2400 -2100 0 1 0 f
X P0_23/I2C0_SCL//CT32B0_CAP0/EZH_23 1 -2650 -500 200 R 50 50 1 1 B
X P0_24/I2C0_SDA//CT32B0_CAP1/EZH_24/CT32B0_MAT0 2 -2650 -600 200 R 50 50 1 1 B
X P0_25/I2C1_SCL/U1_CTS/CT32B0_CAP2/EZH_25/CT32B1_CAP1 3 -2650 -700 200 R 50 50 1 1 B
X P0_26/I2C1_SDA//CT32B0_CAP3/EZH_26 4 -2650 -800 200 R 50 50 1 1 B
X P0_27/I2C2_SCL//CT32B2_CAP0/EZH_27 5 -2650 -900 200 R 50 50 1 1 B
X P0_28/I2C2_SDA//CT32B2_MAT0/EZH_28 6 -2650 -1000 200 R 50 50 1 1 B
X P1_16/R/CT32B0_MAT0/CT32B0_CAP0/SPI1_SSEL1 7 2600 200 200 L 50 50 1 1 B
X VDD_0 8 2600 -150 200 L 50 50 1 1 W
X VSS_0 9 2600 -1100 200 L 50 50 1 1 W
X PIO1_17 10 2600 100 200 L 50 50 1 1 B
X VSSA 20 2600 -1500 200 L 50 50 1 1 W
X P1_10/R/U1_TXD/SCT_OUT4 30 2600 800 200 L 50 50 1 1 B
X P0_6/U1_TXD//CT32B0_MAT1/EZH_6 40 -2650 1200 200 R 50 50 1 1 B
X P0_15/SPI0_SSEL1/SWO/CT32B2_MAT2/EZH_15///TDO 50 -2650 300 200 R 50 50 1 1 B
X P0_20/U3_RXD/U0_SCLK/CT32B3_CAP0/EZH_20///TMS 60 -2650 -200 200 R 50 50 1 1 B
X P0_29/ADC_0/SCT_OUT2/CT32B0_MAT3/EZH_29/CT32B0_CAP1/CT32B0_MAT1 11 -2650 -1100 200 R 50 50 1 1 B
X VREFN 21 2600 -1600 200 L 50 50 1 1 W
X P0_0/U0_RXD/SPI0_SSEL0/CT32B0_CAP0/EZH_0/SCT_OUT3 31 -2650 1800 200 R 50 50 1 1 B
X P0_7/U1_SCLK/SCT_OUT0/CT32B0_MAT2/EZH_7/CT32B0_CAP2 41 -2650 1100 200 R 50 50 1 1 B
X P1_12/R/U3_RXD/CT32B1_MAT0/SPI1_SCK 51 2600 600 200 L 50 50 1 1 B
X P0_21/CLKOUT/U0_TXD/CT32B3_MAT0EZH_21 61 -2650 -300 200 R 50 50 1 1 B
X P0_30/ADC_1/SCT_OUT3/CT32B0_MAT2EZH_30/CT32B0_CAP2 12 -2650 -1200 200 R 50 50 1 1 B
X VREFP 22 2600 -850 200 L 50 50 1 1 W
X P0_1/U0_TXD/SPI0_SSEL1/CT32B0_CAP1/EZH_1/SCT_OUT1 32 -2650 1700 200 R 50 50 1 1 B
X P1_11/R/U1_RTS/CT32B1_CAP0 42 2600 700 200 L 50 50 1 1 B
X P0_16/SPI0_SSEL2/U1_CTSn/CT32B3_MAT1/EZH_16/SWCLK 52 -2650 200 200 R 50 50 1 1 B
X P1_15/R/SCT_OUT5/CT32B1_CAP3/SPI1_SSEL0 62 2600 300 200 L 50 50 1 1 B
X P0_31/ADC_2/U2_CTSn/CT32B2_CAP2/EZH_31/CT32B0_CAP3/CT32B0_MAT3 13 -2650 -1300 200 R 50 50 1 1 B
X VDDA 23 2600 -750 200 L 50 50 1 1 W
X RTCXIN 33 -2650 -1600 200 R 50 50 1 1 B
X P0_8/U2_RXD/SCT_OUT1/CT32B0_MAT3/EZH_8 43 -2650 1000 200 R 50 50 1 1 B
X P0_17/SPI0_SSEL3/U1_RTSn/CT32B3_MAT2/EZH_17/SWDIO 53 -2650 100 200 R 50 50 1 1 B
X P0_22/CLKIN/U0_RXD/CT32B3_MAT3/EZH_22 63 -2650 -400 200 R 50 50 1 1 B
X P1_0/ADC_3/U2_RTS/CT32B3_MAT1/CT32B0_CAP0 14 2600 1800 200 L 50 50 1 1 B
X VDD_1 24 2600 -250 200 L 50 50 1 1 W
X VDD_2 34 2600 -350 200 L 50 50 1 1 W
X P0_9/U2_TXD/SCT_OUT2/CT32B3_CAP0/EZH_9/SPI0_SSEL0 44 -2650 900 200 R 50 50 1 1 B
X P1_13/R/U3_TXD/CT32B1_MAT1/SPI1_MOSI 54 2600 500 200 L 50 50 1 1 B
X RESETn 64 -2650 2000 200 R 50 50 1 1 I
X P1_1/ADC_4/SWO/SCT_OUT4 15 2600 1700 200 L 50 50 1 1 B
X VSS_1 25 2600 -1200 200 L 50 50 1 1 W
X RTCXOUT 35 -2650 -2000 200 R 50 50 1 1 B
X P0_10/U2_SCLK/SCT_OUT3/CT32B3_MAT0/EZH_10 45 -2650 800 200 R 50 50 1 1 B
X VSS_2 55 2600 -1300 200 L 50 50 1 1 W
X P1_2/ADC_5/SPI1_SSEL3/SCT_OUT5/ 16 2600 1600 200 L 50 50 1 1 B
X P1_6/ADC_9/SPI1_SCK/CT32B1_CAP2//CT32B1_MAT2 26 2600 1200 200 L 50 50 1 1 B
X P0_2/U0_CTS/R/CT32B2_CAP1/R 36 -2650 1600 200 R 50 50 1 1 B
X P0_11/SPI0_SCK/U1_RXD/CT32B2_MAT1/EZH_11 46 -2650 700 200 R 50 50 1 1 B
X VDD_3 56 2600 -450 200 L 50 50 1 1 W
X P1_3/ADC_6/SPI1_SSEL2/SCT_OUT6//SPI0_SCK/CT32B0_CAP1 17 2600 1500 200 L 50 50 1 1 B
X P1_7/ADC_10/SPI1_MOSI/CT32B1_MAT2//CT32B1_CAP2 27 2600 1100 200 L 50 50 1 1 B
X P0_3/U0_RTS/R/CT32B1_MAT3/R 37 -2650 1500 200 R 50 50 1 1 B
X P0_12/SPI0_MOSI/U1_TXD/CT32B2_MAT3/EZH_12 47 -2650 600 200 R 50 50 1 1 B
X P1_14/R/U2_RXD/SCT_OUT7/SPI1_MISO 57 2600 400 200 L 50 50 1 1 B
X P1_4/ADC_7/SPI1_SSEL1/SCT_OUT7//SPI0_MISO/CT32B0_MAT1 18 2600 1400 200 L 50 50 1 1 B
X P1_8/ADC_11/SPI1_MISO/CT32B1_MAT3//CT32B1_CAP3 28 2600 1000 200 L 50 50 1 1 B
X P0_4/U0_SCLK/SPI0_SSEL2/CT32B0_CAP2/EZH_4 38 -2650 1400 200 R 50 50 1 1 B
X P0_13/SPI0_MISO/SCT_OUT4/CT32B2_MAT0/EZH_13 48 -2650 500 200 R 50 50 1 1 B
X P0_18/U3_TXD/SCT_OUT0/CT32B0_MAT0/EZH_18///TRSTn 58 -2650 0 200 R 50 50 1 1 B
X P1_5/ADC_8/SPI1_SSEL0/CT32B1_CAP0//CT32B1_MAT3 19 2600 1300 200 L 50 50 1 1 B
X P1_9/R/SPI0_MOSI/CT32B0_CAP2 29 2600 900 200 L 50 50 1 1 B
X P0_5/U1_RXD/SCT_OUT6/CT32B0_MAT0/EZH_5 39 -2650 1300 200 R 50 50 1 1 B
X P0_14/SPI0_SSEL0/SCT_OUT5/CT32B2_MAT1/EZH_14///TCK 49 -2650 400 200 R 50 50 1 1 B
X P0_19/U3_SCLK/SCT_OUT1/CT32B0_MAT1/EZH_19///TDI 59 -2650 -100 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library