Files
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hardware / ButterStick_r0.1 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.1 / ButterStick.sch
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hardware / ButterStick_r0.1 / fileEthernet.sch
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hardware / ButterStick_r0.1 / fileFPGA.sch
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hardware / ButterStick_r0.1 / fileHyperRAM.sch
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hardware / ButterStick_r0.1 / fileIO.sch
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hardware / ButterStick_r0.1 / filePower.sch
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hardware / ButterStick_r0.1 / fileSDMMC.sch
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hardware / ButterStick_r0.1 / SmartVIO.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.1 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.1 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / ButterStick.kicad_pcb
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hardware / ButterStick_r0.2 / ButterStick.sch
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hardware / ButterStick_r0.2 / fileEthernet.sch
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hardware / ButterStick_r0.2 / fileFPGA.sch
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hardware / ButterStick_r0.2 / fileHyperRAM.sch
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hardware / ButterStick_r0.2 / fileIO.sch
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hardware / ButterStick_r0.2 / filePower.sch
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hardware / ButterStick_r0.2 / fileSDMMC.sch
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hardware / ButterStick_r0.2 / PCBSpecs.sch
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hardware / ButterStick_r0.2 / SmartVIO.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT0.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT1.sch
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hardware / ButterStick_r0.2 / SYZYGY_PORT2.sch
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hardware / ButterStick_r0.2 / SyzygyStandard.sch
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hardware / ButterStick_r0.2 / TestPonts.sch
Last update 5 years 6 months
by
Greg Davill
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documentation | |
gateware | |
hardware | |
lib | |
.gitignore | |
.gitmodules | |
README.md |
README.mdButterStick
A simple FPGA board for experiments with high speed LVDS interfaces. 3 Standard connectors with an onboard GigE link.
Still in active Development (Use stuff here if you want, but there is no support.)
Hardware
- ECP5
- Gigabit Ethernet
- 256Mbit PSRAM (Dual HyperRAM upto 166MHz)
- 128Mbit QSPI FLASH Memory (Bitstream + User storage)
- MicroSD socket
- TCXO Oscillator
- JST GH SM06 locking JTAG port
- 5x USER controlable LEDs
- 3x Stardard SYZYGY compatible connectors
- Smart VCCIO controller to support SZYZGY DNA
- Power:
- 3.3V/3A
- 5V/2A
- Adjustable VCCIO 1.2V-3.3V/150mA (per bank)