Files
Last update 1 week 2 days
by ThomasBandin
| FilesCode_STM32Debug | |
|---|---|
| .. | |
| Core | |
| Drivers | |
| makefile | |
| mySTM32G031.elf | |
| mySTM32G031.list | |
| mySTM32G031.map | |
| objects.list | |
| objects.mk | |
| sources.mk |
mySTM32G031.listmySTM32G031.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000bc 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00005a34 080000bc 080000bc 000010bc 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000258 08005af0 08005af0 00006af0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08005d48 08005d48 00007020 2**0 CONTENTS, READONLY 4 .ARM 00000000 08005d48 08005d48 00007020 2**0 CONTENTS, READONLY 5 .preinit_array 00000000 08005d48 08005d48 00007020 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08005d48 08005d48 00006d48 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08005d4c 08005d4c 00006d4c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000020 20000000 08005d50 00007000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000e4 20000020 08005d70 00007020 2**2 ALLOC 10 ._user_heap_stack 00000604 20000104 08005d70 00007104 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00007020 2**0 CONTENTS, READONLY 12 .debug_info 0000c159 00000000 00000000 00007048 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001d9e 00000000 00000000 000131a1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000d50 00000000 00000000 00014f40 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000a5e 00000000 00000000 00015c90 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00016340 00000000 00000000 000166ee 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000ea25 00000000 00000000 0002ca2e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0008fdaa 00000000 00000000 0003b453 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000cb1fd 2**0 CONTENTS, READONLY 20 .debug_frame 00003460 00000000 00000000 000cb240 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000067 00000000 00000000 000ce6a0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000bc <__do_global_dtors_aux>: 80000bc: b510 push {r4, lr} 80000be: 4c06 ldr r4, [pc, #24] @ (80000d8 <__do_global_dtors_aux+0x1c>) 80000c0: 7823 ldrb r3, [r4, #0] 80000c2: 2b00 cmp r3, #0 80000c4: d107 bne.n 80000d6 <__do_global_dtors_aux+0x1a> 80000c6: 4b05 ldr r3, [pc, #20] @ (80000dc <__do_global_dtors_aux+0x20>) 80000c8: 2b00 cmp r3, #0 80000ca: d002 beq.n 80000d2 <__do_global_dtors_aux+0x16> 80000cc: 4804 ldr r0, [pc, #16] @ (80000e0 <__do_global_dtors_aux+0x24>) 80000ce: e000 b.n 80000d2 <__do_global_dtors_aux+0x16> 80000d0: bf00 nop 80000d2: 2301 movs r3, #1 80000d4: 7023 strb r3, [r4, #0] 80000d6: bd10 pop {r4, pc} 80000d8: 20000020 .word 0x20000020 80000dc: 00000000 .word 0x00000000 80000e0: 08005ad8 .word 0x08005ad8 080000e4 <frame_dummy>: 80000e4: 4b04 ldr r3, [pc, #16] @ (80000f8 <frame_dummy+0x14>) 80000e6: b510 push {r4, lr} 80000e8: 2b00 cmp r3, #0 80000ea: d003 beq.n 80000f4 <frame_dummy+0x10> 80000ec: 4903 ldr r1, [pc, #12] @ (80000fc <frame_dummy+0x18>) 80000ee: 4804 ldr r0, [pc, #16] @ (8000100 <frame_dummy+0x1c>) 80000f0: e000 b.n 80000f4 <frame_dummy+0x10> 80000f2: bf00 nop 80000f4: bd10 pop {r4, pc} 80000f6: 46c0 nop @ (mov r8, r8) 80000f8: 00000000 .word 0x00000000 80000fc: 20000024 .word 0x20000024 8000100: 08005ad8 .word 0x08005ad8 08000104 <__udivsi3>: 8000104: 2200 movs r2, #0 8000106: 0843 lsrs r3, r0, #1 8000108: 428b cmp r3, r1 800010a: d374 bcc.n 80001f6 <__udivsi3+0xf2> 800010c: 0903 lsrs r3, r0, #4 800010e: 428b cmp r3, r1 8000110: d35f bcc.n 80001d2 <__udivsi3+0xce> 8000112: 0a03 lsrs r3, r0, #8 8000114: 428b cmp r3, r1 8000116: d344 bcc.n 80001a2 <__udivsi3+0x9e> 8000118: 0b03 lsrs r3, r0, #12 800011a: 428b cmp r3, r1 800011c: d328 bcc.n 8000170 <__udivsi3+0x6c> 800011e: 0c03 lsrs r3, r0, #16 8000120: 428b cmp r3, r1 8000122: d30d bcc.n 8000140 <__udivsi3+0x3c> 8000124: 22ff movs r2, #255 @ 0xff 8000126: 0209 lsls r1, r1, #8 8000128: ba12 rev r2, r2 800012a: 0c03 lsrs r3, r0, #16 800012c: 428b cmp r3, r1 800012e: d302 bcc.n 8000136 <__udivsi3+0x32> 8000130: 1212 asrs r2, r2, #8 8000132: 0209 lsls r1, r1, #8 8000134: d065 beq.n 8000202 <__udivsi3+0xfe> 8000136: 0b03 lsrs r3, r0, #12 8000138: 428b cmp r3, r1 800013a: d319 bcc.n 8000170 <__udivsi3+0x6c> 800013c: e000 b.n 8000140 <__udivsi3+0x3c> 800013e: 0a09 lsrs r1, r1, #8 8000140: 0bc3 lsrs r3, r0, #15 8000142: 428b cmp r3, r1 8000144: d301 bcc.n 800014a <__udivsi3+0x46> 8000146: 03cb lsls r3, r1, #15 8000148: 1ac0 subs r0, r0, r3 800014a: 4152 adcs r2, r2 800014c: 0b83 lsrs r3, r0, #14 800014e: 428b cmp r3, r1 8000150: d301 bcc.n 8000156 <__udivsi3+0x52> 8000152: 038b lsls r3, r1, #14 8000154: 1ac0 subs r0, r0, r3 8000156: 4152 adcs r2, r2 8000158: 0b43 lsrs r3, r0, #13 800015a: 428b cmp r3, r1 800015c: d301 bcc.n 8000162 <__udivsi3+0x5e> 800015e: 034b lsls r3, r1, #13 8000160: 1ac0 subs r0, r0, r3 8000162: 4152 adcs r2, r2 8000164: 0b03 lsrs r3, r0, #12 8000166: 428b cmp r3, r1 8000168: d301 bcc.n 800016e <__udivsi3+0x6a> 800016a: 030b lsls r3, r1, #12 800016c: 1ac0 subs r0, r0, r3 800016e: 4152 adcs r2, r2 8000170: 0ac3 lsrs r3, r0, #11 8000172: 428b cmp r3, r1 8000174: d301 bcc.n 800017a <__udivsi3+0x76> 8000176: 02cb lsls r3, r1, #11 8000178: 1ac0 subs r0, r0, r3 800017a: 4152 adcs r2, r2 800017c: 0a83 lsrs r3, r0, #10 800017e: 428b cmp r3, r1 8000180: d301 bcc.n 8000186 <__udivsi3+0x82> 8000182: 028b lsls r3, r1, #10 8000184: 1ac0 subs r0, r0, r3 8000186: 4152 adcs r2, r2 8000188: 0a43 lsrs r3, r0, #9 800018a: 428b cmp r3, r1 800018c: d301 bcc.n 8000192 <__udivsi3+0x8e> 800018e: 024b lsls r3, r1, #9 8000190: 1ac0 subs r0, r0, r3 8000192: 4152 adcs r2, r2 8000194: 0a03 lsrs r3, r0, #8 8000196: 428b cmp r3, r1 8000198: d301 bcc.n 800019e <__udivsi3+0x9a> 800019a: 020b lsls r3, r1, #8 800019c: 1ac0 subs r0, r0, r3 800019e: 4152 adcs r2, r2 80001a0: d2cd bcs.n 800013e <__udivsi3+0x3a> 80001a2: 09c3 lsrs r3, r0, #7 80001a4: 428b cmp r3, r1 80001a6: d301 bcc.n 80001ac <__udivsi3+0xa8> 80001a8: 01cb lsls r3, r1, #7 80001aa: 1ac0 subs r0, r0, r3 80001ac: 4152 adcs r2, r2 80001ae: 0983 lsrs r3, r0, #6 80001b0: 428b cmp r3, r1 80001b2: d301 bcc.n 80001b8 <__udivsi3+0xb4> 80001b4: 018b lsls r3, r1, #6 80001b6: 1ac0 subs r0, r0, r3 80001b8: 4152 adcs r2, r2 80001ba: 0943 lsrs r3, r0, #5 80001bc: 428b cmp r3, r1 80001be: d301 bcc.n 80001c4 <__udivsi3+0xc0> 80001c0: 014b lsls r3, r1, #5 80001c2: 1ac0 subs r0, r0, r3 80001c4: 4152 adcs r2, r2 80001c6: 0903 lsrs r3, r0, #4 80001c8: 428b cmp r3, r1 80001ca: d301 bcc.n 80001d0 <__udivsi3+0xcc> 80001cc: 010b lsls r3, r1, #4 80001ce: 1ac0 subs r0, r0, r3 80001d0: 4152 adcs r2, r2 80001d2: 08c3 lsrs r3, r0, #3 80001d4: 428b cmp r3, r1 80001d6: d301 bcc.n 80001dc <__udivsi3+0xd8> 80001d8: 00cb lsls r3, r1, #3 80001da: 1ac0 subs r0, r0, r3 80001dc: 4152 adcs r2, r2 80001de: 0883 lsrs r3, r0, #2 80001e0: 428b cmp r3, r1 80001e2: d301 bcc.n 80001e8 <__udivsi3+0xe4> 80001e4: 008b lsls r3, r1, #2 80001e6: 1ac0 subs r0, r0, r3 80001e8: 4152 adcs r2, r2 80001ea: 0843 lsrs r3, r0, #1 80001ec: 428b cmp r3, r1 80001ee: d301 bcc.n 80001f4 <__udivsi3+0xf0> 80001f0: 004b lsls r3, r1, #1 80001f2: 1ac0 subs r0, r0, r3 80001f4: 4152 adcs r2, r2 80001f6: 1a41 subs r1, r0, r1 80001f8: d200 bcs.n 80001fc <__udivsi3+0xf8> 80001fa: 4601 mov r1, r0 80001fc: 4152 adcs r2, r2 80001fe: 4610 mov r0, r2 8000200: 4770 bx lr 8000202: e7ff b.n 8000204 <__udivsi3+0x100> 8000204: b501 push {r0, lr} 8000206: 2000 movs r0, #0 8000208: f000 f8f0 bl 80003ec <__aeabi_idiv0> 800020c: bd02 pop {r1, pc} 800020e: 46c0 nop @ (mov r8, r8) 08000210 <__aeabi_uidivmod>: 8000210: 2900 cmp r1, #0 8000212: d0f7 beq.n 8000204 <__udivsi3+0x100> 8000214: e776 b.n 8000104 <__udivsi3> 8000216: 4770 bx lr 08000218 <__divsi3>: 8000218: 4603 mov r3, r0 800021a: 430b orrs r3, r1 800021c: d47f bmi.n 800031e <__divsi3+0x106> 800021e: 2200 movs r2, #0 8000220: 0843 lsrs r3, r0, #1 8000222: 428b cmp r3, r1 8000224: d374 bcc.n 8000310 <__divsi3+0xf8> 8000226: 0903 lsrs r3, r0, #4 8000228: 428b cmp r3, r1 800022a: d35f bcc.n 80002ec <__divsi3+0xd4> 800022c: 0a03 lsrs r3, r0, #8 800022e: 428b cmp r3, r1 8000230: d344 bcc.n 80002bc <__divsi3+0xa4> 8000232: 0b03 lsrs r3, r0, #12 8000234: 428b cmp r3, r1 8000236: d328 bcc.n 800028a <__divsi3+0x72> 8000238: 0c03 lsrs r3, r0, #16 800023a: 428b cmp r3, r1 800023c: d30d bcc.n 800025a <__divsi3+0x42> 800023e: 22ff movs r2, #255 @ 0xff 8000240: 0209 lsls r1, r1, #8 8000242: ba12 rev r2, r2 8000244: 0c03 lsrs r3, r0, #16 8000246: 428b cmp r3, r1 8000248: d302 bcc.n 8000250 <__divsi3+0x38> 800024a: 1212 asrs r2, r2, #8 800024c: 0209 lsls r1, r1, #8 800024e: d065 beq.n 800031c <__divsi3+0x104> 8000250: 0b03 lsrs r3, r0, #12 8000252: 428b cmp r3, r1 8000254: d319 bcc.n 800028a <__divsi3+0x72> 8000256: e000 b.n 800025a <__divsi3+0x42> 8000258: 0a09 lsrs r1, r1, #8 800025a: 0bc3 lsrs r3, r0, #15 800025c: 428b cmp r3, r1 800025e: d301 bcc.n 8000264 <__divsi3+0x4c> 8000260: 03cb lsls r3, r1, #15 8000262: 1ac0 subs r0, r0, r3 8000264: 4152 adcs r2, r2 8000266: 0b83 lsrs r3, r0, #14 8000268: 428b cmp r3, r1 800026a: d301 bcc.n 8000270 <__divsi3+0x58> 800026c: 038b lsls r3, r1, #14 800026e: 1ac0 subs r0, r0, r3 8000270: 4152 adcs r2, r2 8000272: 0b43 lsrs r3, r0, #13 8000274: 428b cmp r3, r1 8000276: d301 bcc.n 800027c <__divsi3+0x64> 8000278: 034b lsls r3, r1, #13 800027a: 1ac0 subs r0, r0, r3 800027c: 4152 adcs r2, r2 800027e: 0b03 lsrs r3, r0, #12 8000280: 428b cmp r3, r1 8000282: d301 bcc.n 8000288 <__divsi3+0x70> 8000284: 030b lsls r3, r1, #12 8000286: 1ac0 subs r0, r0, r3 8000288: 4152 adcs r2, r2 800028a: 0ac3 lsrs r3, r0, #11 800028c: 428b cmp r3, r1 800028e: d301 bcc.n 8000294 <__divsi3+0x7c> 8000290: 02cb lsls r3, r1, #11 8000292: 1ac0 subs r0, r0, r3 8000294: 4152 adcs r2, r2 8000296: 0a83 lsrs r3, r0, #10 8000298: 428b cmp r3, r1 800029a: d301 bcc.n 80002a0 <__divsi3+0x88> 800029c: 028b lsls r3, r1, #10 800029e: 1ac0 subs r0, r0, r3 80002a0: 4152 adcs r2, r2 80002a2: 0a43 lsrs r3, r0, #9 80002a4: 428b cmp r3, r1 80002a6: d301 bcc.n 80002ac <__divsi3+0x94> 80002a8: 024b lsls r3, r1, #9 80002aa: 1ac0 subs r0, r0, r3 80002ac: 4152 adcs r2, r2 80002ae: 0a03 lsrs r3, r0, #8 80002b0: 428b cmp r3, r1 80002b2: d301 bcc.n 80002b8 <__divsi3+0xa0> 80002b4: 020b lsls r3, r1, #8 80002b6: 1ac0 subs r0, r0, r3 80002b8: 4152 adcs r2, r2 80002ba: d2cd bcs.n 8000258 <__divsi3+0x40> 80002bc: 09c3 lsrs r3, r0, #7 80002be: 428b cmp r3, r1 80002c0: d301 bcc.n 80002c6 <__divsi3+0xae> 80002c2: 01cb lsls r3, r1, #7 80002c4: 1ac0 subs r0, r0, r3 80002c6: 4152 adcs r2, r2 80002c8: 0983 lsrs r3, r0, #6 80002ca: 428b cmp r3, r1 80002cc: d301 bcc.n 80002d2 <__divsi3+0xba> 80002ce: 018b lsls r3, r1, #6 80002d0: 1ac0 subs r0, r0, r3 80002d2: 4152 adcs r2, r2 80002d4: 0943 lsrs r3, r0, #5 80002d6: 428b cmp r3, r1 80002d8: d301 bcc.n 80002de <__divsi3+0xc6> 80002da: 014b lsls r3, r1, #5 80002dc: 1ac0 subs r0, r0, r3 80002de: 4152 adcs r2, r2 80002e0: 0903 lsrs r3, r0, #4 80002e2: 428b cmp r3, r1 80002e4: d301 bcc.n 80002ea <__divsi3+0xd2> 80002e6: 010b lsls r3, r1, #4 80002e8: 1ac0 subs r0, r0, r3 80002ea: 4152 adcs r2, r2 80002ec: 08c3 lsrs r3, r0, #3 80002ee: 428b cmp r3, r1 80002f0: d301 bcc.n 80002f6 <__divsi3+0xde> 80002f2: 00cb lsls r3, r1, #3 80002f4: 1ac0 subs r0, r0, r3 80002f6: 4152 adcs r2, r2 80002f8: 0883 lsrs r3, r0, #2 80002fa: 428b cmp r3, r1 80002fc: d301 bcc.n 8000302 <__divsi3+0xea> 80002fe: 008b lsls r3, r1, #2 8000300: 1ac0 subs r0, r0, r3 8000302: 4152 adcs r2, r2 8000304: 0843 lsrs r3, r0, #1 8000306: 428b cmp r3, r1 8000308: d301 bcc.n 800030e <__divsi3+0xf6> 800030a: 004b lsls r3, r1, #1 800030c: 1ac0 subs r0, r0, r3 800030e: 4152 adcs r2, r2 8000310: 1a41 subs r1, r0, r1 8000312: d200 bcs.n 8000316 <__divsi3+0xfe> 8000314: 4601 mov r1, r0 8000316: 4152 adcs r2, r2 8000318: 4610 mov r0, r2 800031a: 4770 bx lr 800031c: e05d b.n 80003da <__divsi3+0x1c2> 800031e: 0fca lsrs r2, r1, #31 8000320: d000 beq.n 8000324 <__divsi3+0x10c> 8000322: 4249 negs r1, r1 8000324: 1003 asrs r3, r0, #32 8000326: d300 bcc.n 800032a <__divsi3+0x112> 8000328: 4240 negs r0, r0 800032a: 4053 eors r3, r2 800032c: 2200 movs r2, #0 800032e: 469c mov ip, r3 8000330: 0903 lsrs r3, r0, #4 8000332: 428b cmp r3, r1 8000334: d32d bcc.n 8000392 <__divsi3+0x17a> 8000336: 0a03 lsrs r3, r0, #8 8000338: 428b cmp r3, r1 800033a: d312 bcc.n 8000362 <__divsi3+0x14a> 800033c: 22fc movs r2, #252 @ 0xfc 800033e: 0189 lsls r1, r1, #6 8000340: ba12 rev r2, r2 8000342: 0a03 lsrs r3, r0, #8 8000344: 428b cmp r3, r1 8000346: d30c bcc.n 8000362 <__divsi3+0x14a> 8000348: 0189 lsls r1, r1, #6 800034a: 1192 asrs r2, r2, #6 800034c: 428b cmp r3, r1 800034e: d308 bcc.n 8000362 <__divsi3+0x14a> 8000350: 0189 lsls r1, r1, #6 8000352: 1192 asrs r2, r2, #6 8000354: 428b cmp r3, r1 8000356: d304 bcc.n 8000362 <__divsi3+0x14a> 8000358: 0189 lsls r1, r1, #6 800035a: d03a beq.n 80003d2 <__divsi3+0x1ba> 800035c: 1192 asrs r2, r2, #6 800035e: e000 b.n 8000362 <__divsi3+0x14a> 8000360: 0989 lsrs r1, r1, #6 8000362: 09c3 lsrs r3, r0, #7 8000364: 428b cmp r3, r1 8000366: d301 bcc.n 800036c <__divsi3+0x154> 8000368: 01cb lsls r3, r1, #7 800036a: 1ac0 subs r0, r0, r3 800036c: 4152 adcs r2, r2 800036e: 0983 lsrs r3, r0, #6 8000370: 428b cmp r3, r1 8000372: d301 bcc.n 8000378 <__divsi3+0x160> 8000374: 018b lsls r3, r1, #6 8000376: 1ac0 subs r0, r0, r3 8000378: 4152 adcs r2, r2 800037a: 0943 lsrs r3, r0, #5 800037c: 428b cmp r3, r1 800037e: d301 bcc.n 8000384 <__divsi3+0x16c> 8000380: 014b lsls r3, r1, #5 8000382: 1ac0 subs r0, r0, r3 8000384: 4152 adcs r2, r2 8000386: 0903 lsrs r3, r0, #4 8000388: 428b cmp r3, r1 800038a: d301 bcc.n 8000390 <__divsi3+0x178> 800038c: 010b lsls r3, r1, #4 800038e: 1ac0 subs r0, r0, r3 8000390: 4152 adcs r2, r2 8000392: 08c3 lsrs r3, r0, #3 8000394: 428b cmp r3, r1 8000396: d301 bcc.n 800039c <__divsi3+0x184> 8000398: 00cb lsls r3, r1, #3 800039a: 1ac0 subs r0, r0, r3 800039c: 4152 adcs r2, r2 800039e: 0883 lsrs r3, r0, #2 80003a0: 428b cmp r3, r1 80003a2: d301 bcc.n 80003a8 <__divsi3+0x190> 80003a4: 008b lsls r3, r1, #2 80003a6: 1ac0 subs r0, r0, r3 80003a8: 4152 adcs r2, r2 80003aa: d2d9 bcs.n 8000360 <__divsi3+0x148> 80003ac: 0843 lsrs r3, r0, #1 80003ae: 428b cmp r3, r1 80003b0: d301 bcc.n 80003b6 <__divsi3+0x19e> 80003b2: 004b lsls r3, r1, #1 80003b4: 1ac0 subs r0, r0, r3 80003b6: 4152 adcs r2, r2 80003b8: 1a41 subs r1, r0, r1 80003ba: d200 bcs.n 80003be <__divsi3+0x1a6> 80003bc: 4601 mov r1, r0 80003be: 4663 mov r3, ip 80003c0: 4152 adcs r2, r2 80003c2: 105b asrs r3, r3, #1 80003c4: 4610 mov r0, r2 80003c6: d301 bcc.n 80003cc <__divsi3+0x1b4> 80003c8: 4240 negs r0, r0 80003ca: 2b00 cmp r3, #0 80003cc: d500 bpl.n 80003d0 <__divsi3+0x1b8> 80003ce: 4249 negs r1, r1 80003d0: 4770 bx lr 80003d2: 4663 mov r3, ip 80003d4: 105b asrs r3, r3, #1 80003d6: d300 bcc.n 80003da <__divsi3+0x1c2> 80003d8: 4240 negs r0, r0 80003da: b501 push {r0, lr} 80003dc: 2000 movs r0, #0 80003de: f000 f805 bl 80003ec <__aeabi_idiv0> 80003e2: bd02 pop {r1, pc} 080003e4 <__aeabi_idivmod>: 80003e4: 2900 cmp r1, #0 80003e6: d0f8 beq.n 80003da <__divsi3+0x1c2> 80003e8: e716 b.n 8000218 <__divsi3> 80003ea: 4770 bx lr 080003ec <__aeabi_idiv0>: 80003ec: 4770 bx lr 80003ee: 46c0 nop @ (mov r8, r8) 080003f0 <__aeabi_cdrcmple>: 80003f0: 4684 mov ip, r0 80003f2: 0010 movs r0, r2 80003f4: 4662 mov r2, ip 80003f6: 468c mov ip, r1 80003f8: 0019 movs r1, r3 80003fa: 4663 mov r3, ip 80003fc: e000 b.n 8000400 <__aeabi_cdcmpeq> 80003fe: 46c0 nop @ (mov r8, r8) 08000400 <__aeabi_cdcmpeq>: 8000400: b51f push {r0, r1, r2, r3, r4, lr} 8000402: f001 f829 bl 8001458 <__ledf2> 8000406: 2800 cmp r0, #0 8000408: d401 bmi.n 800040e <__aeabi_cdcmpeq+0xe> 800040a: 2100 movs r1, #0 800040c: 42c8 cmn r0, r1 800040e: bd1f pop {r0, r1, r2, r3, r4, pc} 08000410 <__aeabi_dcmpeq>: 8000410: b510 push {r4, lr} 8000412: f000 ff6d bl 80012f0 <__eqdf2> 8000416: 4240 negs r0, r0 8000418: 3001 adds r0, #1 800041a: bd10 pop {r4, pc} 0800041c <__aeabi_dcmplt>: 800041c: b510 push {r4, lr} 800041e: f001 f81b bl 8001458 <__ledf2> 8000422: 2800 cmp r0, #0 8000424: db01 blt.n 800042a <__aeabi_dcmplt+0xe> 8000426: 2000 movs r0, #0 8000428: bd10 pop {r4, pc} 800042a: 2001 movs r0, #1 800042c: bd10 pop {r4, pc} 800042e: 46c0 nop @ (mov r8, r8) 08000430 <__aeabi_dcmple>: 8000430: b510 push {r4, lr} 8000432: f001 f811 bl 8001458 <__ledf2> 8000436: 2800 cmp r0, #0 8000438: dd01 ble.n 800043e <__aeabi_dcmple+0xe> 800043a: 2000 movs r0, #0 800043c: bd10 pop {r4, pc} 800043e: 2001 movs r0, #1 8000440: bd10 pop {r4, pc} 8000442: 46c0 nop @ (mov r8, r8) 08000444 <__aeabi_dcmpgt>: 8000444: b510 push {r4, lr} 8000446: f000 ff97 bl 8001378 <__gedf2> 800044a: 2800 cmp r0, #0 800044c: dc01 bgt.n 8000452 <__aeabi_dcmpgt+0xe> 800044e: 2000 movs r0, #0 8000450: bd10 pop {r4, pc} 8000452: 2001 movs r0, #1 8000454: bd10 pop {r4, pc} 8000456: 46c0 nop @ (mov r8, r8) 08000458 <__aeabi_dcmpge>: 8000458: b510 push {r4, lr} 800045a: f000 ff8d bl 8001378 <__gedf2> 800045e: 2800 cmp r0, #0 8000460: da01 bge.n 8000466 <__aeabi_dcmpge+0xe> 8000462: 2000 movs r0, #0 8000464: bd10 pop {r4, pc} 8000466: 2001 movs r0, #1 8000468: bd10 pop {r4, pc} 800046a: 46c0 nop @ (mov r8, r8) 0800046c <__aeabi_d2uiz>: 800046c: b570 push {r4, r5, r6, lr} 800046e: 2200 movs r2, #0 8000470: 4b0c ldr r3, [pc, #48] @ (80004a4 <__aeabi_d2uiz+0x38>) 8000472: 0004 movs r4, r0 8000474: 000d movs r5, r1 8000476: f7ff ffef bl 8000458 <__aeabi_dcmpge> 800047a: 2800 cmp r0, #0 800047c: d104 bne.n 8000488 <__aeabi_d2uiz+0x1c> 800047e: 0020 movs r0, r4 8000480: 0029 movs r1, r5 8000482: f001 ff47 bl 8002314 <__aeabi_d2iz> 8000486: bd70 pop {r4, r5, r6, pc} 8000488: 4b06 ldr r3, [pc, #24] @ (80004a4 <__aeabi_d2uiz+0x38>) 800048a: 2200 movs r2, #0 800048c: 0020 movs r0, r4 800048e: 0029 movs r1, r5 8000490: f001 fb36 bl 8001b00 <__aeabi_dsub> 8000494: f001 ff3e bl 8002314 <__aeabi_d2iz> 8000498: 2380 movs r3, #128 @ 0x80 800049a: 061b lsls r3, r3, #24 800049c: 469c mov ip, r3 800049e: 4460 add r0, ip 80004a0: e7f1 b.n 8000486 <__aeabi_d2uiz+0x1a> 80004a2: 46c0 nop @ (mov r8, r8) 80004a4: 41e00000 .word 0x41e00000 080004a8 <__aeabi_ui2f>: 80004a8: b510 push {r4, lr} 80004aa: 1e04 subs r4, r0, #0 80004ac: d00d beq.n 80004ca <__aeabi_ui2f+0x22> 80004ae: f002 f865 bl 800257c <__clzsi2> 80004b2: 239e movs r3, #158 @ 0x9e 80004b4: 1a1b subs r3, r3, r0 80004b6: 2b96 cmp r3, #150 @ 0x96 80004b8: dc0c bgt.n 80004d4 <__aeabi_ui2f+0x2c> 80004ba: 2808 cmp r0, #8 80004bc: d034 beq.n 8000528 <__aeabi_ui2f+0x80> 80004be: 3808 subs r0, #8 80004c0: 4084 lsls r4, r0 80004c2: 0264 lsls r4, r4, #9 80004c4: 0a64 lsrs r4, r4, #9 80004c6: b2d8 uxtb r0, r3 80004c8: e001 b.n 80004ce <__aeabi_ui2f+0x26> 80004ca: 2000 movs r0, #0 80004cc: 2400 movs r4, #0 80004ce: 05c0 lsls r0, r0, #23 80004d0: 4320 orrs r0, r4 80004d2: bd10 pop {r4, pc} 80004d4: 2b99 cmp r3, #153 @ 0x99 80004d6: dc13 bgt.n 8000500 <__aeabi_ui2f+0x58> 80004d8: 1f42 subs r2, r0, #5 80004da: 4094 lsls r4, r2 80004dc: 4a14 ldr r2, [pc, #80] @ (8000530 <__aeabi_ui2f+0x88>) 80004de: 4022 ands r2, r4 80004e0: 0761 lsls r1, r4, #29 80004e2: d01c beq.n 800051e <__aeabi_ui2f+0x76> 80004e4: 210f movs r1, #15 80004e6: 4021 ands r1, r4 80004e8: 2904 cmp r1, #4 80004ea: d018 beq.n 800051e <__aeabi_ui2f+0x76> 80004ec: 3204 adds r2, #4 80004ee: 08d4 lsrs r4, r2, #3 80004f0: 0152 lsls r2, r2, #5 80004f2: d515 bpl.n 8000520 <__aeabi_ui2f+0x78> 80004f4: 239f movs r3, #159 @ 0x9f 80004f6: 0264 lsls r4, r4, #9 80004f8: 1a18 subs r0, r3, r0 80004fa: 0a64 lsrs r4, r4, #9 80004fc: b2c0 uxtb r0, r0 80004fe: e7e6 b.n 80004ce <__aeabi_ui2f+0x26> 8000500: 0002 movs r2, r0 8000502: 0021 movs r1, r4 8000504: 321b adds r2, #27 8000506: 4091 lsls r1, r2 8000508: 000a movs r2, r1 800050a: 1e51 subs r1, r2, #1 800050c: 418a sbcs r2, r1 800050e: 2105 movs r1, #5 8000510: 1a09 subs r1, r1, r0 8000512: 40cc lsrs r4, r1 8000514: 4314 orrs r4, r2 8000516: 4a06 ldr r2, [pc, #24] @ (8000530 <__aeabi_ui2f+0x88>) 8000518: 4022 ands r2, r4 800051a: 0761 lsls r1, r4, #29 800051c: d1e2 bne.n 80004e4 <__aeabi_ui2f+0x3c> 800051e: 08d4 lsrs r4, r2, #3 8000520: 0264 lsls r4, r4, #9 8000522: 0a64 lsrs r4, r4, #9 8000524: b2d8 uxtb r0, r3 8000526: e7d2 b.n 80004ce <__aeabi_ui2f+0x26> 8000528: 0264 lsls r4, r4, #9 800052a: 0a64 lsrs r4, r4, #9 800052c: 308e adds r0, #142 @ 0x8e 800052e: e7ce b.n 80004ce <__aeabi_ui2f+0x26> 8000530: fbffffff .word 0xfbffffff 08000534 <__aeabi_dadd>: 8000534: b5f0 push {r4, r5, r6, r7, lr} 8000536: 464f mov r7, r9 8000538: 4646 mov r6, r8 800053a: 46d6 mov lr, sl 800053c: b5c0 push {r6, r7, lr} 800053e: b082 sub sp, #8 8000540: 9000 str r0, [sp, #0] 8000542: 9101 str r1, [sp, #4] 8000544: 030e lsls r6, r1, #12 8000546: 004c lsls r4, r1, #1 8000548: 0fcd lsrs r5, r1, #31 800054a: 0a71 lsrs r1, r6, #9 800054c: 9e00 ldr r6, [sp, #0] 800054e: 005f lsls r7, r3, #1 8000550: 0f76 lsrs r6, r6, #29 8000552: 430e orrs r6, r1 8000554: 9900 ldr r1, [sp, #0] 8000556: 9200 str r2, [sp, #0] 8000558: 9301 str r3, [sp, #4] 800055a: 00c9 lsls r1, r1, #3 800055c: 4689 mov r9, r1 800055e: 0319 lsls r1, r3, #12 8000560: 0d7b lsrs r3, r7, #21 8000562: 4698 mov r8, r3 8000564: 9b01 ldr r3, [sp, #4] 8000566: 0a49 lsrs r1, r1, #9 8000568: 0fdb lsrs r3, r3, #31 800056a: 469c mov ip, r3 800056c: 9b00 ldr r3, [sp, #0] 800056e: 9a00 ldr r2, [sp, #0] 8000570: 0f5b lsrs r3, r3, #29 8000572: 430b orrs r3, r1 8000574: 4641 mov r1, r8 8000576: 0d64 lsrs r4, r4, #21 8000578: 00d2 lsls r2, r2, #3 800057a: 1a61 subs r1, r4, r1 800057c: 4565 cmp r5, ip 800057e: d100 bne.n 8000582 <__aeabi_dadd+0x4e> 8000580: e0a6 b.n 80006d0 <__aeabi_dadd+0x19c> 8000582: 2900 cmp r1, #0 8000584: dd72 ble.n 800066c <__aeabi_dadd+0x138> 8000586: 4647 mov r7, r8 8000588: 2f00 cmp r7, #0 800058a: d100 bne.n 800058e <__aeabi_dadd+0x5a> 800058c: e0dd b.n 800074a <__aeabi_dadd+0x216> 800058e: 4fcc ldr r7, [pc, #816] @ (80008c0 <__aeabi_dadd+0x38c>) 8000590: 42bc cmp r4, r7 8000592: d100 bne.n 8000596 <__aeabi_dadd+0x62> 8000594: e19a b.n 80008cc <__aeabi_dadd+0x398> 8000596: 2701 movs r7, #1 8000598: 2938 cmp r1, #56 @ 0x38 800059a: dc17 bgt.n 80005cc <__aeabi_dadd+0x98> 800059c: 2780 movs r7, #128 @ 0x80 800059e: 043f lsls r7, r7, #16 80005a0: 433b orrs r3, r7 80005a2: 291f cmp r1, #31 80005a4: dd00 ble.n 80005a8 <__aeabi_dadd+0x74> 80005a6: e1dd b.n 8000964 <__aeabi_dadd+0x430> 80005a8: 2720 movs r7, #32 80005aa: 1a78 subs r0, r7, r1 80005ac: 001f movs r7, r3 80005ae: 4087 lsls r7, r0 80005b0: 46ba mov sl, r7 80005b2: 0017 movs r7, r2 80005b4: 40cf lsrs r7, r1 80005b6: 4684 mov ip, r0 80005b8: 0038 movs r0, r7 80005ba: 4657 mov r7, sl 80005bc: 4307 orrs r7, r0 80005be: 4660 mov r0, ip 80005c0: 4082 lsls r2, r0 80005c2: 40cb lsrs r3, r1 80005c4: 1e50 subs r0, r2, #1 80005c6: 4182 sbcs r2, r0 80005c8: 1af6 subs r6, r6, r3 80005ca: 4317 orrs r7, r2 80005cc: 464b mov r3, r9 80005ce: 1bdf subs r7, r3, r7 80005d0: 45b9 cmp r9, r7 80005d2: 4180 sbcs r0, r0 80005d4: 4240 negs r0, r0 80005d6: 1a36 subs r6, r6, r0 80005d8: 0233 lsls r3, r6, #8 80005da: d400 bmi.n 80005de <__aeabi_dadd+0xaa> 80005dc: e0ff b.n 80007de <__aeabi_dadd+0x2aa> 80005de: 0276 lsls r6, r6, #9 80005e0: 0a76 lsrs r6, r6, #9 80005e2: 2e00 cmp r6, #0 80005e4: d100 bne.n 80005e8 <__aeabi_dadd+0xb4> 80005e6: e13c b.n 8000862 <__aeabi_dadd+0x32e> 80005e8: 0030 movs r0, r6 80005ea: f001 ffc7 bl 800257c <__clzsi2> 80005ee: 0003 movs r3, r0 80005f0: 3b08 subs r3, #8 80005f2: 2120 movs r1, #32 80005f4: 0038 movs r0, r7 80005f6: 1aca subs r2, r1, r3 80005f8: 40d0 lsrs r0, r2 80005fa: 409e lsls r6, r3 80005fc: 0002 movs r2, r0 80005fe: 409f lsls r7, r3 8000600: 4332 orrs r2, r6 8000602: 429c cmp r4, r3 8000604: dd00 ble.n 8000608 <__aeabi_dadd+0xd4> 8000606: e1a6 b.n 8000956 <__aeabi_dadd+0x422> 8000608: 1b18 subs r0, r3, r4 800060a: 3001 adds r0, #1 800060c: 1a09 subs r1, r1, r0 800060e: 003e movs r6, r7 8000610: 408f lsls r7, r1 8000612: 40c6 lsrs r6, r0 8000614: 1e7b subs r3, r7, #1 8000616: 419f sbcs r7, r3 8000618: 0013 movs r3, r2 800061a: 408b lsls r3, r1 800061c: 4337 orrs r7, r6 800061e: 431f orrs r7, r3 8000620: 40c2 lsrs r2, r0 8000622: 003b movs r3, r7 8000624: 0016 movs r6, r2 8000626: 2400 movs r4, #0 8000628: 4313 orrs r3, r2 800062a: d100 bne.n 800062e <__aeabi_dadd+0xfa> 800062c: e1df b.n 80009ee <__aeabi_dadd+0x4ba> 800062e: 077b lsls r3, r7, #29 8000630: d100 bne.n 8000634 <__aeabi_dadd+0x100> 8000632: e332 b.n 8000c9a <__aeabi_dadd+0x766> 8000634: 230f movs r3, #15 8000636: 003a movs r2, r7 8000638: 403b ands r3, r7 800063a: 2b04 cmp r3, #4 800063c: d004 beq.n 8000648 <__aeabi_dadd+0x114> 800063e: 1d3a adds r2, r7, #4 8000640: 42ba cmp r2, r7 8000642: 41bf sbcs r7, r7 8000644: 427f negs r7, r7 8000646: 19f6 adds r6, r6, r7 8000648: 0233 lsls r3, r6, #8 800064a: d400 bmi.n 800064e <__aeabi_dadd+0x11a> 800064c: e323 b.n 8000c96 <__aeabi_dadd+0x762> 800064e: 4b9c ldr r3, [pc, #624] @ (80008c0 <__aeabi_dadd+0x38c>) 8000650: 3401 adds r4, #1 8000652: 429c cmp r4, r3 8000654: d100 bne.n 8000658 <__aeabi_dadd+0x124> 8000656: e0b4 b.n 80007c2 <__aeabi_dadd+0x28e> 8000658: 4b9a ldr r3, [pc, #616] @ (80008c4 <__aeabi_dadd+0x390>) 800065a: 0564 lsls r4, r4, #21 800065c: 401e ands r6, r3 800065e: 0d64 lsrs r4, r4, #21 8000660: 0777 lsls r7, r6, #29 8000662: 08d2 lsrs r2, r2, #3 8000664: 0276 lsls r6, r6, #9 8000666: 4317 orrs r7, r2 8000668: 0b36 lsrs r6, r6, #12 800066a: e0ac b.n 80007c6 <__aeabi_dadd+0x292> 800066c: 2900 cmp r1, #0 800066e: d100 bne.n 8000672 <__aeabi_dadd+0x13e> 8000670: e07e b.n 8000770 <__aeabi_dadd+0x23c> 8000672: 4641 mov r1, r8 8000674: 1b09 subs r1, r1, r4 8000676: 2c00 cmp r4, #0 8000678: d000 beq.n 800067c <__aeabi_dadd+0x148> 800067a: e160 b.n 800093e <__aeabi_dadd+0x40a> 800067c: 0034 movs r4, r6 800067e: 4648 mov r0, r9 8000680: 4304 orrs r4, r0 8000682: d100 bne.n 8000686 <__aeabi_dadd+0x152> 8000684: e1c9 b.n 8000a1a <__aeabi_dadd+0x4e6> 8000686: 1e4c subs r4, r1, #1 8000688: 2901 cmp r1, #1 800068a: d100 bne.n 800068e <__aeabi_dadd+0x15a> 800068c: e22e b.n 8000aec <__aeabi_dadd+0x5b8> 800068e: 4d8c ldr r5, [pc, #560] @ (80008c0 <__aeabi_dadd+0x38c>) 8000690: 42a9 cmp r1, r5 8000692: d100 bne.n 8000696 <__aeabi_dadd+0x162> 8000694: e224 b.n 8000ae0 <__aeabi_dadd+0x5ac> 8000696: 2701 movs r7, #1 8000698: 2c38 cmp r4, #56 @ 0x38 800069a: dc11 bgt.n 80006c0 <__aeabi_dadd+0x18c> 800069c: 0021 movs r1, r4 800069e: 291f cmp r1, #31 80006a0: dd00 ble.n 80006a4 <__aeabi_dadd+0x170> 80006a2: e20b b.n 8000abc <__aeabi_dadd+0x588> 80006a4: 2420 movs r4, #32 80006a6: 0037 movs r7, r6 80006a8: 4648 mov r0, r9 80006aa: 1a64 subs r4, r4, r1 80006ac: 40a7 lsls r7, r4 80006ae: 40c8 lsrs r0, r1 80006b0: 4307 orrs r7, r0 80006b2: 4648 mov r0, r9 80006b4: 40a0 lsls r0, r4 80006b6: 40ce lsrs r6, r1 80006b8: 1e44 subs r4, r0, #1 80006ba: 41a0 sbcs r0, r4 80006bc: 1b9b subs r3, r3, r6 80006be: 4307 orrs r7, r0 80006c0: 1bd7 subs r7, r2, r7 80006c2: 42ba cmp r2, r7 80006c4: 4192 sbcs r2, r2 80006c6: 4252 negs r2, r2 80006c8: 4665 mov r5, ip 80006ca: 4644 mov r4, r8 80006cc: 1a9e subs r6, r3, r2 80006ce: e783 b.n 80005d8 <__aeabi_dadd+0xa4> 80006d0: 2900 cmp r1, #0 80006d2: dc00 bgt.n 80006d6 <__aeabi_dadd+0x1a2> 80006d4: e09c b.n 8000810 <__aeabi_dadd+0x2dc> 80006d6: 4647 mov r7, r8 80006d8: 2f00 cmp r7, #0 80006da: d167 bne.n 80007ac <__aeabi_dadd+0x278> 80006dc: 001f movs r7, r3 80006de: 4317 orrs r7, r2 80006e0: d100 bne.n 80006e4 <__aeabi_dadd+0x1b0> 80006e2: e0e4 b.n 80008ae <__aeabi_dadd+0x37a> 80006e4: 1e48 subs r0, r1, #1 80006e6: 2901 cmp r1, #1 80006e8: d100 bne.n 80006ec <__aeabi_dadd+0x1b8> 80006ea: e19b b.n 8000a24 <__aeabi_dadd+0x4f0> 80006ec: 4f74 ldr r7, [pc, #464] @ (80008c0 <__aeabi_dadd+0x38c>) 80006ee: 42b9 cmp r1, r7 80006f0: d100 bne.n 80006f4 <__aeabi_dadd+0x1c0> 80006f2: e0eb b.n 80008cc <__aeabi_dadd+0x398> 80006f4: 2701 movs r7, #1 80006f6: 0001 movs r1, r0 80006f8: 2838 cmp r0, #56 @ 0x38 80006fa: dc11 bgt.n 8000720 <__aeabi_dadd+0x1ec> 80006fc: 291f cmp r1, #31 80006fe: dd00 ble.n 8000702 <__aeabi_dadd+0x1ce> 8000700: e1c7 b.n 8000a92 <__aeabi_dadd+0x55e> 8000702: 2720 movs r7, #32 8000704: 1a78 subs r0, r7, r1 8000706: 001f movs r7, r3 8000708: 4684 mov ip, r0 800070a: 4087 lsls r7, r0 800070c: 0010 movs r0, r2 800070e: 40c8 lsrs r0, r1 8000710: 4307 orrs r7, r0 8000712: 4660 mov r0, ip 8000714: 4082 lsls r2, r0 8000716: 40cb lsrs r3, r1 8000718: 1e50 subs r0, r2, #1 800071a: 4182 sbcs r2, r0 800071c: 18f6 adds r6, r6, r3 800071e: 4317 orrs r7, r2 8000720: 444f add r7, r9 8000722: 454f cmp r7, r9 8000724: 4180 sbcs r0, r0 8000726: 4240 negs r0, r0 8000728: 1836 adds r6, r6, r0 800072a: 0233 lsls r3, r6, #8 800072c: d557 bpl.n 80007de <__aeabi_dadd+0x2aa> 800072e: 4b64 ldr r3, [pc, #400] @ (80008c0 <__aeabi_dadd+0x38c>) 8000730: 3401 adds r4, #1 8000732: 429c cmp r4, r3 8000734: d045 beq.n 80007c2 <__aeabi_dadd+0x28e> 8000736: 2101 movs r1, #1 8000738: 4b62 ldr r3, [pc, #392] @ (80008c4 <__aeabi_dadd+0x390>) 800073a: 087a lsrs r2, r7, #1 800073c: 401e ands r6, r3 800073e: 4039 ands r1, r7 8000740: 430a orrs r2, r1 8000742: 07f7 lsls r7, r6, #31 8000744: 4317 orrs r7, r2 8000746: 0876 lsrs r6, r6, #1 8000748: e771 b.n 800062e <__aeabi_dadd+0xfa> 800074a: 001f movs r7, r3 800074c: 4317 orrs r7, r2 800074e: d100 bne.n 8000752 <__aeabi_dadd+0x21e> 8000750: e0ad b.n 80008ae <__aeabi_dadd+0x37a> 8000752: 1e4f subs r7, r1, #1 8000754: 46bc mov ip, r7 8000756: 2901 cmp r1, #1 8000758: d100 bne.n 800075c <__aeabi_dadd+0x228> 800075a: e182 b.n 8000a62 <__aeabi_dadd+0x52e> 800075c: 4f58 ldr r7, [pc, #352] @ (80008c0 <__aeabi_dadd+0x38c>) 800075e: 42b9 cmp r1, r7 8000760: d100 bne.n 8000764 <__aeabi_dadd+0x230> 8000762: e190 b.n 8000a86 <__aeabi_dadd+0x552> 8000764: 4661 mov r1, ip 8000766: 2701 movs r7, #1 8000768: 2938 cmp r1, #56 @ 0x38 800076a: dd00 ble.n 800076e <__aeabi_dadd+0x23a> 800076c: e72e b.n 80005cc <__aeabi_dadd+0x98> 800076e: e718 b.n 80005a2 <__aeabi_dadd+0x6e> 8000770: 4f55 ldr r7, [pc, #340] @ (80008c8 <__aeabi_dadd+0x394>) 8000772: 1c61 adds r1, r4, #1 8000774: 4239 tst r1, r7 8000776: d000 beq.n 800077a <__aeabi_dadd+0x246> 8000778: e0d0 b.n 800091c <__aeabi_dadd+0x3e8> 800077a: 0031 movs r1, r6 800077c: 4648 mov r0, r9 800077e: 001f movs r7, r3 8000780: 4301 orrs r1, r0 8000782: 4317 orrs r7, r2 8000784: 2c00 cmp r4, #0 8000786: d000 beq.n 800078a <__aeabi_dadd+0x256> 8000788: e13d b.n 8000a06 <__aeabi_dadd+0x4d2> 800078a: 2900 cmp r1, #0 800078c: d100 bne.n 8000790 <__aeabi_dadd+0x25c> 800078e: e1bc b.n 8000b0a <__aeabi_dadd+0x5d6> 8000790: 2f00 cmp r7, #0 8000792: d000 beq.n 8000796 <__aeabi_dadd+0x262> 8000794: e1bf b.n 8000b16 <__aeabi_dadd+0x5e2> 8000796: 464b mov r3, r9 8000798: 2100 movs r1, #0 800079a: 08d8 lsrs r0, r3, #3 800079c: 0777 lsls r7, r6, #29 800079e: 4307 orrs r7, r0 80007a0: 08f0 lsrs r0, r6, #3 80007a2: 0306 lsls r6, r0, #12 80007a4: 054c lsls r4, r1, #21 80007a6: 0b36 lsrs r6, r6, #12 80007a8: 0d64 lsrs r4, r4, #21 80007aa: e00c b.n 80007c6 <__aeabi_dadd+0x292> 80007ac: 4f44 ldr r7, [pc, #272] @ (80008c0 <__aeabi_dadd+0x38c>) 80007ae: 42bc cmp r4, r7 80007b0: d100 bne.n 80007b4 <__aeabi_dadd+0x280> 80007b2: e08b b.n 80008cc <__aeabi_dadd+0x398> 80007b4: 2701 movs r7, #1 80007b6: 2938 cmp r1, #56 @ 0x38 80007b8: dcb2 bgt.n 8000720 <__aeabi_dadd+0x1ec> 80007ba: 2780 movs r7, #128 @ 0x80 80007bc: 043f lsls r7, r7, #16 80007be: 433b orrs r3, r7 80007c0: e79c b.n 80006fc <__aeabi_dadd+0x1c8> 80007c2: 2600 movs r6, #0 80007c4: 2700 movs r7, #0 80007c6: 0524 lsls r4, r4, #20 80007c8: 4334 orrs r4, r6 80007ca: 07ed lsls r5, r5, #31 80007cc: 432c orrs r4, r5 80007ce: 0038 movs r0, r7 80007d0: 0021 movs r1, r4 80007d2: b002 add sp, #8 80007d4: bce0 pop {r5, r6, r7} 80007d6: 46ba mov sl, r7 80007d8: 46b1 mov r9, r6 80007da: 46a8 mov r8, r5 80007dc: bdf0 pop {r4, r5, r6, r7, pc} 80007de: 077b lsls r3, r7, #29 80007e0: d004 beq.n 80007ec <__aeabi_dadd+0x2b8> 80007e2: 230f movs r3, #15 80007e4: 403b ands r3, r7 80007e6: 2b04 cmp r3, #4 80007e8: d000 beq.n 80007ec <__aeabi_dadd+0x2b8> 80007ea: e728 b.n 800063e <__aeabi_dadd+0x10a> 80007ec: 08f8 lsrs r0, r7, #3 80007ee: 4b34 ldr r3, [pc, #208] @ (80008c0 <__aeabi_dadd+0x38c>) 80007f0: 0777 lsls r7, r6, #29 80007f2: 4307 orrs r7, r0 80007f4: 08f0 lsrs r0, r6, #3 80007f6: 429c cmp r4, r3 80007f8: d000 beq.n 80007fc <__aeabi_dadd+0x2c8> 80007fa: e24a b.n 8000c92 <__aeabi_dadd+0x75e> 80007fc: 003b movs r3, r7 80007fe: 4303 orrs r3, r0 8000800: d059 beq.n 80008b6 <__aeabi_dadd+0x382> 8000802: 2680 movs r6, #128 @ 0x80 8000804: 0336 lsls r6, r6, #12 8000806: 4306 orrs r6, r0 8000808: 0336 lsls r6, r6, #12 800080a: 4c2d ldr r4, [pc, #180] @ (80008c0 <__aeabi_dadd+0x38c>) 800080c: 0b36 lsrs r6, r6, #12 800080e: e7da b.n 80007c6 <__aeabi_dadd+0x292> 8000810: 2900 cmp r1, #0 8000812: d061 beq.n 80008d8 <__aeabi_dadd+0x3a4> 8000814: 4641 mov r1, r8 8000816: 1b09 subs r1, r1, r4 8000818: 2c00 cmp r4, #0 800081a: d100 bne.n 800081e <__aeabi_dadd+0x2ea> 800081c: e0b9 b.n 8000992 <__aeabi_dadd+0x45e> 800081e: 4c28 ldr r4, [pc, #160] @ (80008c0 <__aeabi_dadd+0x38c>) 8000820: 45a0 cmp r8, r4 8000822: d100 bne.n 8000826 <__aeabi_dadd+0x2f2> 8000824: e1a5 b.n 8000b72 <__aeabi_dadd+0x63e> 8000826: 2701 movs r7, #1 8000828: 2938 cmp r1, #56 @ 0x38 800082a: dc13 bgt.n 8000854 <__aeabi_dadd+0x320> 800082c: 2480 movs r4, #128 @ 0x80 800082e: 0424 lsls r4, r4, #16 8000830: 4326 orrs r6, r4 8000832: 291f cmp r1, #31 8000834: dd00 ble.n 8000838 <__aeabi_dadd+0x304> 8000836: e1c8 b.n 8000bca <__aeabi_dadd+0x696> 8000838: 2420 movs r4, #32 800083a: 0037 movs r7, r6 800083c: 4648 mov r0, r9 800083e: 1a64 subs r4, r4, r1 8000840: 40a7 lsls r7, r4 8000842: 40c8 lsrs r0, r1 8000844: 4307 orrs r7, r0 8000846: 4648 mov r0, r9 8000848: 40a0 lsls r0, r4 800084a: 40ce lsrs r6, r1 800084c: 1e44 subs r4, r0, #1 800084e: 41a0 sbcs r0, r4 8000850: 199b adds r3, r3, r6 8000852: 4307 orrs r7, r0 8000854: 18bf adds r7, r7, r2 8000856: 4297 cmp r7, r2 8000858: 4192 sbcs r2, r2 800085a: 4252 negs r2, r2 800085c: 4644 mov r4, r8 800085e: 18d6 adds r6, r2, r3 8000860: e763 b.n 800072a <__aeabi_dadd+0x1f6> 8000862: 0038 movs r0, r7 8000864: f001 fe8a bl 800257c <__clzsi2> 8000868: 0003 movs r3, r0 800086a: 3318 adds r3, #24 800086c: 2b1f cmp r3, #31 800086e: dc00 bgt.n 8000872 <__aeabi_dadd+0x33e> 8000870: e6bf b.n 80005f2 <__aeabi_dadd+0xbe> 8000872: 003a movs r2, r7 8000874: 3808 subs r0, #8 8000876: 4082 lsls r2, r0 8000878: 429c cmp r4, r3 800087a: dd00 ble.n 800087e <__aeabi_dadd+0x34a> 800087c: e083 b.n 8000986 <__aeabi_dadd+0x452> 800087e: 1b1b subs r3, r3, r4 8000880: 1c58 adds r0, r3, #1 8000882: 281f cmp r0, #31 8000884: dc00 bgt.n 8000888 <__aeabi_dadd+0x354> 8000886: e1b4 b.n 8000bf2 <__aeabi_dadd+0x6be> 8000888: 0017 movs r7, r2 800088a: 3b1f subs r3, #31 800088c: 40df lsrs r7, r3 800088e: 2820 cmp r0, #32 8000890: d005 beq.n 800089e <__aeabi_dadd+0x36a> 8000892: 2340 movs r3, #64 @ 0x40 8000894: 1a1b subs r3, r3, r0 8000896: 409a lsls r2, r3 8000898: 1e53 subs r3, r2, #1 800089a: 419a sbcs r2, r3 800089c: 4317 orrs r7, r2 800089e: 2400 movs r4, #0 80008a0: 2f00 cmp r7, #0 80008a2: d00a beq.n 80008ba <__aeabi_dadd+0x386> 80008a4: 077b lsls r3, r7, #29 80008a6: d000 beq.n 80008aa <__aeabi_dadd+0x376> 80008a8: e6c4 b.n 8000634 <__aeabi_dadd+0x100> 80008aa: 0026 movs r6, r4 80008ac: e79e b.n 80007ec <__aeabi_dadd+0x2b8> 80008ae: 464b mov r3, r9 80008b0: 000c movs r4, r1 80008b2: 08d8 lsrs r0, r3, #3 80008b4: e79b b.n 80007ee <__aeabi_dadd+0x2ba> 80008b6: 2700 movs r7, #0 80008b8: 4c01 ldr r4, [pc, #4] @ (80008c0 <__aeabi_dadd+0x38c>) 80008ba: 2600 movs r6, #0 80008bc: e783 b.n 80007c6 <__aeabi_dadd+0x292> 80008be: 46c0 nop @ (mov r8, r8) 80008c0: 000007ff .word 0x000007ff 80008c4: ff7fffff .word 0xff7fffff 80008c8: 000007fe .word 0x000007fe 80008cc: 464b mov r3, r9 80008ce: 0777 lsls r7, r6, #29 80008d0: 08d8 lsrs r0, r3, #3 80008d2: 4307 orrs r7, r0 80008d4: 08f0 lsrs r0, r6, #3 80008d6: e791 b.n 80007fc <__aeabi_dadd+0x2c8> 80008d8: 4fcd ldr r7, [pc, #820] @ (8000c10 <__aeabi_dadd+0x6dc>) 80008da: 1c61 adds r1, r4, #1 80008dc: 4239 tst r1, r7 80008de: d16b bne.n 80009b8 <__aeabi_dadd+0x484> 80008e0: 0031 movs r1, r6 80008e2: 4648 mov r0, r9 80008e4: 4301 orrs r1, r0 80008e6: 2c00 cmp r4, #0 80008e8: d000 beq.n 80008ec <__aeabi_dadd+0x3b8> 80008ea: e14b b.n 8000b84 <__aeabi_dadd+0x650> 80008ec: 001f movs r7, r3 80008ee: 4317 orrs r7, r2 80008f0: 2900 cmp r1, #0 80008f2: d100 bne.n 80008f6 <__aeabi_dadd+0x3c2> 80008f4: e181 b.n 8000bfa <__aeabi_dadd+0x6c6> 80008f6: 2f00 cmp r7, #0 80008f8: d100 bne.n 80008fc <__aeabi_dadd+0x3c8> 80008fa: e74c b.n 8000796 <__aeabi_dadd+0x262> 80008fc: 444a add r2, r9 80008fe: 454a cmp r2, r9 8000900: 4180 sbcs r0, r0 8000902: 18f6 adds r6, r6, r3 8000904: 4240 negs r0, r0 8000906: 1836 adds r6, r6, r0 8000908: 0233 lsls r3, r6, #8 800090a: d500 bpl.n 800090e <__aeabi_dadd+0x3da> 800090c: e1b0 b.n 8000c70 <__aeabi_dadd+0x73c> 800090e: 0017 movs r7, r2 8000910: 4691 mov r9, r2 8000912: 4337 orrs r7, r6 8000914: d000 beq.n 8000918 <__aeabi_dadd+0x3e4> 8000916: e73e b.n 8000796 <__aeabi_dadd+0x262> 8000918: 2600 movs r6, #0 800091a: e754 b.n 80007c6 <__aeabi_dadd+0x292> 800091c: 4649 mov r1, r9 800091e: 1a89 subs r1, r1, r2 8000920: 4688 mov r8, r1 8000922: 45c1 cmp r9, r8 8000924: 41bf sbcs r7, r7 8000926: 1af1 subs r1, r6, r3 8000928: 427f negs r7, r7 800092a: 1bc9 subs r1, r1, r7 800092c: 020f lsls r7, r1, #8 800092e: d461 bmi.n 80009f4 <__aeabi_dadd+0x4c0> 8000930: 4647 mov r7, r8 8000932: 430f orrs r7, r1 8000934: d100 bne.n 8000938 <__aeabi_dadd+0x404> 8000936: e0bd b.n 8000ab4 <__aeabi_dadd+0x580> 8000938: 000e movs r6, r1 800093a: 4647 mov r7, r8 800093c: e651 b.n 80005e2 <__aeabi_dadd+0xae> 800093e: 4cb5 ldr r4, [pc, #724] @ (8000c14 <__aeabi_dadd+0x6e0>) 8000940: 45a0 cmp r8, r4 8000942: d100 bne.n 8000946 <__aeabi_dadd+0x412> 8000944: e100 b.n 8000b48 <__aeabi_dadd+0x614> 8000946: 2701 movs r7, #1 8000948: 2938 cmp r1, #56 @ 0x38 800094a: dd00 ble.n 800094e <__aeabi_dadd+0x41a> 800094c: e6b8 b.n 80006c0 <__aeabi_dadd+0x18c> 800094e: 2480 movs r4, #128 @ 0x80 8000950: 0424 lsls r4, r4, #16 8000952: 4326 orrs r6, r4 8000954: e6a3 b.n 800069e <__aeabi_dadd+0x16a> 8000956: 4eb0 ldr r6, [pc, #704] @ (8000c18 <__aeabi_dadd+0x6e4>) 8000958: 1ae4 subs r4, r4, r3 800095a: 4016 ands r6, r2 800095c: 077b lsls r3, r7, #29 800095e: d000 beq.n 8000962 <__aeabi_dadd+0x42e> 8000960: e73f b.n 80007e2 <__aeabi_dadd+0x2ae> 8000962: e743 b.n 80007ec <__aeabi_dadd+0x2b8> 8000964: 000f movs r7, r1 8000966: 0018 movs r0, r3 8000968: 3f20 subs r7, #32 800096a: 40f8 lsrs r0, r7 800096c: 4684 mov ip, r0 800096e: 2920 cmp r1, #32 8000970: d003 beq.n 800097a <__aeabi_dadd+0x446> 8000972: 2740 movs r7, #64 @ 0x40 8000974: 1a79 subs r1, r7, r1 8000976: 408b lsls r3, r1 8000978: 431a orrs r2, r3 800097a: 1e53 subs r3, r2, #1 800097c: 419a sbcs r2, r3 800097e: 4663 mov r3, ip 8000980: 0017 movs r7, r2 8000982: 431f orrs r7, r3 8000984: e622 b.n 80005cc <__aeabi_dadd+0x98> 8000986: 48a4 ldr r0, [pc, #656] @ (8000c18 <__aeabi_dadd+0x6e4>) 8000988: 1ae1 subs r1, r4, r3 800098a: 4010 ands r0, r2 800098c: 0747 lsls r7, r0, #29 800098e: 08c0 lsrs r0, r0, #3 8000990: e707 b.n 80007a2 <__aeabi_dadd+0x26e> 8000992: 0034 movs r4, r6 8000994: 4648 mov r0, r9 8000996: 4304 orrs r4, r0 8000998: d100 bne.n 800099c <__aeabi_dadd+0x468> 800099a: e0fa b.n 8000b92 <__aeabi_dadd+0x65e> 800099c: 1e4c subs r4, r1, #1 800099e: 2901 cmp r1, #1 80009a0: d100 bne.n 80009a4 <__aeabi_dadd+0x470> 80009a2: e0d7 b.n 8000b54 <__aeabi_dadd+0x620> 80009a4: 4f9b ldr r7, [pc, #620] @ (8000c14 <__aeabi_dadd+0x6e0>) 80009a6: 42b9 cmp r1, r7 80009a8: d100 bne.n 80009ac <__aeabi_dadd+0x478> 80009aa: e0e2 b.n 8000b72 <__aeabi_dadd+0x63e> 80009ac: 2701 movs r7, #1 80009ae: 2c38 cmp r4, #56 @ 0x38 80009b0: dd00 ble.n 80009b4 <__aeabi_dadd+0x480> 80009b2: e74f b.n 8000854 <__aeabi_dadd+0x320> 80009b4: 0021 movs r1, r4 80009b6: e73c b.n 8000832 <__aeabi_dadd+0x2fe> 80009b8: 4c96 ldr r4, [pc, #600] @ (8000c14 <__aeabi_dadd+0x6e0>) 80009ba: 42a1 cmp r1, r4 80009bc: d100 bne.n 80009c0 <__aeabi_dadd+0x48c> 80009be: e0dd b.n 8000b7c <__aeabi_dadd+0x648> 80009c0: 444a add r2, r9 80009c2: 454a cmp r2, r9 80009c4: 4180 sbcs r0, r0 80009c6: 18f3 adds r3, r6, r3 80009c8: 4240 negs r0, r0 80009ca: 1818 adds r0, r3, r0 80009cc: 07c7 lsls r7, r0, #31 80009ce: 0852 lsrs r2, r2, #1 80009d0: 4317 orrs r7, r2 80009d2: 0846 lsrs r6, r0, #1 80009d4: 0752 lsls r2, r2, #29 80009d6: d005 beq.n 80009e4 <__aeabi_dadd+0x4b0> 80009d8: 220f movs r2, #15 80009da: 000c movs r4, r1 80009dc: 403a ands r2, r7 80009de: 2a04 cmp r2, #4 80009e0: d000 beq.n 80009e4 <__aeabi_dadd+0x4b0> 80009e2: e62c b.n 800063e <__aeabi_dadd+0x10a> 80009e4: 0776 lsls r6, r6, #29 80009e6: 08ff lsrs r7, r7, #3 80009e8: 4337 orrs r7, r6 80009ea: 0900 lsrs r0, r0, #4 80009ec: e6d9 b.n 80007a2 <__aeabi_dadd+0x26e> 80009ee: 2700 movs r7, #0 80009f0: 2600 movs r6, #0 80009f2: e6e8 b.n 80007c6 <__aeabi_dadd+0x292> 80009f4: 4649 mov r1, r9 80009f6: 1a57 subs r7, r2, r1 80009f8: 42ba cmp r2, r7 80009fa: 4192 sbcs r2, r2 80009fc: 1b9e subs r6, r3, r6 80009fe: 4252 negs r2, r2 8000a00: 4665 mov r5, ip 8000a02: 1ab6 subs r6, r6, r2 8000a04: e5ed b.n 80005e2 <__aeabi_dadd+0xae> 8000a06: 2900 cmp r1, #0 8000a08: d000 beq.n 8000a0c <__aeabi_dadd+0x4d8> 8000a0a: e0c6 b.n 8000b9a <__aeabi_dadd+0x666> 8000a0c: 2f00 cmp r7, #0 8000a0e: d167 bne.n 8000ae0 <__aeabi_dadd+0x5ac> 8000a10: 2680 movs r6, #128 @ 0x80 8000a12: 2500 movs r5, #0 8000a14: 4c7f ldr r4, [pc, #508] @ (8000c14 <__aeabi_dadd+0x6e0>) 8000a16: 0336 lsls r6, r6, #12 8000a18: e6d5 b.n 80007c6 <__aeabi_dadd+0x292> 8000a1a: 4665 mov r5, ip 8000a1c: 000c movs r4, r1 8000a1e: 001e movs r6, r3 8000a20: 08d0 lsrs r0, r2, #3 8000a22: e6e4 b.n 80007ee <__aeabi_dadd+0x2ba> 8000a24: 444a add r2, r9 8000a26: 454a cmp r2, r9 8000a28: 4180 sbcs r0, r0 8000a2a: 18f3 adds r3, r6, r3 8000a2c: 4240 negs r0, r0 8000a2e: 1818 adds r0, r3, r0 8000a30: 0011 movs r1, r2 8000a32: 0203 lsls r3, r0, #8 8000a34: d400 bmi.n 8000a38 <__aeabi_dadd+0x504> 8000a36: e096 b.n 8000b66 <__aeabi_dadd+0x632> 8000a38: 4b77 ldr r3, [pc, #476] @ (8000c18 <__aeabi_dadd+0x6e4>) 8000a3a: 0849 lsrs r1, r1, #1 8000a3c: 4018 ands r0, r3 8000a3e: 07c3 lsls r3, r0, #31 8000a40: 430b orrs r3, r1 8000a42: 0844 lsrs r4, r0, #1 8000a44: 0749 lsls r1, r1, #29 8000a46: d100 bne.n 8000a4a <__aeabi_dadd+0x516> 8000a48: e129 b.n 8000c9e <__aeabi_dadd+0x76a> 8000a4a: 220f movs r2, #15 8000a4c: 401a ands r2, r3 8000a4e: 2a04 cmp r2, #4 8000a50: d100 bne.n 8000a54 <__aeabi_dadd+0x520> 8000a52: e0ea b.n 8000c2a <__aeabi_dadd+0x6f6> 8000a54: 1d1f adds r7, r3, #4 8000a56: 429f cmp r7, r3 8000a58: 41b6 sbcs r6, r6 8000a5a: 4276 negs r6, r6 8000a5c: 1936 adds r6, r6, r4 8000a5e: 2402 movs r4, #2 8000a60: e6c4 b.n 80007ec <__aeabi_dadd+0x2b8> 8000a62: 4649 mov r1, r9 8000a64: 1a8f subs r7, r1, r2 8000a66: 45b9 cmp r9, r7 8000a68: 4180 sbcs r0, r0 8000a6a: 1af6 subs r6, r6, r3 8000a6c: 4240 negs r0, r0 8000a6e: 1a36 subs r6, r6, r0 8000a70: 0233 lsls r3, r6, #8 8000a72: d406 bmi.n 8000a82 <__aeabi_dadd+0x54e> 8000a74: 0773 lsls r3, r6, #29 8000a76: 08ff lsrs r7, r7, #3 8000a78: 2101 movs r1, #1 8000a7a: 431f orrs r7, r3 8000a7c: 08f0 lsrs r0, r6, #3 8000a7e: e690 b.n 80007a2 <__aeabi_dadd+0x26e> 8000a80: 4665 mov r5, ip 8000a82: 2401 movs r4, #1 8000a84: e5ab b.n 80005de <__aeabi_dadd+0xaa> 8000a86: 464b mov r3, r9 8000a88: 0777 lsls r7, r6, #29 8000a8a: 08d8 lsrs r0, r3, #3 8000a8c: 4307 orrs r7, r0 8000a8e: 08f0 lsrs r0, r6, #3 8000a90: e6b4 b.n 80007fc <__aeabi_dadd+0x2c8> 8000a92: 000f movs r7, r1 8000a94: 0018 movs r0, r3 8000a96: 3f20 subs r7, #32 8000a98: 40f8 lsrs r0, r7 8000a9a: 4684 mov ip, r0 8000a9c: 2920 cmp r1, #32 8000a9e: d003 beq.n 8000aa8 <__aeabi_dadd+0x574> 8000aa0: 2740 movs r7, #64 @ 0x40 8000aa2: 1a79 subs r1, r7, r1 8000aa4: 408b lsls r3, r1 8000aa6: 431a orrs r2, r3 8000aa8: 1e53 subs r3, r2, #1 8000aaa: 419a sbcs r2, r3 8000aac: 4663 mov r3, ip 8000aae: 0017 movs r7, r2 8000ab0: 431f orrs r7, r3 8000ab2: e635 b.n 8000720 <__aeabi_dadd+0x1ec> 8000ab4: 2500 movs r5, #0 8000ab6: 2400 movs r4, #0 8000ab8: 2600 movs r6, #0 8000aba: e684 b.n 80007c6 <__aeabi_dadd+0x292> 8000abc: 000c movs r4, r1 8000abe: 0035 movs r5, r6 8000ac0: 3c20 subs r4, #32 8000ac2: 40e5 lsrs r5, r4 8000ac4: 2920 cmp r1, #32 8000ac6: d005 beq.n 8000ad4 <__aeabi_dadd+0x5a0> 8000ac8: 2440 movs r4, #64 @ 0x40 8000aca: 1a61 subs r1, r4, r1 8000acc: 408e lsls r6, r1 8000ace: 4649 mov r1, r9 8000ad0: 4331 orrs r1, r6 8000ad2: 4689 mov r9, r1 8000ad4: 4648 mov r0, r9 8000ad6: 1e41 subs r1, r0, #1 8000ad8: 4188 sbcs r0, r1 8000ada: 0007 movs r7, r0 8000adc: 432f orrs r7, r5 8000ade: e5ef b.n 80006c0 <__aeabi_dadd+0x18c> 8000ae0: 08d2 lsrs r2, r2, #3 8000ae2: 075f lsls r7, r3, #29 8000ae4: 4665 mov r5, ip 8000ae6: 4317 orrs r7, r2 8000ae8: 08d8 lsrs r0, r3, #3 8000aea: e687 b.n 80007fc <__aeabi_dadd+0x2c8> 8000aec: 1a17 subs r7, r2, r0 8000aee: 42ba cmp r2, r7 8000af0: 4192 sbcs r2, r2 8000af2: 1b9e subs r6, r3, r6 8000af4: 4252 negs r2, r2 8000af6: 1ab6 subs r6, r6, r2 8000af8: 0233 lsls r3, r6, #8 8000afa: d4c1 bmi.n 8000a80 <__aeabi_dadd+0x54c> 8000afc: 0773 lsls r3, r6, #29 8000afe: 08ff lsrs r7, r7, #3 8000b00: 4665 mov r5, ip 8000b02: 2101 movs r1, #1 8000b04: 431f orrs r7, r3 8000b06: 08f0 lsrs r0, r6, #3 8000b08: e64b b.n 80007a2 <__aeabi_dadd+0x26e> 8000b0a: 2f00 cmp r7, #0 8000b0c: d07b beq.n 8000c06 <__aeabi_dadd+0x6d2> 8000b0e: 4665 mov r5, ip 8000b10: 001e movs r6, r3 8000b12: 4691 mov r9, r2 8000b14: e63f b.n 8000796 <__aeabi_dadd+0x262> 8000b16: 1a81 subs r1, r0, r2 8000b18: 4688 mov r8, r1 8000b1a: 45c1 cmp r9, r8 8000b1c: 41a4 sbcs r4, r4 8000b1e: 1af1 subs r1, r6, r3 8000b20: 4264 negs r4, r4 8000b22: 1b09 subs r1, r1, r4 8000b24: 2480 movs r4, #128 @ 0x80 8000b26: 0424 lsls r4, r4, #16 8000b28: 4221 tst r1, r4 8000b2a: d077 beq.n 8000c1c <__aeabi_dadd+0x6e8> 8000b2c: 1a10 subs r0, r2, r0 8000b2e: 4282 cmp r2, r0 8000b30: 4192 sbcs r2, r2 8000b32: 0007 movs r7, r0 8000b34: 1b9e subs r6, r3, r6 8000b36: 4252 negs r2, r2 8000b38: 1ab6 subs r6, r6, r2 8000b3a: 4337 orrs r7, r6 8000b3c: d000 beq.n 8000b40 <__aeabi_dadd+0x60c> 8000b3e: e0a0 b.n 8000c82 <__aeabi_dadd+0x74e> 8000b40: 4665 mov r5, ip 8000b42: 2400 movs r4, #0 8000b44: 2600 movs r6, #0 8000b46: e63e b.n 80007c6 <__aeabi_dadd+0x292> 8000b48: 075f lsls r7, r3, #29 8000b4a: 08d2 lsrs r2, r2, #3 8000b4c: 4665 mov r5, ip 8000b4e: 4317 orrs r7, r2 8000b50: 08d8 lsrs r0, r3, #3 8000b52: e653 b.n 80007fc <__aeabi_dadd+0x2c8> 8000b54: 1881 adds r1, r0, r2 8000b56: 4291 cmp r1, r2 8000b58: 4192 sbcs r2, r2 8000b5a: 18f0 adds r0, r6, r3 8000b5c: 4252 negs r2, r2 8000b5e: 1880 adds r0, r0, r2 8000b60: 0203 lsls r3, r0, #8 8000b62: d500 bpl.n 8000b66 <__aeabi_dadd+0x632> 8000b64: e768 b.n 8000a38 <__aeabi_dadd+0x504> 8000b66: 0747 lsls r7, r0, #29 8000b68: 08c9 lsrs r1, r1, #3 8000b6a: 430f orrs r7, r1 8000b6c: 08c0 lsrs r0, r0, #3 8000b6e: 2101 movs r1, #1 8000b70: e617 b.n 80007a2 <__aeabi_dadd+0x26e> 8000b72: 08d2 lsrs r2, r2, #3 8000b74: 075f lsls r7, r3, #29 8000b76: 4317 orrs r7, r2 8000b78: 08d8 lsrs r0, r3, #3 8000b7a: e63f b.n 80007fc <__aeabi_dadd+0x2c8> 8000b7c: 000c movs r4, r1 8000b7e: 2600 movs r6, #0 8000b80: 2700 movs r7, #0 8000b82: e620 b.n 80007c6 <__aeabi_dadd+0x292> 8000b84: 2900 cmp r1, #0 8000b86: d156 bne.n 8000c36 <__aeabi_dadd+0x702> 8000b88: 075f lsls r7, r3, #29 8000b8a: 08d2 lsrs r2, r2, #3 8000b8c: 4317 orrs r7, r2 8000b8e: 08d8 lsrs r0, r3, #3 8000b90: e634 b.n 80007fc <__aeabi_dadd+0x2c8> 8000b92: 000c movs r4, r1 8000b94: 001e movs r6, r3 8000b96: 08d0 lsrs r0, r2, #3 8000b98: e629 b.n 80007ee <__aeabi_dadd+0x2ba> 8000b9a: 08c1 lsrs r1, r0, #3 8000b9c: 0770 lsls r0, r6, #29 8000b9e: 4301 orrs r1, r0 8000ba0: 08f0 lsrs r0, r6, #3 8000ba2: 2f00 cmp r7, #0 8000ba4: d062 beq.n 8000c6c <__aeabi_dadd+0x738> 8000ba6: 2480 movs r4, #128 @ 0x80 8000ba8: 0324 lsls r4, r4, #12 8000baa: 4220 tst r0, r4 8000bac: d007 beq.n 8000bbe <__aeabi_dadd+0x68a> 8000bae: 08de lsrs r6, r3, #3 8000bb0: 4226 tst r6, r4 8000bb2: d104 bne.n 8000bbe <__aeabi_dadd+0x68a> 8000bb4: 4665 mov r5, ip 8000bb6: 0030 movs r0, r6 8000bb8: 08d1 lsrs r1, r2, #3 8000bba: 075b lsls r3, r3, #29 8000bbc: 4319 orrs r1, r3 8000bbe: 0f4f lsrs r7, r1, #29 8000bc0: 00c9 lsls r1, r1, #3 8000bc2: 08c9 lsrs r1, r1, #3 8000bc4: 077f lsls r7, r7, #29 8000bc6: 430f orrs r7, r1 8000bc8: e618 b.n 80007fc <__aeabi_dadd+0x2c8> 8000bca: 000c movs r4, r1 8000bcc: 0030 movs r0, r6 8000bce: 3c20 subs r4, #32 8000bd0: 40e0 lsrs r0, r4 8000bd2: 4684 mov ip, r0 8000bd4: 2920 cmp r1, #32 8000bd6: d005 beq.n 8000be4 <__aeabi_dadd+0x6b0> 8000bd8: 2440 movs r4, #64 @ 0x40 8000bda: 1a61 subs r1, r4, r1 8000bdc: 408e lsls r6, r1 8000bde: 4649 mov r1, r9 8000be0: 4331 orrs r1, r6 8000be2: 4689 mov r9, r1 8000be4: 4648 mov r0, r9 8000be6: 1e41 subs r1, r0, #1 8000be8: 4188 sbcs r0, r1 8000bea: 4661 mov r1, ip 8000bec: 0007 movs r7, r0 8000bee: 430f orrs r7, r1 8000bf0: e630 b.n 8000854 <__aeabi_dadd+0x320> 8000bf2: 2120 movs r1, #32 8000bf4: 2700 movs r7, #0 8000bf6: 1a09 subs r1, r1, r0 8000bf8: e50e b.n 8000618 <__aeabi_dadd+0xe4> 8000bfa: 001e movs r6, r3 8000bfc: 2f00 cmp r7, #0 8000bfe: d000 beq.n 8000c02 <__aeabi_dadd+0x6ce> 8000c00: e522 b.n 8000648 <__aeabi_dadd+0x114> 8000c02: 2400 movs r4, #0 8000c04: e758 b.n 8000ab8 <__aeabi_dadd+0x584> 8000c06: 2500 movs r5, #0 8000c08: 2400 movs r4, #0 8000c0a: 2600 movs r6, #0 8000c0c: e5db b.n 80007c6 <__aeabi_dadd+0x292> 8000c0e: 46c0 nop @ (mov r8, r8) 8000c10: 000007fe .word 0x000007fe 8000c14: 000007ff .word 0x000007ff 8000c18: ff7fffff .word 0xff7fffff 8000c1c: 4647 mov r7, r8 8000c1e: 430f orrs r7, r1 8000c20: d100 bne.n 8000c24 <__aeabi_dadd+0x6f0> 8000c22: e747 b.n 8000ab4 <__aeabi_dadd+0x580> 8000c24: 000e movs r6, r1 8000c26: 46c1 mov r9, r8 8000c28: e5b5 b.n 8000796 <__aeabi_dadd+0x262> 8000c2a: 08df lsrs r7, r3, #3 8000c2c: 0764 lsls r4, r4, #29 8000c2e: 2102 movs r1, #2 8000c30: 4327 orrs r7, r4 8000c32: 0900 lsrs r0, r0, #4 8000c34: e5b5 b.n 80007a2 <__aeabi_dadd+0x26e> 8000c36: 0019 movs r1, r3 8000c38: 08c0 lsrs r0, r0, #3 8000c3a: 0777 lsls r7, r6, #29 8000c3c: 4307 orrs r7, r0 8000c3e: 4311 orrs r1, r2 8000c40: 08f0 lsrs r0, r6, #3 8000c42: 2900 cmp r1, #0 8000c44: d100 bne.n 8000c48 <__aeabi_dadd+0x714> 8000c46: e5d9 b.n 80007fc <__aeabi_dadd+0x2c8> 8000c48: 2180 movs r1, #128 @ 0x80 8000c4a: 0309 lsls r1, r1, #12 8000c4c: 4208 tst r0, r1 8000c4e: d007 beq.n 8000c60 <__aeabi_dadd+0x72c> 8000c50: 08dc lsrs r4, r3, #3 8000c52: 420c tst r4, r1 8000c54: d104 bne.n 8000c60 <__aeabi_dadd+0x72c> 8000c56: 08d2 lsrs r2, r2, #3 8000c58: 075b lsls r3, r3, #29 8000c5a: 431a orrs r2, r3 8000c5c: 0017 movs r7, r2 8000c5e: 0020 movs r0, r4 8000c60: 0f7b lsrs r3, r7, #29 8000c62: 00ff lsls r7, r7, #3 8000c64: 08ff lsrs r7, r7, #3 8000c66: 075b lsls r3, r3, #29 8000c68: 431f orrs r7, r3 8000c6a: e5c7 b.n 80007fc <__aeabi_dadd+0x2c8> 8000c6c: 000f movs r7, r1 8000c6e: e5c5 b.n 80007fc <__aeabi_dadd+0x2c8> 8000c70: 4b12 ldr r3, [pc, #72] @ (8000cbc <__aeabi_dadd+0x788>) 8000c72: 08d2 lsrs r2, r2, #3 8000c74: 4033 ands r3, r6 8000c76: 075f lsls r7, r3, #29 8000c78: 025b lsls r3, r3, #9 8000c7a: 2401 movs r4, #1 8000c7c: 4317 orrs r7, r2 8000c7e: 0b1e lsrs r6, r3, #12 8000c80: e5a1 b.n 80007c6 <__aeabi_dadd+0x292> 8000c82: 4226 tst r6, r4 8000c84: d012 beq.n 8000cac <__aeabi_dadd+0x778> 8000c86: 4b0d ldr r3, [pc, #52] @ (8000cbc <__aeabi_dadd+0x788>) 8000c88: 4665 mov r5, ip 8000c8a: 0002 movs r2, r0 8000c8c: 2401 movs r4, #1 8000c8e: 401e ands r6, r3 8000c90: e4e6 b.n 8000660 <__aeabi_dadd+0x12c> 8000c92: 0021 movs r1, r4 8000c94: e585 b.n 80007a2 <__aeabi_dadd+0x26e> 8000c96: 0017 movs r7, r2 8000c98: e5a8 b.n 80007ec <__aeabi_dadd+0x2b8> 8000c9a: 003a movs r2, r7 8000c9c: e4d4 b.n 8000648 <__aeabi_dadd+0x114> 8000c9e: 08db lsrs r3, r3, #3 8000ca0: 0764 lsls r4, r4, #29 8000ca2: 431c orrs r4, r3 8000ca4: 0027 movs r7, r4 8000ca6: 2102 movs r1, #2 8000ca8: 0900 lsrs r0, r0, #4 8000caa: e57a b.n 80007a2 <__aeabi_dadd+0x26e> 8000cac: 08c0 lsrs r0, r0, #3 8000cae: 0777 lsls r7, r6, #29 8000cb0: 4307 orrs r7, r0 8000cb2: 4665 mov r5, ip 8000cb4: 2100 movs r1, #0 8000cb6: 08f0 lsrs r0, r6, #3 8000cb8: e573 b.n 80007a2 <__aeabi_dadd+0x26e> 8000cba: 46c0 nop @ (mov r8, r8) 8000cbc: ff7fffff .word 0xff7fffff 08000cc0 <__aeabi_ddiv>: 8000cc0: b5f0 push {r4, r5, r6, r7, lr} 8000cc2: 46de mov lr, fp 8000cc4: 4645 mov r5, r8 8000cc6: 4657 mov r7, sl 8000cc8: 464e mov r6, r9 8000cca: b5e0 push {r5, r6, r7, lr} 8000ccc: b087 sub sp, #28 8000cce: 9200 str r2, [sp, #0] 8000cd0: 9301 str r3, [sp, #4] 8000cd2: 030b lsls r3, r1, #12 8000cd4: 0b1b lsrs r3, r3, #12 8000cd6: 469b mov fp, r3 8000cd8: 0fca lsrs r2, r1, #31 8000cda: 004b lsls r3, r1, #1 8000cdc: 0004 movs r4, r0 8000cde: 4680 mov r8, r0 8000ce0: 0d5b lsrs r3, r3, #21 8000ce2: 9202 str r2, [sp, #8] 8000ce4: d100 bne.n 8000ce8 <__aeabi_ddiv+0x28> 8000ce6: e098 b.n 8000e1a <__aeabi_ddiv+0x15a> 8000ce8: 4a7c ldr r2, [pc, #496] @ (8000edc <__aeabi_ddiv+0x21c>) 8000cea: 4293 cmp r3, r2 8000cec: d037 beq.n 8000d5e <__aeabi_ddiv+0x9e> 8000cee: 4659 mov r1, fp 8000cf0: 0f42 lsrs r2, r0, #29 8000cf2: 00c9 lsls r1, r1, #3 8000cf4: 430a orrs r2, r1 8000cf6: 2180 movs r1, #128 @ 0x80 8000cf8: 0409 lsls r1, r1, #16 8000cfa: 4311 orrs r1, r2 8000cfc: 00c2 lsls r2, r0, #3 8000cfe: 4690 mov r8, r2 8000d00: 4a77 ldr r2, [pc, #476] @ (8000ee0 <__aeabi_ddiv+0x220>) 8000d02: 4689 mov r9, r1 8000d04: 4692 mov sl, r2 8000d06: 449a add sl, r3 8000d08: 2300 movs r3, #0 8000d0a: 2400 movs r4, #0 8000d0c: 9303 str r3, [sp, #12] 8000d0e: 9e00 ldr r6, [sp, #0] 8000d10: 9f01 ldr r7, [sp, #4] 8000d12: 033b lsls r3, r7, #12 8000d14: 0b1b lsrs r3, r3, #12 8000d16: 469b mov fp, r3 8000d18: 007b lsls r3, r7, #1 8000d1a: 0030 movs r0, r6 8000d1c: 0d5b lsrs r3, r3, #21 8000d1e: 0ffd lsrs r5, r7, #31 8000d20: 2b00 cmp r3, #0 8000d22: d059 beq.n 8000dd8 <__aeabi_ddiv+0x118> 8000d24: 4a6d ldr r2, [pc, #436] @ (8000edc <__aeabi_ddiv+0x21c>) 8000d26: 4293 cmp r3, r2 8000d28: d048 beq.n 8000dbc <__aeabi_ddiv+0xfc> 8000d2a: 4659 mov r1, fp 8000d2c: 0f72 lsrs r2, r6, #29 8000d2e: 00c9 lsls r1, r1, #3 8000d30: 430a orrs r2, r1 8000d32: 2180 movs r1, #128 @ 0x80 8000d34: 0409 lsls r1, r1, #16 8000d36: 4311 orrs r1, r2 8000d38: 468b mov fp, r1 8000d3a: 4969 ldr r1, [pc, #420] @ (8000ee0 <__aeabi_ddiv+0x220>) 8000d3c: 00f2 lsls r2, r6, #3 8000d3e: 468c mov ip, r1 8000d40: 4651 mov r1, sl 8000d42: 4463 add r3, ip 8000d44: 1acb subs r3, r1, r3 8000d46: 469a mov sl, r3 8000d48: 2100 movs r1, #0 8000d4a: 9e02 ldr r6, [sp, #8] 8000d4c: 406e eors r6, r5 8000d4e: b2f6 uxtb r6, r6 8000d50: 2c0f cmp r4, #15 8000d52: d900 bls.n 8000d56 <__aeabi_ddiv+0x96> 8000d54: e0ce b.n 8000ef4 <__aeabi_ddiv+0x234> 8000d56: 4b63 ldr r3, [pc, #396] @ (8000ee4 <__aeabi_ddiv+0x224>) 8000d58: 00a4 lsls r4, r4, #2 8000d5a: 591b ldr r3, [r3, r4] 8000d5c: 469f mov pc, r3 8000d5e: 465a mov r2, fp 8000d60: 4302 orrs r2, r0 8000d62: 4691 mov r9, r2 8000d64: d000 beq.n 8000d68 <__aeabi_ddiv+0xa8> 8000d66: e090 b.n 8000e8a <__aeabi_ddiv+0x1ca> 8000d68: 469a mov sl, r3 8000d6a: 2302 movs r3, #2 8000d6c: 4690 mov r8, r2 8000d6e: 2408 movs r4, #8 8000d70: 9303 str r3, [sp, #12] 8000d72: e7cc b.n 8000d0e <__aeabi_ddiv+0x4e> 8000d74: 46cb mov fp, r9 8000d76: 4642 mov r2, r8 8000d78: 9d02 ldr r5, [sp, #8] 8000d7a: 9903 ldr r1, [sp, #12] 8000d7c: 2902 cmp r1, #2 8000d7e: d100 bne.n 8000d82 <__aeabi_ddiv+0xc2> 8000d80: e1de b.n 8001140 <__aeabi_ddiv+0x480> 8000d82: 2903 cmp r1, #3 8000d84: d100 bne.n 8000d88 <__aeabi_ddiv+0xc8> 8000d86: e08d b.n 8000ea4 <__aeabi_ddiv+0x1e4> 8000d88: 2901 cmp r1, #1 8000d8a: d000 beq.n 8000d8e <__aeabi_ddiv+0xce> 8000d8c: e179 b.n 8001082 <__aeabi_ddiv+0x3c2> 8000d8e: 002e movs r6, r5 8000d90: 2200 movs r2, #0 8000d92: 2300 movs r3, #0 8000d94: 2400 movs r4, #0 8000d96: 4690 mov r8, r2 8000d98: 051b lsls r3, r3, #20 8000d9a: 4323 orrs r3, r4 8000d9c: 07f6 lsls r6, r6, #31 8000d9e: 4333 orrs r3, r6 8000da0: 4640 mov r0, r8 8000da2: 0019 movs r1, r3 8000da4: b007 add sp, #28 8000da6: bcf0 pop {r4, r5, r6, r7} 8000da8: 46bb mov fp, r7 8000daa: 46b2 mov sl, r6 8000dac: 46a9 mov r9, r5 8000dae: 46a0 mov r8, r4 8000db0: bdf0 pop {r4, r5, r6, r7, pc} 8000db2: 2200 movs r2, #0 8000db4: 2400 movs r4, #0 8000db6: 4690 mov r8, r2 8000db8: 4b48 ldr r3, [pc, #288] @ (8000edc <__aeabi_ddiv+0x21c>) 8000dba: e7ed b.n 8000d98 <__aeabi_ddiv+0xd8> 8000dbc: 465a mov r2, fp 8000dbe: 9b00 ldr r3, [sp, #0] 8000dc0: 431a orrs r2, r3 8000dc2: 4b49 ldr r3, [pc, #292] @ (8000ee8 <__aeabi_ddiv+0x228>) 8000dc4: 469c mov ip, r3 8000dc6: 44e2 add sl, ip 8000dc8: 2a00 cmp r2, #0 8000dca: d159 bne.n 8000e80 <__aeabi_ddiv+0x1c0> 8000dcc: 2302 movs r3, #2 8000dce: 431c orrs r4, r3 8000dd0: 2300 movs r3, #0 8000dd2: 2102 movs r1, #2 8000dd4: 469b mov fp, r3 8000dd6: e7b8 b.n 8000d4a <__aeabi_ddiv+0x8a> 8000dd8: 465a mov r2, fp 8000dda: 9b00 ldr r3, [sp, #0] 8000ddc: 431a orrs r2, r3 8000dde: d049 beq.n 8000e74 <__aeabi_ddiv+0x1b4> 8000de0: 465b mov r3, fp 8000de2: 2b00 cmp r3, #0 8000de4: d100 bne.n 8000de8 <__aeabi_ddiv+0x128> 8000de6: e19c b.n 8001122 <__aeabi_ddiv+0x462> 8000de8: 4658 mov r0, fp 8000dea: f001 fbc7 bl 800257c <__clzsi2> 8000dee: 0002 movs r2, r0 8000df0: 0003 movs r3, r0 8000df2: 3a0b subs r2, #11 8000df4: 271d movs r7, #29 8000df6: 9e00 ldr r6, [sp, #0] 8000df8: 1aba subs r2, r7, r2 8000dfa: 0019 movs r1, r3 8000dfc: 4658 mov r0, fp 8000dfe: 40d6 lsrs r6, r2 8000e00: 3908 subs r1, #8 8000e02: 4088 lsls r0, r1 8000e04: 0032 movs r2, r6 8000e06: 4302 orrs r2, r0 8000e08: 4693 mov fp, r2 8000e0a: 9a00 ldr r2, [sp, #0] 8000e0c: 408a lsls r2, r1 8000e0e: 4937 ldr r1, [pc, #220] @ (8000eec <__aeabi_ddiv+0x22c>) 8000e10: 4453 add r3, sl 8000e12: 468a mov sl, r1 8000e14: 2100 movs r1, #0 8000e16: 449a add sl, r3 8000e18: e797 b.n 8000d4a <__aeabi_ddiv+0x8a> 8000e1a: 465b mov r3, fp 8000e1c: 4303 orrs r3, r0 8000e1e: 4699 mov r9, r3 8000e20: d021 beq.n 8000e66 <__aeabi_ddiv+0x1a6> 8000e22: 465b mov r3, fp 8000e24: 2b00 cmp r3, #0 8000e26: d100 bne.n 8000e2a <__aeabi_ddiv+0x16a> 8000e28: e169 b.n 80010fe <__aeabi_ddiv+0x43e> 8000e2a: 4658 mov r0, fp 8000e2c: f001 fba6 bl 800257c <__clzsi2> 8000e30: 230b movs r3, #11 8000e32: 425b negs r3, r3 8000e34: 469c mov ip, r3 8000e36: 0002 movs r2, r0 8000e38: 4484 add ip, r0 8000e3a: 4666 mov r6, ip 8000e3c: 231d movs r3, #29 8000e3e: 1b9b subs r3, r3, r6 8000e40: 0026 movs r6, r4 8000e42: 0011 movs r1, r2 8000e44: 4658 mov r0, fp 8000e46: 40de lsrs r6, r3 8000e48: 3908 subs r1, #8 8000e4a: 4088 lsls r0, r1 8000e4c: 0033 movs r3, r6 8000e4e: 4303 orrs r3, r0 8000e50: 4699 mov r9, r3 8000e52: 0023 movs r3, r4 8000e54: 408b lsls r3, r1 8000e56: 4698 mov r8, r3 8000e58: 4b25 ldr r3, [pc, #148] @ (8000ef0 <__aeabi_ddiv+0x230>) 8000e5a: 2400 movs r4, #0 8000e5c: 1a9b subs r3, r3, r2 8000e5e: 469a mov sl, r3 8000e60: 2300 movs r3, #0 8000e62: 9303 str r3, [sp, #12] 8000e64: e753 b.n 8000d0e <__aeabi_ddiv+0x4e> 8000e66: 2300 movs r3, #0 8000e68: 4698 mov r8, r3 8000e6a: 469a mov sl, r3 8000e6c: 3301 adds r3, #1 8000e6e: 2404 movs r4, #4 8000e70: 9303 str r3, [sp, #12] 8000e72: e74c b.n 8000d0e <__aeabi_ddiv+0x4e> 8000e74: 2301 movs r3, #1 8000e76: 431c orrs r4, r3 8000e78: 2300 movs r3, #0 8000e7a: 2101 movs r1, #1 8000e7c: 469b mov fp, r3 8000e7e: e764 b.n 8000d4a <__aeabi_ddiv+0x8a> 8000e80: 2303 movs r3, #3 8000e82: 0032 movs r2, r6 8000e84: 2103 movs r1, #3 8000e86: 431c orrs r4, r3 8000e88: e75f b.n 8000d4a <__aeabi_ddiv+0x8a> 8000e8a: 469a mov sl, r3 8000e8c: 2303 movs r3, #3 8000e8e: 46d9 mov r9, fp 8000e90: 240c movs r4, #12 8000e92: 9303 str r3, [sp, #12] 8000e94: e73b b.n 8000d0e <__aeabi_ddiv+0x4e> 8000e96: 2300 movs r3, #0 8000e98: 2480 movs r4, #128 @ 0x80 8000e9a: 4698 mov r8, r3 8000e9c: 2600 movs r6, #0 8000e9e: 4b0f ldr r3, [pc, #60] @ (8000edc <__aeabi_ddiv+0x21c>) 8000ea0: 0324 lsls r4, r4, #12 8000ea2: e779 b.n 8000d98 <__aeabi_ddiv+0xd8> 8000ea4: 2480 movs r4, #128 @ 0x80 8000ea6: 465b mov r3, fp 8000ea8: 0324 lsls r4, r4, #12 8000eaa: 431c orrs r4, r3 8000eac: 0324 lsls r4, r4, #12 8000eae: 002e movs r6, r5 8000eb0: 4690 mov r8, r2 8000eb2: 4b0a ldr r3, [pc, #40] @ (8000edc <__aeabi_ddiv+0x21c>) 8000eb4: 0b24 lsrs r4, r4, #12 8000eb6: e76f b.n 8000d98 <__aeabi_ddiv+0xd8> 8000eb8: 2480 movs r4, #128 @ 0x80 8000eba: 464b mov r3, r9 8000ebc: 0324 lsls r4, r4, #12 8000ebe: 4223 tst r3, r4 8000ec0: d002 beq.n 8000ec8 <__aeabi_ddiv+0x208> 8000ec2: 465b mov r3, fp 8000ec4: 4223 tst r3, r4 8000ec6: d0f0 beq.n 8000eaa <__aeabi_ddiv+0x1ea> 8000ec8: 2480 movs r4, #128 @ 0x80 8000eca: 464b mov r3, r9 8000ecc: 0324 lsls r4, r4, #12 8000ece: 431c orrs r4, r3 8000ed0: 0324 lsls r4, r4, #12 8000ed2: 9e02 ldr r6, [sp, #8] 8000ed4: 4b01 ldr r3, [pc, #4] @ (8000edc <__aeabi_ddiv+0x21c>) 8000ed6: 0b24 lsrs r4, r4, #12 8000ed8: e75e b.n 8000d98 <__aeabi_ddiv+0xd8> 8000eda: 46c0 nop @ (mov r8, r8) 8000edc: 000007ff .word 0x000007ff 8000ee0: fffffc01 .word 0xfffffc01 8000ee4: 08005af0 .word 0x08005af0 8000ee8: fffff801 .word 0xfffff801 8000eec: 000003f3 .word 0x000003f3 8000ef0: fffffc0d .word 0xfffffc0d 8000ef4: 45cb cmp fp, r9 8000ef6: d200 bcs.n 8000efa <__aeabi_ddiv+0x23a> 8000ef8: e0f8 b.n 80010ec <__aeabi_ddiv+0x42c> 8000efa: d100 bne.n 8000efe <__aeabi_ddiv+0x23e> 8000efc: e0f3 b.n 80010e6 <__aeabi_ddiv+0x426> 8000efe: 2301 movs r3, #1 8000f00: 425b negs r3, r3 8000f02: 469c mov ip, r3 8000f04: 4644 mov r4, r8 8000f06: 4648 mov r0, r9 8000f08: 2500 movs r5, #0 8000f0a: 44e2 add sl, ip 8000f0c: 465b mov r3, fp 8000f0e: 0e17 lsrs r7, r2, #24 8000f10: 021b lsls r3, r3, #8 8000f12: 431f orrs r7, r3 8000f14: 0c19 lsrs r1, r3, #16 8000f16: 043b lsls r3, r7, #16 8000f18: 0212 lsls r2, r2, #8 8000f1a: 9700 str r7, [sp, #0] 8000f1c: 0c1f lsrs r7, r3, #16 8000f1e: 4691 mov r9, r2 8000f20: 9102 str r1, [sp, #8] 8000f22: 9703 str r7, [sp, #12] 8000f24: f7ff f974 bl 8000210 <__aeabi_uidivmod> 8000f28: 0002 movs r2, r0 8000f2a: 437a muls r2, r7 8000f2c: 040b lsls r3, r1, #16 8000f2e: 0c21 lsrs r1, r4, #16 8000f30: 4680 mov r8, r0 8000f32: 4319 orrs r1, r3 8000f34: 428a cmp r2, r1 8000f36: d909 bls.n 8000f4c <__aeabi_ddiv+0x28c> 8000f38: 9f00 ldr r7, [sp, #0] 8000f3a: 2301 movs r3, #1 8000f3c: 46bc mov ip, r7 8000f3e: 425b negs r3, r3 8000f40: 4461 add r1, ip 8000f42: 469c mov ip, r3 8000f44: 44e0 add r8, ip 8000f46: 428f cmp r7, r1 8000f48: d800 bhi.n 8000f4c <__aeabi_ddiv+0x28c> 8000f4a: e15c b.n 8001206 <__aeabi_ddiv+0x546> 8000f4c: 1a88 subs r0, r1, r2 8000f4e: 9902 ldr r1, [sp, #8] 8000f50: f7ff f95e bl 8000210 <__aeabi_uidivmod> 8000f54: 9a03 ldr r2, [sp, #12] 8000f56: 0424 lsls r4, r4, #16 8000f58: 4342 muls r2, r0 8000f5a: 0409 lsls r1, r1, #16 8000f5c: 0c24 lsrs r4, r4, #16 8000f5e: 0003 movs r3, r0 8000f60: 430c orrs r4, r1 8000f62: 42a2 cmp r2, r4 8000f64: d906 bls.n 8000f74 <__aeabi_ddiv+0x2b4> 8000f66: 9900 ldr r1, [sp, #0] 8000f68: 3b01 subs r3, #1 8000f6a: 468c mov ip, r1 8000f6c: 4464 add r4, ip 8000f6e: 42a1 cmp r1, r4 8000f70: d800 bhi.n 8000f74 <__aeabi_ddiv+0x2b4> 8000f72: e142 b.n 80011fa <__aeabi_ddiv+0x53a> 8000f74: 1aa0 subs r0, r4, r2 8000f76: 4642 mov r2, r8 8000f78: 0412 lsls r2, r2, #16 8000f7a: 431a orrs r2, r3 8000f7c: 4693 mov fp, r2 8000f7e: 464b mov r3, r9 8000f80: 4659 mov r1, fp 8000f82: 0c1b lsrs r3, r3, #16 8000f84: 001f movs r7, r3 8000f86: 9304 str r3, [sp, #16] 8000f88: 040b lsls r3, r1, #16 8000f8a: 4649 mov r1, r9 8000f8c: 0409 lsls r1, r1, #16 8000f8e: 0c09 lsrs r1, r1, #16 8000f90: 000c movs r4, r1 8000f92: 0c1b lsrs r3, r3, #16 8000f94: 435c muls r4, r3 8000f96: 0c12 lsrs r2, r2, #16 8000f98: 437b muls r3, r7 8000f9a: 4688 mov r8, r1 8000f9c: 4351 muls r1, r2 8000f9e: 437a muls r2, r7 8000fa0: 0c27 lsrs r7, r4, #16 8000fa2: 46bc mov ip, r7 8000fa4: 185b adds r3, r3, r1 8000fa6: 4463 add r3, ip 8000fa8: 4299 cmp r1, r3 8000faa: d903 bls.n 8000fb4 <__aeabi_ddiv+0x2f4> 8000fac: 2180 movs r1, #128 @ 0x80 8000fae: 0249 lsls r1, r1, #9 8000fb0: 468c mov ip, r1 8000fb2: 4462 add r2, ip 8000fb4: 0c19 lsrs r1, r3, #16 8000fb6: 0424 lsls r4, r4, #16 8000fb8: 041b lsls r3, r3, #16 8000fba: 0c24 lsrs r4, r4, #16 8000fbc: 188a adds r2, r1, r2 8000fbe: 191c adds r4, r3, r4 8000fc0: 4290 cmp r0, r2 8000fc2: d302 bcc.n 8000fca <__aeabi_ddiv+0x30a> 8000fc4: d116 bne.n 8000ff4 <__aeabi_ddiv+0x334> 8000fc6: 42a5 cmp r5, r4 8000fc8: d214 bcs.n 8000ff4 <__aeabi_ddiv+0x334> 8000fca: 465b mov r3, fp 8000fcc: 9f00 ldr r7, [sp, #0] 8000fce: 3b01 subs r3, #1 8000fd0: 444d add r5, r9 8000fd2: 9305 str r3, [sp, #20] 8000fd4: 454d cmp r5, r9 8000fd6: 419b sbcs r3, r3 8000fd8: 46bc mov ip, r7 8000fda: 425b negs r3, r3 8000fdc: 4463 add r3, ip 8000fde: 18c0 adds r0, r0, r3 8000fe0: 4287 cmp r7, r0 8000fe2: d300 bcc.n 8000fe6 <__aeabi_ddiv+0x326> 8000fe4: e102 b.n 80011ec <__aeabi_ddiv+0x52c> 8000fe6: 4282 cmp r2, r0 8000fe8: d900 bls.n 8000fec <__aeabi_ddiv+0x32c> 8000fea: e129 b.n 8001240 <__aeabi_ddiv+0x580> 8000fec: d100 bne.n 8000ff0 <__aeabi_ddiv+0x330> 8000fee: e124 b.n 800123a <__aeabi_ddiv+0x57a> 8000ff0: 9b05 ldr r3, [sp, #20] 8000ff2: 469b mov fp, r3 8000ff4: 1b2c subs r4, r5, r4 8000ff6: 42a5 cmp r5, r4 8000ff8: 41ad sbcs r5, r5 8000ffa: 9b00 ldr r3, [sp, #0] 8000ffc: 1a80 subs r0, r0, r2 8000ffe: 426d negs r5, r5 8001000: 1b40 subs r0, r0, r5 8001002: 4283 cmp r3, r0 8001004: d100 bne.n 8001008 <__aeabi_ddiv+0x348> 8001006: e10f b.n 8001228 <__aeabi_ddiv+0x568> 8001008: 9902 ldr r1, [sp, #8] 800100a: f7ff f901 bl 8000210 <__aeabi_uidivmod> 800100e: 9a03 ldr r2, [sp, #12] 8001010: 040b lsls r3, r1, #16 8001012: 4342 muls r2, r0 8001014: 0c21 lsrs r1, r4, #16 8001016: 0005 movs r5, r0 8001018: 4319 orrs r1, r3 800101a: 428a cmp r2, r1 800101c: d900 bls.n 8001020 <__aeabi_ddiv+0x360> 800101e: e0cb b.n 80011b8 <__aeabi_ddiv+0x4f8> 8001020: 1a88 subs r0, r1, r2 8001022: 9902 ldr r1, [sp, #8] 8001024: f7ff f8f4 bl 8000210 <__aeabi_uidivmod> 8001028: 9a03 ldr r2, [sp, #12] 800102a: 0424 lsls r4, r4, #16 800102c: 4342 muls r2, r0 800102e: 0409 lsls r1, r1, #16 8001030: 0c24 lsrs r4, r4, #16 8001032: 0003 movs r3, r0 8001034: 430c orrs r4, r1 8001036: 42a2 cmp r2, r4 8001038: d900 bls.n 800103c <__aeabi_ddiv+0x37c> 800103a: e0ca b.n 80011d2 <__aeabi_ddiv+0x512> 800103c: 4641 mov r1, r8 800103e: 1aa4 subs r4, r4, r2 8001040: 042a lsls r2, r5, #16 8001042: 431a orrs r2, r3 8001044: 9f04 ldr r7, [sp, #16] 8001046: 0413 lsls r3, r2, #16 8001048: 0c1b lsrs r3, r3, #16 800104a: 4359 muls r1, r3 800104c: 4640 mov r0, r8 800104e: 437b muls r3, r7 8001050: 469c mov ip, r3 8001052: 0c15 lsrs r5, r2, #16 8001054: 4368 muls r0, r5 8001056: 0c0b lsrs r3, r1, #16 8001058: 4484 add ip, r0 800105a: 4463 add r3, ip 800105c: 437d muls r5, r7 800105e: 4298 cmp r0, r3 8001060: d903 bls.n 800106a <__aeabi_ddiv+0x3aa> 8001062: 2080 movs r0, #128 @ 0x80 8001064: 0240 lsls r0, r0, #9 8001066: 4684 mov ip, r0 8001068: 4465 add r5, ip 800106a: 0c18 lsrs r0, r3, #16 800106c: 0409 lsls r1, r1, #16 800106e: 041b lsls r3, r3, #16 8001070: 0c09 lsrs r1, r1, #16 8001072: 1940 adds r0, r0, r5 8001074: 185b adds r3, r3, r1 8001076: 4284 cmp r4, r0 8001078: d327 bcc.n 80010ca <__aeabi_ddiv+0x40a> 800107a: d023 beq.n 80010c4 <__aeabi_ddiv+0x404> 800107c: 2301 movs r3, #1 800107e: 0035 movs r5, r6 8001080: 431a orrs r2, r3 8001082: 4b94 ldr r3, [pc, #592] @ (80012d4 <__aeabi_ddiv+0x614>) 8001084: 4453 add r3, sl 8001086: 2b00 cmp r3, #0 8001088: dd60 ble.n 800114c <__aeabi_ddiv+0x48c> 800108a: 0751 lsls r1, r2, #29 800108c: d000 beq.n 8001090 <__aeabi_ddiv+0x3d0> 800108e: e086 b.n 800119e <__aeabi_ddiv+0x4de> 8001090: 002e movs r6, r5 8001092: 08d1 lsrs r1, r2, #3 8001094: 465a mov r2, fp 8001096: 01d2 lsls r2, r2, #7 8001098: d506 bpl.n 80010a8 <__aeabi_ddiv+0x3e8> 800109a: 465a mov r2, fp 800109c: 4b8e ldr r3, [pc, #568] @ (80012d8 <__aeabi_ddiv+0x618>) 800109e: 401a ands r2, r3 80010a0: 2380 movs r3, #128 @ 0x80 80010a2: 4693 mov fp, r2 80010a4: 00db lsls r3, r3, #3 80010a6: 4453 add r3, sl 80010a8: 4a8c ldr r2, [pc, #560] @ (80012dc <__aeabi_ddiv+0x61c>) 80010aa: 4293 cmp r3, r2 80010ac: dd00 ble.n 80010b0 <__aeabi_ddiv+0x3f0> 80010ae: e680 b.n 8000db2 <__aeabi_ddiv+0xf2> 80010b0: 465a mov r2, fp 80010b2: 0752 lsls r2, r2, #29 80010b4: 430a orrs r2, r1 80010b6: 4690 mov r8, r2 80010b8: 465a mov r2, fp 80010ba: 055b lsls r3, r3, #21 80010bc: 0254 lsls r4, r2, #9 80010be: 0b24 lsrs r4, r4, #12 80010c0: 0d5b lsrs r3, r3, #21 80010c2: e669 b.n 8000d98 <__aeabi_ddiv+0xd8> 80010c4: 0035 movs r5, r6 80010c6: 2b00 cmp r3, #0 80010c8: d0db beq.n 8001082 <__aeabi_ddiv+0x3c2> 80010ca: 9d00 ldr r5, [sp, #0] 80010cc: 1e51 subs r1, r2, #1 80010ce: 46ac mov ip, r5 80010d0: 4464 add r4, ip 80010d2: 42ac cmp r4, r5 80010d4: d200 bcs.n 80010d8 <__aeabi_ddiv+0x418> 80010d6: e09e b.n 8001216 <__aeabi_ddiv+0x556> 80010d8: 4284 cmp r4, r0 80010da: d200 bcs.n 80010de <__aeabi_ddiv+0x41e> 80010dc: e0e1 b.n 80012a2 <__aeabi_ddiv+0x5e2> 80010de: d100 bne.n 80010e2 <__aeabi_ddiv+0x422> 80010e0: e0ee b.n 80012c0 <__aeabi_ddiv+0x600> 80010e2: 000a movs r2, r1 80010e4: e7ca b.n 800107c <__aeabi_ddiv+0x3bc> 80010e6: 4542 cmp r2, r8 80010e8: d900 bls.n 80010ec <__aeabi_ddiv+0x42c> 80010ea: e708 b.n 8000efe <__aeabi_ddiv+0x23e> 80010ec: 464b mov r3, r9 80010ee: 07dc lsls r4, r3, #31 80010f0: 0858 lsrs r0, r3, #1 80010f2: 4643 mov r3, r8 80010f4: 085b lsrs r3, r3, #1 80010f6: 431c orrs r4, r3 80010f8: 4643 mov r3, r8 80010fa: 07dd lsls r5, r3, #31 80010fc: e706 b.n 8000f0c <__aeabi_ddiv+0x24c> 80010fe: f001 fa3d bl 800257c <__clzsi2> 8001102: 2315 movs r3, #21 8001104: 469c mov ip, r3 8001106: 4484 add ip, r0 8001108: 0002 movs r2, r0 800110a: 4663 mov r3, ip 800110c: 3220 adds r2, #32 800110e: 2b1c cmp r3, #28 8001110: dc00 bgt.n 8001114 <__aeabi_ddiv+0x454> 8001112: e692 b.n 8000e3a <__aeabi_ddiv+0x17a> 8001114: 0023 movs r3, r4 8001116: 3808 subs r0, #8 8001118: 4083 lsls r3, r0 800111a: 4699 mov r9, r3 800111c: 2300 movs r3, #0 800111e: 4698 mov r8, r3 8001120: e69a b.n 8000e58 <__aeabi_ddiv+0x198> 8001122: f001 fa2b bl 800257c <__clzsi2> 8001126: 0002 movs r2, r0 8001128: 0003 movs r3, r0 800112a: 3215 adds r2, #21 800112c: 3320 adds r3, #32 800112e: 2a1c cmp r2, #28 8001130: dc00 bgt.n 8001134 <__aeabi_ddiv+0x474> 8001132: e65f b.n 8000df4 <__aeabi_ddiv+0x134> 8001134: 9900 ldr r1, [sp, #0] 8001136: 3808 subs r0, #8 8001138: 4081 lsls r1, r0 800113a: 2200 movs r2, #0 800113c: 468b mov fp, r1 800113e: e666 b.n 8000e0e <__aeabi_ddiv+0x14e> 8001140: 2200 movs r2, #0 8001142: 002e movs r6, r5 8001144: 2400 movs r4, #0 8001146: 4690 mov r8, r2 8001148: 4b65 ldr r3, [pc, #404] @ (80012e0 <__aeabi_ddiv+0x620>) 800114a: e625 b.n 8000d98 <__aeabi_ddiv+0xd8> 800114c: 002e movs r6, r5 800114e: 2101 movs r1, #1 8001150: 1ac9 subs r1, r1, r3 8001152: 2938 cmp r1, #56 @ 0x38 8001154: dd00 ble.n 8001158 <__aeabi_ddiv+0x498> 8001156: e61b b.n 8000d90 <__aeabi_ddiv+0xd0> 8001158: 291f cmp r1, #31 800115a: dc7e bgt.n 800125a <__aeabi_ddiv+0x59a> 800115c: 4861 ldr r0, [pc, #388] @ (80012e4 <__aeabi_ddiv+0x624>) 800115e: 0014 movs r4, r2 8001160: 4450 add r0, sl 8001162: 465b mov r3, fp 8001164: 4082 lsls r2, r0 8001166: 4083 lsls r3, r0 8001168: 40cc lsrs r4, r1 800116a: 1e50 subs r0, r2, #1 800116c: 4182 sbcs r2, r0 800116e: 4323 orrs r3, r4 8001170: 431a orrs r2, r3 8001172: 465b mov r3, fp 8001174: 40cb lsrs r3, r1 8001176: 0751 lsls r1, r2, #29 8001178: d009 beq.n 800118e <__aeabi_ddiv+0x4ce> 800117a: 210f movs r1, #15 800117c: 4011 ands r1, r2 800117e: 2904 cmp r1, #4 8001180: d005 beq.n 800118e <__aeabi_ddiv+0x4ce> 8001182: 1d11 adds r1, r2, #4 8001184: 4291 cmp r1, r2 8001186: 4192 sbcs r2, r2 8001188: 4252 negs r2, r2 800118a: 189b adds r3, r3, r2 800118c: 000a movs r2, r1 800118e: 0219 lsls r1, r3, #8 8001190: d400 bmi.n 8001194 <__aeabi_ddiv+0x4d4> 8001192: e09b b.n 80012cc <__aeabi_ddiv+0x60c> 8001194: 2200 movs r2, #0 8001196: 2301 movs r3, #1 8001198: 2400 movs r4, #0 800119a: 4690 mov r8, r2 800119c: e5fc b.n 8000d98 <__aeabi_ddiv+0xd8> 800119e: 210f movs r1, #15 80011a0: 4011 ands r1, r2 80011a2: 2904 cmp r1, #4 80011a4: d100 bne.n 80011a8 <__aeabi_ddiv+0x4e8> 80011a6: e773 b.n 8001090 <__aeabi_ddiv+0x3d0> 80011a8: 1d11 adds r1, r2, #4 80011aa: 4291 cmp r1, r2 80011ac: 4192 sbcs r2, r2 80011ae: 4252 negs r2, r2 80011b0: 002e movs r6, r5 80011b2: 08c9 lsrs r1, r1, #3 80011b4: 4493 add fp, r2 80011b6: e76d b.n 8001094 <__aeabi_ddiv+0x3d4> 80011b8: 9b00 ldr r3, [sp, #0] 80011ba: 3d01 subs r5, #1 80011bc: 469c mov ip, r3 80011be: 4461 add r1, ip 80011c0: 428b cmp r3, r1 80011c2: d900 bls.n 80011c6 <__aeabi_ddiv+0x506> 80011c4: e72c b.n 8001020 <__aeabi_ddiv+0x360> 80011c6: 428a cmp r2, r1 80011c8: d800 bhi.n 80011cc <__aeabi_ddiv+0x50c> 80011ca: e729 b.n 8001020 <__aeabi_ddiv+0x360> 80011cc: 1e85 subs r5, r0, #2 80011ce: 4461 add r1, ip 80011d0: e726 b.n 8001020 <__aeabi_ddiv+0x360> 80011d2: 9900 ldr r1, [sp, #0] 80011d4: 3b01 subs r3, #1 80011d6: 468c mov ip, r1 80011d8: 4464 add r4, ip 80011da: 42a1 cmp r1, r4 80011dc: d900 bls.n 80011e0 <__aeabi_ddiv+0x520> 80011de: e72d b.n 800103c <__aeabi_ddiv+0x37c> 80011e0: 42a2 cmp r2, r4 80011e2: d800 bhi.n 80011e6 <__aeabi_ddiv+0x526> 80011e4: e72a b.n 800103c <__aeabi_ddiv+0x37c> 80011e6: 1e83 subs r3, r0, #2 80011e8: 4464 add r4, ip 80011ea: e727 b.n 800103c <__aeabi_ddiv+0x37c> 80011ec: 4287 cmp r7, r0 80011ee: d000 beq.n 80011f2 <__aeabi_ddiv+0x532> 80011f0: e6fe b.n 8000ff0 <__aeabi_ddiv+0x330> 80011f2: 45a9 cmp r9, r5 80011f4: d900 bls.n 80011f8 <__aeabi_ddiv+0x538> 80011f6: e6fb b.n 8000ff0 <__aeabi_ddiv+0x330> 80011f8: e6f5 b.n 8000fe6 <__aeabi_ddiv+0x326> 80011fa: 42a2 cmp r2, r4 80011fc: d800 bhi.n 8001200 <__aeabi_ddiv+0x540> 80011fe: e6b9 b.n 8000f74 <__aeabi_ddiv+0x2b4> 8001200: 1e83 subs r3, r0, #2 8001202: 4464 add r4, ip 8001204: e6b6 b.n 8000f74 <__aeabi_ddiv+0x2b4> 8001206: 428a cmp r2, r1 8001208: d800 bhi.n 800120c <__aeabi_ddiv+0x54c> 800120a: e69f b.n 8000f4c <__aeabi_ddiv+0x28c> 800120c: 46bc mov ip, r7 800120e: 1e83 subs r3, r0, #2 8001210: 4698 mov r8, r3 8001212: 4461 add r1, ip 8001214: e69a b.n 8000f4c <__aeabi_ddiv+0x28c> 8001216: 000a movs r2, r1 8001218: 4284 cmp r4, r0 800121a: d000 beq.n 800121e <__aeabi_ddiv+0x55e> 800121c: e72e b.n 800107c <__aeabi_ddiv+0x3bc> 800121e: 454b cmp r3, r9 8001220: d000 beq.n 8001224 <__aeabi_ddiv+0x564> 8001222: e72b b.n 800107c <__aeabi_ddiv+0x3bc> 8001224: 0035 movs r5, r6 8001226: e72c b.n 8001082 <__aeabi_ddiv+0x3c2> 8001228: 4b2a ldr r3, [pc, #168] @ (80012d4 <__aeabi_ddiv+0x614>) 800122a: 4a2f ldr r2, [pc, #188] @ (80012e8 <__aeabi_ddiv+0x628>) 800122c: 4453 add r3, sl 800122e: 4592 cmp sl, r2 8001230: db43 blt.n 80012ba <__aeabi_ddiv+0x5fa> 8001232: 2201 movs r2, #1 8001234: 2100 movs r1, #0 8001236: 4493 add fp, r2 8001238: e72c b.n 8001094 <__aeabi_ddiv+0x3d4> 800123a: 42ac cmp r4, r5 800123c: d800 bhi.n 8001240 <__aeabi_ddiv+0x580> 800123e: e6d7 b.n 8000ff0 <__aeabi_ddiv+0x330> 8001240: 2302 movs r3, #2 8001242: 425b negs r3, r3 8001244: 469c mov ip, r3 8001246: 9900 ldr r1, [sp, #0] 8001248: 444d add r5, r9 800124a: 454d cmp r5, r9 800124c: 419b sbcs r3, r3 800124e: 44e3 add fp, ip 8001250: 468c mov ip, r1 8001252: 425b negs r3, r3 8001254: 4463 add r3, ip 8001256: 18c0 adds r0, r0, r3 8001258: e6cc b.n 8000ff4 <__aeabi_ddiv+0x334> 800125a: 201f movs r0, #31 800125c: 4240 negs r0, r0 800125e: 1ac3 subs r3, r0, r3 8001260: 4658 mov r0, fp 8001262: 40d8 lsrs r0, r3 8001264: 2920 cmp r1, #32 8001266: d004 beq.n 8001272 <__aeabi_ddiv+0x5b2> 8001268: 4659 mov r1, fp 800126a: 4b20 ldr r3, [pc, #128] @ (80012ec <__aeabi_ddiv+0x62c>) 800126c: 4453 add r3, sl 800126e: 4099 lsls r1, r3 8001270: 430a orrs r2, r1 8001272: 1e53 subs r3, r2, #1 8001274: 419a sbcs r2, r3 8001276: 2307 movs r3, #7 8001278: 0019 movs r1, r3 800127a: 4302 orrs r2, r0 800127c: 2400 movs r4, #0 800127e: 4011 ands r1, r2 8001280: 4213 tst r3, r2 8001282: d009 beq.n 8001298 <__aeabi_ddiv+0x5d8> 8001284: 3308 adds r3, #8 8001286: 4013 ands r3, r2 8001288: 2b04 cmp r3, #4 800128a: d01d beq.n 80012c8 <__aeabi_ddiv+0x608> 800128c: 1d13 adds r3, r2, #4 800128e: 4293 cmp r3, r2 8001290: 4189 sbcs r1, r1 8001292: 001a movs r2, r3 8001294: 4249 negs r1, r1 8001296: 0749 lsls r1, r1, #29 8001298: 08d2 lsrs r2, r2, #3 800129a: 430a orrs r2, r1 800129c: 4690 mov r8, r2 800129e: 2300 movs r3, #0 80012a0: e57a b.n 8000d98 <__aeabi_ddiv+0xd8> 80012a2: 4649 mov r1, r9 80012a4: 9f00 ldr r7, [sp, #0] 80012a6: 004d lsls r5, r1, #1 80012a8: 454d cmp r5, r9 80012aa: 4189 sbcs r1, r1 80012ac: 46bc mov ip, r7 80012ae: 4249 negs r1, r1 80012b0: 4461 add r1, ip 80012b2: 46a9 mov r9, r5 80012b4: 3a02 subs r2, #2 80012b6: 1864 adds r4, r4, r1 80012b8: e7ae b.n 8001218 <__aeabi_ddiv+0x558> 80012ba: 2201 movs r2, #1 80012bc: 4252 negs r2, r2 80012be: e746 b.n 800114e <__aeabi_ddiv+0x48e> 80012c0: 4599 cmp r9, r3 80012c2: d3ee bcc.n 80012a2 <__aeabi_ddiv+0x5e2> 80012c4: 000a movs r2, r1 80012c6: e7aa b.n 800121e <__aeabi_ddiv+0x55e> 80012c8: 2100 movs r1, #0 80012ca: e7e5 b.n 8001298 <__aeabi_ddiv+0x5d8> 80012cc: 0759 lsls r1, r3, #29 80012ce: 025b lsls r3, r3, #9 80012d0: 0b1c lsrs r4, r3, #12 80012d2: e7e1 b.n 8001298 <__aeabi_ddiv+0x5d8> 80012d4: 000003ff .word 0x000003ff 80012d8: feffffff .word 0xfeffffff 80012dc: 000007fe .word 0x000007fe 80012e0: 000007ff .word 0x000007ff 80012e4: 0000041e .word 0x0000041e 80012e8: fffffc02 .word 0xfffffc02 80012ec: 0000043e .word 0x0000043e 080012f0 <__eqdf2>: 80012f0: b5f0 push {r4, r5, r6, r7, lr} 80012f2: 4657 mov r7, sl 80012f4: 46de mov lr, fp 80012f6: 464e mov r6, r9 80012f8: 4645 mov r5, r8 80012fa: b5e0 push {r5, r6, r7, lr} 80012fc: 000d movs r5, r1 80012fe: 0004 movs r4, r0 8001300: 0fe8 lsrs r0, r5, #31 8001302: 4683 mov fp, r0 8001304: 0309 lsls r1, r1, #12 8001306: 0fd8 lsrs r0, r3, #31 8001308: 0b09 lsrs r1, r1, #12 800130a: 4682 mov sl, r0 800130c: 4819 ldr r0, [pc, #100] @ (8001374 <__eqdf2+0x84>) 800130e: 468c mov ip, r1 8001310: 031f lsls r7, r3, #12 8001312: 0069 lsls r1, r5, #1 8001314: 005e lsls r6, r3, #1 8001316: 0d49 lsrs r1, r1, #21 8001318: 0b3f lsrs r7, r7, #12 800131a: 0d76 lsrs r6, r6, #21 800131c: 4281 cmp r1, r0 800131e: d018 beq.n 8001352 <__eqdf2+0x62> 8001320: 4286 cmp r6, r0 8001322: d00f beq.n 8001344 <__eqdf2+0x54> 8001324: 2001 movs r0, #1 8001326: 42b1 cmp r1, r6 8001328: d10d bne.n 8001346 <__eqdf2+0x56> 800132a: 45bc cmp ip, r7 800132c: d10b bne.n 8001346 <__eqdf2+0x56> 800132e: 4294 cmp r4, r2 8001330: d109 bne.n 8001346 <__eqdf2+0x56> 8001332: 45d3 cmp fp, sl 8001334: d01c beq.n 8001370 <__eqdf2+0x80> 8001336: 2900 cmp r1, #0 8001338: d105 bne.n 8001346 <__eqdf2+0x56> 800133a: 4660 mov r0, ip 800133c: 4320 orrs r0, r4 800133e: 1e43 subs r3, r0, #1 8001340: 4198 sbcs r0, r3 8001342: e000 b.n 8001346 <__eqdf2+0x56> 8001344: 2001 movs r0, #1 8001346: bcf0 pop {r4, r5, r6, r7} 8001348: 46bb mov fp, r7 800134a: 46b2 mov sl, r6 800134c: 46a9 mov r9, r5 800134e: 46a0 mov r8, r4 8001350: bdf0 pop {r4, r5, r6, r7, pc} 8001352: 2001 movs r0, #1 8001354: 428e cmp r6, r1 8001356: d1f6 bne.n 8001346 <__eqdf2+0x56> 8001358: 4661 mov r1, ip 800135a: 4339 orrs r1, r7 800135c: 000f movs r7, r1 800135e: 4317 orrs r7, r2 8001360: 4327 orrs r7, r4 8001362: d1f0 bne.n 8001346 <__eqdf2+0x56> 8001364: 465b mov r3, fp 8001366: 4652 mov r2, sl 8001368: 1a98 subs r0, r3, r2 800136a: 1e43 subs r3, r0, #1 800136c: 4198 sbcs r0, r3 800136e: e7ea b.n 8001346 <__eqdf2+0x56> 8001370: 2000 movs r0, #0 8001372: e7e8 b.n 8001346 <__eqdf2+0x56> 8001374: 000007ff .word 0x000007ff 08001378 <__gedf2>: 8001378: b5f0 push {r4, r5, r6, r7, lr} 800137a: 4657 mov r7, sl 800137c: 464e mov r6, r9 800137e: 4645 mov r5, r8 8001380: 46de mov lr, fp 8001382: b5e0 push {r5, r6, r7, lr} 8001384: 000d movs r5, r1 8001386: 030e lsls r6, r1, #12 8001388: 0049 lsls r1, r1, #1 800138a: 0d49 lsrs r1, r1, #21 800138c: 468a mov sl, r1 800138e: 0fdf lsrs r7, r3, #31 8001390: 0fe9 lsrs r1, r5, #31 8001392: 46bc mov ip, r7 8001394: b083 sub sp, #12 8001396: 4f2f ldr r7, [pc, #188] @ (8001454 <__gedf2+0xdc>) 8001398: 0004 movs r4, r0 800139a: 4680 mov r8, r0 800139c: 9101 str r1, [sp, #4] 800139e: 0058 lsls r0, r3, #1 80013a0: 0319 lsls r1, r3, #12 80013a2: 4691 mov r9, r2 80013a4: 0b36 lsrs r6, r6, #12 80013a6: 0b09 lsrs r1, r1, #12 80013a8: 0d40 lsrs r0, r0, #21 80013aa: 45ba cmp sl, r7 80013ac: d01d beq.n 80013ea <__gedf2+0x72> 80013ae: 42b8 cmp r0, r7 80013b0: d00d beq.n 80013ce <__gedf2+0x56> 80013b2: 4657 mov r7, sl 80013b4: 2f00 cmp r7, #0 80013b6: d12a bne.n 800140e <__gedf2+0x96> 80013b8: 4334 orrs r4, r6 80013ba: 2800 cmp r0, #0 80013bc: d124 bne.n 8001408 <__gedf2+0x90> 80013be: 430a orrs r2, r1 80013c0: d036 beq.n 8001430 <__gedf2+0xb8> 80013c2: 2c00 cmp r4, #0 80013c4: d141 bne.n 800144a <__gedf2+0xd2> 80013c6: 4663 mov r3, ip 80013c8: 0058 lsls r0, r3, #1 80013ca: 3801 subs r0, #1 80013cc: e015 b.n 80013fa <__gedf2+0x82> 80013ce: 4311 orrs r1, r2 80013d0: d138 bne.n 8001444 <__gedf2+0xcc> 80013d2: 4653 mov r3, sl 80013d4: 2b00 cmp r3, #0 80013d6: d101 bne.n 80013dc <__gedf2+0x64> 80013d8: 4326 orrs r6, r4 80013da: d0f4 beq.n 80013c6 <__gedf2+0x4e> 80013dc: 9b01 ldr r3, [sp, #4] 80013de: 4563 cmp r3, ip 80013e0: d107 bne.n 80013f2 <__gedf2+0x7a> 80013e2: 9b01 ldr r3, [sp, #4] 80013e4: 0058 lsls r0, r3, #1 80013e6: 3801 subs r0, #1 80013e8: e007 b.n 80013fa <__gedf2+0x82> 80013ea: 4326 orrs r6, r4 80013ec: d12a bne.n 8001444 <__gedf2+0xcc> 80013ee: 4550 cmp r0, sl 80013f0: d021 beq.n 8001436 <__gedf2+0xbe> 80013f2: 2001 movs r0, #1 80013f4: 9b01 ldr r3, [sp, #4] 80013f6: 425f negs r7, r3 80013f8: 4338 orrs r0, r7 80013fa: b003 add sp, #12 80013fc: bcf0 pop {r4, r5, r6, r7} 80013fe: 46bb mov fp, r7 8001400: 46b2 mov sl, r6 8001402: 46a9 mov r9, r5 8001404: 46a0 mov r8, r4 8001406: bdf0 pop {r4, r5, r6, r7, pc} 8001408: 2c00 cmp r4, #0 800140a: d0dc beq.n 80013c6 <__gedf2+0x4e> 800140c: e7e6 b.n 80013dc <__gedf2+0x64> 800140e: 2800 cmp r0, #0 8001410: d0ef beq.n 80013f2 <__gedf2+0x7a> 8001412: 9b01 ldr r3, [sp, #4] 8001414: 4563 cmp r3, ip 8001416: d1ec bne.n 80013f2 <__gedf2+0x7a> 8001418: 4582 cmp sl, r0 800141a: dcea bgt.n 80013f2 <__gedf2+0x7a> 800141c: dbe1 blt.n 80013e2 <__gedf2+0x6a> 800141e: 428e cmp r6, r1 8001420: d8e7 bhi.n 80013f2 <__gedf2+0x7a> 8001422: d1de bne.n 80013e2 <__gedf2+0x6a> 8001424: 45c8 cmp r8, r9 8001426: d8e4 bhi.n 80013f2 <__gedf2+0x7a> 8001428: 2000 movs r0, #0 800142a: 45c8 cmp r8, r9 800142c: d2e5 bcs.n 80013fa <__gedf2+0x82> 800142e: e7d8 b.n 80013e2 <__gedf2+0x6a> 8001430: 2c00 cmp r4, #0 8001432: d0e2 beq.n 80013fa <__gedf2+0x82> 8001434: e7dd b.n 80013f2 <__gedf2+0x7a> 8001436: 4311 orrs r1, r2 8001438: d104 bne.n 8001444 <__gedf2+0xcc> 800143a: 9b01 ldr r3, [sp, #4] 800143c: 4563 cmp r3, ip 800143e: d1d8 bne.n 80013f2 <__gedf2+0x7a> 8001440: 2000 movs r0, #0 8001442: e7da b.n 80013fa <__gedf2+0x82> 8001444: 2002 movs r0, #2 8001446: 4240 negs r0, r0 8001448: e7d7 b.n 80013fa <__gedf2+0x82> 800144a: 9b01 ldr r3, [sp, #4] 800144c: 4563 cmp r3, ip 800144e: d0e6 beq.n 800141e <__gedf2+0xa6> 8001450: e7cf b.n 80013f2 <__gedf2+0x7a> 8001452: 46c0 nop @ (mov r8, r8) 8001454: 000007ff .word 0x000007ff 08001458 <__ledf2>: 8001458: b5f0 push {r4, r5, r6, r7, lr} 800145a: 4657 mov r7, sl 800145c: 464e mov r6, r9 800145e: 4645 mov r5, r8 8001460: 46de mov lr, fp 8001462: b5e0 push {r5, r6, r7, lr} 8001464: 000d movs r5, r1 8001466: 030e lsls r6, r1, #12 8001468: 0049 lsls r1, r1, #1 800146a: 0d49 lsrs r1, r1, #21 800146c: 468a mov sl, r1 800146e: 0fdf lsrs r7, r3, #31 8001470: 0fe9 lsrs r1, r5, #31 8001472: 46bc mov ip, r7 8001474: b083 sub sp, #12 8001476: 4f2e ldr r7, [pc, #184] @ (8001530 <__ledf2+0xd8>) 8001478: 0004 movs r4, r0 800147a: 4680 mov r8, r0 800147c: 9101 str r1, [sp, #4] 800147e: 0058 lsls r0, r3, #1 8001480: 0319 lsls r1, r3, #12 8001482: 4691 mov r9, r2 8001484: 0b36 lsrs r6, r6, #12 8001486: 0b09 lsrs r1, r1, #12 8001488: 0d40 lsrs r0, r0, #21 800148a: 45ba cmp sl, r7 800148c: d01e beq.n 80014cc <__ledf2+0x74> 800148e: 42b8 cmp r0, r7 8001490: d00d beq.n 80014ae <__ledf2+0x56> 8001492: 4657 mov r7, sl 8001494: 2f00 cmp r7, #0 8001496: d127 bne.n 80014e8 <__ledf2+0x90> 8001498: 4334 orrs r4, r6 800149a: 2800 cmp r0, #0 800149c: d133 bne.n 8001506 <__ledf2+0xae> 800149e: 430a orrs r2, r1 80014a0: d034 beq.n 800150c <__ledf2+0xb4> 80014a2: 2c00 cmp r4, #0 80014a4: d140 bne.n 8001528 <__ledf2+0xd0> 80014a6: 4663 mov r3, ip 80014a8: 0058 lsls r0, r3, #1 80014aa: 3801 subs r0, #1 80014ac: e015 b.n 80014da <__ledf2+0x82> 80014ae: 4311 orrs r1, r2 80014b0: d112 bne.n 80014d8 <__ledf2+0x80> 80014b2: 4653 mov r3, sl 80014b4: 2b00 cmp r3, #0 80014b6: d101 bne.n 80014bc <__ledf2+0x64> 80014b8: 4326 orrs r6, r4 80014ba: d0f4 beq.n 80014a6 <__ledf2+0x4e> 80014bc: 9b01 ldr r3, [sp, #4] 80014be: 4563 cmp r3, ip 80014c0: d01d beq.n 80014fe <__ledf2+0xa6> 80014c2: 2001 movs r0, #1 80014c4: 9b01 ldr r3, [sp, #4] 80014c6: 425f negs r7, r3 80014c8: 4338 orrs r0, r7 80014ca: e006 b.n 80014da <__ledf2+0x82> 80014cc: 4326 orrs r6, r4 80014ce: d103 bne.n 80014d8 <__ledf2+0x80> 80014d0: 4550 cmp r0, sl 80014d2: d1f6 bne.n 80014c2 <__ledf2+0x6a> 80014d4: 4311 orrs r1, r2 80014d6: d01c beq.n 8001512 <__ledf2+0xba> 80014d8: 2002 movs r0, #2 80014da: b003 add sp, #12 80014dc: bcf0 pop {r4, r5, r6, r7} 80014de: 46bb mov fp, r7 80014e0: 46b2 mov sl, r6 80014e2: 46a9 mov r9, r5 80014e4: 46a0 mov r8, r4 80014e6: bdf0 pop {r4, r5, r6, r7, pc} 80014e8: 2800 cmp r0, #0 80014ea: d0ea beq.n 80014c2 <__ledf2+0x6a> 80014ec: 9b01 ldr r3, [sp, #4] 80014ee: 4563 cmp r3, ip 80014f0: d1e7 bne.n 80014c2 <__ledf2+0x6a> 80014f2: 4582 cmp sl, r0 80014f4: dce5 bgt.n 80014c2 <__ledf2+0x6a> 80014f6: db02 blt.n 80014fe <__ledf2+0xa6> 80014f8: 428e cmp r6, r1 80014fa: d8e2 bhi.n 80014c2 <__ledf2+0x6a> 80014fc: d00e beq.n 800151c <__ledf2+0xc4> 80014fe: 9b01 ldr r3, [sp, #4] 8001500: 0058 lsls r0, r3, #1 8001502: 3801 subs r0, #1 8001504: e7e9 b.n 80014da <__ledf2+0x82> 8001506: 2c00 cmp r4, #0 8001508: d0cd beq.n 80014a6 <__ledf2+0x4e> 800150a: e7d7 b.n 80014bc <__ledf2+0x64> 800150c: 2c00 cmp r4, #0 800150e: d0e4 beq.n 80014da <__ledf2+0x82> 8001510: e7d7 b.n 80014c2 <__ledf2+0x6a> 8001512: 9b01 ldr r3, [sp, #4] 8001514: 2000 movs r0, #0 8001516: 4563 cmp r3, ip 8001518: d0df beq.n 80014da <__ledf2+0x82> 800151a: e7d2 b.n 80014c2 <__ledf2+0x6a> 800151c: 45c8 cmp r8, r9 800151e: d8d0 bhi.n 80014c2 <__ledf2+0x6a> 8001520: 2000 movs r0, #0 8001522: 45c8 cmp r8, r9 8001524: d2d9 bcs.n 80014da <__ledf2+0x82> 8001526: e7ea b.n 80014fe <__ledf2+0xa6> 8001528: 9b01 ldr r3, [sp, #4] 800152a: 4563 cmp r3, ip 800152c: d0e4 beq.n 80014f8 <__ledf2+0xa0> 800152e: e7c8 b.n 80014c2 <__ledf2+0x6a> 8001530: 000007ff .word 0x000007ff 08001534 <__aeabi_dmul>: 8001534: b5f0 push {r4, r5, r6, r7, lr} 8001536: 4657 mov r7, sl 8001538: 464e mov r6, r9 800153a: 46de mov lr, fp 800153c: 4645 mov r5, r8 800153e: b5e0 push {r5, r6, r7, lr} 8001540: 001f movs r7, r3 8001542: 030b lsls r3, r1, #12 8001544: 0b1b lsrs r3, r3, #12 8001546: 0016 movs r6, r2 8001548: 469a mov sl, r3 800154a: 0fca lsrs r2, r1, #31 800154c: 004b lsls r3, r1, #1 800154e: 0004 movs r4, r0 8001550: 4691 mov r9, r2 8001552: b085 sub sp, #20 8001554: 0d5b lsrs r3, r3, #21 8001556: d100 bne.n 800155a <__aeabi_dmul+0x26> 8001558: e1cf b.n 80018fa <__aeabi_dmul+0x3c6> 800155a: 4acd ldr r2, [pc, #820] @ (8001890 <__aeabi_dmul+0x35c>) 800155c: 4293 cmp r3, r2 800155e: d055 beq.n 800160c <__aeabi_dmul+0xd8> 8001560: 4651 mov r1, sl 8001562: 0f42 lsrs r2, r0, #29 8001564: 00c9 lsls r1, r1, #3 8001566: 430a orrs r2, r1 8001568: 2180 movs r1, #128 @ 0x80 800156a: 0409 lsls r1, r1, #16 800156c: 4311 orrs r1, r2 800156e: 00c2 lsls r2, r0, #3 8001570: 4690 mov r8, r2 8001572: 4ac8 ldr r2, [pc, #800] @ (8001894 <__aeabi_dmul+0x360>) 8001574: 468a mov sl, r1 8001576: 4693 mov fp, r2 8001578: 449b add fp, r3 800157a: 2300 movs r3, #0 800157c: 2500 movs r5, #0 800157e: 9302 str r3, [sp, #8] 8001580: 033c lsls r4, r7, #12 8001582: 007b lsls r3, r7, #1 8001584: 0ffa lsrs r2, r7, #31 8001586: 9601 str r6, [sp, #4] 8001588: 0b24 lsrs r4, r4, #12 800158a: 0d5b lsrs r3, r3, #21 800158c: 9200 str r2, [sp, #0] 800158e: d100 bne.n 8001592 <__aeabi_dmul+0x5e> 8001590: e188 b.n 80018a4 <__aeabi_dmul+0x370> 8001592: 4abf ldr r2, [pc, #764] @ (8001890 <__aeabi_dmul+0x35c>) 8001594: 4293 cmp r3, r2 8001596: d100 bne.n 800159a <__aeabi_dmul+0x66> 8001598: e092 b.n 80016c0 <__aeabi_dmul+0x18c> 800159a: 4abe ldr r2, [pc, #760] @ (8001894 <__aeabi_dmul+0x360>) 800159c: 4694 mov ip, r2 800159e: 4463 add r3, ip 80015a0: 449b add fp, r3 80015a2: 2d0a cmp r5, #10 80015a4: dc42 bgt.n 800162c <__aeabi_dmul+0xf8> 80015a6: 00e4 lsls r4, r4, #3 80015a8: 0f73 lsrs r3, r6, #29 80015aa: 4323 orrs r3, r4 80015ac: 2480 movs r4, #128 @ 0x80 80015ae: 4649 mov r1, r9 80015b0: 0424 lsls r4, r4, #16 80015b2: 431c orrs r4, r3 80015b4: 00f3 lsls r3, r6, #3 80015b6: 9301 str r3, [sp, #4] 80015b8: 9b00 ldr r3, [sp, #0] 80015ba: 2000 movs r0, #0 80015bc: 4059 eors r1, r3 80015be: b2cb uxtb r3, r1 80015c0: 9303 str r3, [sp, #12] 80015c2: 2d02 cmp r5, #2 80015c4: dc00 bgt.n 80015c8 <__aeabi_dmul+0x94> 80015c6: e094 b.n 80016f2 <__aeabi_dmul+0x1be> 80015c8: 2301 movs r3, #1 80015ca: 40ab lsls r3, r5 80015cc: 001d movs r5, r3 80015ce: 23a6 movs r3, #166 @ 0xa6 80015d0: 002a movs r2, r5 80015d2: 00db lsls r3, r3, #3 80015d4: 401a ands r2, r3 80015d6: 421d tst r5, r3 80015d8: d000 beq.n 80015dc <__aeabi_dmul+0xa8> 80015da: e229 b.n 8001a30 <__aeabi_dmul+0x4fc> 80015dc: 2390 movs r3, #144 @ 0x90 80015de: 009b lsls r3, r3, #2 80015e0: 421d tst r5, r3 80015e2: d100 bne.n 80015e6 <__aeabi_dmul+0xb2> 80015e4: e24d b.n 8001a82 <__aeabi_dmul+0x54e> 80015e6: 2300 movs r3, #0 80015e8: 2480 movs r4, #128 @ 0x80 80015ea: 4699 mov r9, r3 80015ec: 0324 lsls r4, r4, #12 80015ee: 4ba8 ldr r3, [pc, #672] @ (8001890 <__aeabi_dmul+0x35c>) 80015f0: 0010 movs r0, r2 80015f2: 464a mov r2, r9 80015f4: 051b lsls r3, r3, #20 80015f6: 4323 orrs r3, r4 80015f8: 07d2 lsls r2, r2, #31 80015fa: 4313 orrs r3, r2 80015fc: 0019 movs r1, r3 80015fe: b005 add sp, #20 8001600: bcf0 pop {r4, r5, r6, r7} 8001602: 46bb mov fp, r7 8001604: 46b2 mov sl, r6 8001606: 46a9 mov r9, r5 8001608: 46a0 mov r8, r4 800160a: bdf0 pop {r4, r5, r6, r7, pc} 800160c: 4652 mov r2, sl 800160e: 4302 orrs r2, r0 8001610: 4690 mov r8, r2 8001612: d000 beq.n 8001616 <__aeabi_dmul+0xe2> 8001614: e1ac b.n 8001970 <__aeabi_dmul+0x43c> 8001616: 469b mov fp, r3 8001618: 2302 movs r3, #2 800161a: 4692 mov sl, r2 800161c: 2508 movs r5, #8 800161e: 9302 str r3, [sp, #8] 8001620: e7ae b.n 8001580 <__aeabi_dmul+0x4c> 8001622: 9b00 ldr r3, [sp, #0] 8001624: 46a2 mov sl, r4 8001626: 4699 mov r9, r3 8001628: 9b01 ldr r3, [sp, #4] 800162a: 4698 mov r8, r3 800162c: 9b02 ldr r3, [sp, #8] 800162e: 2b02 cmp r3, #2 8001630: d100 bne.n 8001634 <__aeabi_dmul+0x100> 8001632: e1ca b.n 80019ca <__aeabi_dmul+0x496> 8001634: 2b03 cmp r3, #3 8001636: d100 bne.n 800163a <__aeabi_dmul+0x106> 8001638: e192 b.n 8001960 <__aeabi_dmul+0x42c> 800163a: 2b01 cmp r3, #1 800163c: d110 bne.n 8001660 <__aeabi_dmul+0x12c> 800163e: 2300 movs r3, #0 8001640: 2400 movs r4, #0 8001642: 2200 movs r2, #0 8001644: e7d4 b.n 80015f0 <__aeabi_dmul+0xbc> 8001646: 2201 movs r2, #1 8001648: 087b lsrs r3, r7, #1 800164a: 403a ands r2, r7 800164c: 4313 orrs r3, r2 800164e: 4652 mov r2, sl 8001650: 07d2 lsls r2, r2, #31 8001652: 4313 orrs r3, r2 8001654: 4698 mov r8, r3 8001656: 4653 mov r3, sl 8001658: 085b lsrs r3, r3, #1 800165a: 469a mov sl, r3 800165c: 9b03 ldr r3, [sp, #12] 800165e: 4699 mov r9, r3 8001660: 465b mov r3, fp 8001662: 1c58 adds r0, r3, #1 8001664: 2380 movs r3, #128 @ 0x80 8001666: 00db lsls r3, r3, #3 8001668: 445b add r3, fp 800166a: 2b00 cmp r3, #0 800166c: dc00 bgt.n 8001670 <__aeabi_dmul+0x13c> 800166e: e1b1 b.n 80019d4 <__aeabi_dmul+0x4a0> 8001670: 4642 mov r2, r8 8001672: 0752 lsls r2, r2, #29 8001674: d00b beq.n 800168e <__aeabi_dmul+0x15a> 8001676: 220f movs r2, #15 8001678: 4641 mov r1, r8 800167a: 400a ands r2, r1 800167c: 2a04 cmp r2, #4 800167e: d006 beq.n 800168e <__aeabi_dmul+0x15a> 8001680: 4642 mov r2, r8 8001682: 1d11 adds r1, r2, #4 8001684: 4541 cmp r1, r8 8001686: 4192 sbcs r2, r2 8001688: 4688 mov r8, r1 800168a: 4252 negs r2, r2 800168c: 4492 add sl, r2 800168e: 4652 mov r2, sl 8001690: 01d2 lsls r2, r2, #7 8001692: d506 bpl.n 80016a2 <__aeabi_dmul+0x16e> 8001694: 4652 mov r2, sl 8001696: 4b80 ldr r3, [pc, #512] @ (8001898 <__aeabi_dmul+0x364>) 8001698: 401a ands r2, r3 800169a: 2380 movs r3, #128 @ 0x80 800169c: 4692 mov sl, r2 800169e: 00db lsls r3, r3, #3 80016a0: 18c3 adds r3, r0, r3 80016a2: 4a7e ldr r2, [pc, #504] @ (800189c <__aeabi_dmul+0x368>) 80016a4: 4293 cmp r3, r2 80016a6: dd00 ble.n 80016aa <__aeabi_dmul+0x176> 80016a8: e18f b.n 80019ca <__aeabi_dmul+0x496> 80016aa: 4642 mov r2, r8 80016ac: 08d1 lsrs r1, r2, #3 80016ae: 4652 mov r2, sl 80016b0: 0752 lsls r2, r2, #29 80016b2: 430a orrs r2, r1 80016b4: 4651 mov r1, sl 80016b6: 055b lsls r3, r3, #21 80016b8: 024c lsls r4, r1, #9 80016ba: 0b24 lsrs r4, r4, #12 80016bc: 0d5b lsrs r3, r3, #21 80016be: e797 b.n 80015f0 <__aeabi_dmul+0xbc> 80016c0: 4b73 ldr r3, [pc, #460] @ (8001890 <__aeabi_dmul+0x35c>) 80016c2: 4326 orrs r6, r4 80016c4: 469c mov ip, r3 80016c6: 44e3 add fp, ip 80016c8: 2e00 cmp r6, #0 80016ca: d100 bne.n 80016ce <__aeabi_dmul+0x19a> 80016cc: e16f b.n 80019ae <__aeabi_dmul+0x47a> 80016ce: 2303 movs r3, #3 80016d0: 4649 mov r1, r9 80016d2: 431d orrs r5, r3 80016d4: 9b00 ldr r3, [sp, #0] 80016d6: 4059 eors r1, r3 80016d8: b2cb uxtb r3, r1 80016da: 9303 str r3, [sp, #12] 80016dc: 2d0a cmp r5, #10 80016de: dd00 ble.n 80016e2 <__aeabi_dmul+0x1ae> 80016e0: e133 b.n 800194a <__aeabi_dmul+0x416> 80016e2: 2301 movs r3, #1 80016e4: 40ab lsls r3, r5 80016e6: 001d movs r5, r3 80016e8: 2303 movs r3, #3 80016ea: 9302 str r3, [sp, #8] 80016ec: 2288 movs r2, #136 @ 0x88 80016ee: 422a tst r2, r5 80016f0: d197 bne.n 8001622 <__aeabi_dmul+0xee> 80016f2: 4642 mov r2, r8 80016f4: 4643 mov r3, r8 80016f6: 0412 lsls r2, r2, #16 80016f8: 0c12 lsrs r2, r2, #16 80016fa: 0016 movs r6, r2 80016fc: 9801 ldr r0, [sp, #4] 80016fe: 0c1d lsrs r5, r3, #16 8001700: 0c03 lsrs r3, r0, #16 8001702: 0400 lsls r0, r0, #16 8001704: 0c00 lsrs r0, r0, #16 8001706: 4346 muls r6, r0 8001708: 46b4 mov ip, r6 800170a: 001e movs r6, r3 800170c: 436e muls r6, r5 800170e: 9600 str r6, [sp, #0] 8001710: 0016 movs r6, r2 8001712: 0007 movs r7, r0 8001714: 435e muls r6, r3 8001716: 4661 mov r1, ip 8001718: 46b0 mov r8, r6 800171a: 436f muls r7, r5 800171c: 0c0e lsrs r6, r1, #16 800171e: 44b8 add r8, r7 8001720: 4446 add r6, r8 8001722: 42b7 cmp r7, r6 8001724: d905 bls.n 8001732 <__aeabi_dmul+0x1fe> 8001726: 2180 movs r1, #128 @ 0x80 8001728: 0249 lsls r1, r1, #9 800172a: 4688 mov r8, r1 800172c: 9f00 ldr r7, [sp, #0] 800172e: 4447 add r7, r8 8001730: 9700 str r7, [sp, #0] 8001732: 4661 mov r1, ip 8001734: 0409 lsls r1, r1, #16 8001736: 0c09 lsrs r1, r1, #16 8001738: 0c37 lsrs r7, r6, #16 800173a: 0436 lsls r6, r6, #16 800173c: 468c mov ip, r1 800173e: 0031 movs r1, r6 8001740: 4461 add r1, ip 8001742: 9101 str r1, [sp, #4] 8001744: 0011 movs r1, r2 8001746: 0c26 lsrs r6, r4, #16 8001748: 0424 lsls r4, r4, #16 800174a: 0c24 lsrs r4, r4, #16 800174c: 4361 muls r1, r4 800174e: 468c mov ip, r1 8001750: 0021 movs r1, r4 8001752: 4369 muls r1, r5 8001754: 4689 mov r9, r1 8001756: 4661 mov r1, ip 8001758: 0c09 lsrs r1, r1, #16 800175a: 4688 mov r8, r1 800175c: 4372 muls r2, r6 800175e: 444a add r2, r9 8001760: 4442 add r2, r8 8001762: 4375 muls r5, r6 8001764: 4591 cmp r9, r2 8001766: d903 bls.n 8001770 <__aeabi_dmul+0x23c> 8001768: 2180 movs r1, #128 @ 0x80 800176a: 0249 lsls r1, r1, #9 800176c: 4688 mov r8, r1 800176e: 4445 add r5, r8 8001770: 0c11 lsrs r1, r2, #16 8001772: 4688 mov r8, r1 8001774: 4661 mov r1, ip 8001776: 0409 lsls r1, r1, #16 8001778: 0c09 lsrs r1, r1, #16 800177a: 468c mov ip, r1 800177c: 0412 lsls r2, r2, #16 800177e: 4462 add r2, ip 8001780: 18b9 adds r1, r7, r2 8001782: 9102 str r1, [sp, #8] 8001784: 4651 mov r1, sl 8001786: 0c09 lsrs r1, r1, #16 8001788: 468c mov ip, r1 800178a: 4651 mov r1, sl 800178c: 040f lsls r7, r1, #16 800178e: 0c3f lsrs r7, r7, #16 8001790: 0039 movs r1, r7 8001792: 4341 muls r1, r0 8001794: 4445 add r5, r8 8001796: 4688 mov r8, r1 8001798: 4661 mov r1, ip 800179a: 4341 muls r1, r0 800179c: 468a mov sl, r1 800179e: 4641 mov r1, r8 80017a0: 4660 mov r0, ip 80017a2: 0c09 lsrs r1, r1, #16 80017a4: 4689 mov r9, r1 80017a6: 4358 muls r0, r3 80017a8: 437b muls r3, r7 80017aa: 4453 add r3, sl 80017ac: 444b add r3, r9 80017ae: 459a cmp sl, r3 80017b0: d903 bls.n 80017ba <__aeabi_dmul+0x286> 80017b2: 2180 movs r1, #128 @ 0x80 80017b4: 0249 lsls r1, r1, #9 80017b6: 4689 mov r9, r1 80017b8: 4448 add r0, r9 80017ba: 0c19 lsrs r1, r3, #16 80017bc: 4689 mov r9, r1 80017be: 4641 mov r1, r8 80017c0: 0409 lsls r1, r1, #16 80017c2: 0c09 lsrs r1, r1, #16 80017c4: 4688 mov r8, r1 80017c6: 0039 movs r1, r7 80017c8: 4361 muls r1, r4 80017ca: 041b lsls r3, r3, #16 80017cc: 4443 add r3, r8 80017ce: 4688 mov r8, r1 80017d0: 4661 mov r1, ip 80017d2: 434c muls r4, r1 80017d4: 4371 muls r1, r6 80017d6: 468c mov ip, r1 80017d8: 4641 mov r1, r8 80017da: 4377 muls r7, r6 80017dc: 0c0e lsrs r6, r1, #16 80017de: 193f adds r7, r7, r4 80017e0: 19f6 adds r6, r6, r7 80017e2: 4448 add r0, r9 80017e4: 42b4 cmp r4, r6 80017e6: d903 bls.n 80017f0 <__aeabi_dmul+0x2bc> 80017e8: 2180 movs r1, #128 @ 0x80 80017ea: 0249 lsls r1, r1, #9 80017ec: 4689 mov r9, r1 80017ee: 44cc add ip, r9 80017f0: 9902 ldr r1, [sp, #8] 80017f2: 9f00 ldr r7, [sp, #0] 80017f4: 4689 mov r9, r1 80017f6: 0431 lsls r1, r6, #16 80017f8: 444f add r7, r9 80017fa: 4689 mov r9, r1 80017fc: 4641 mov r1, r8 80017fe: 4297 cmp r7, r2 8001800: 4192 sbcs r2, r2 8001802: 040c lsls r4, r1, #16 8001804: 0c24 lsrs r4, r4, #16 8001806: 444c add r4, r9 8001808: 18ff adds r7, r7, r3 800180a: 4252 negs r2, r2 800180c: 1964 adds r4, r4, r5 800180e: 18a1 adds r1, r4, r2 8001810: 429f cmp r7, r3 8001812: 419b sbcs r3, r3 8001814: 4688 mov r8, r1 8001816: 4682 mov sl, r0 8001818: 425b negs r3, r3 800181a: 4699 mov r9, r3 800181c: 4590 cmp r8, r2 800181e: 4192 sbcs r2, r2 8001820: 42ac cmp r4, r5 8001822: 41a4 sbcs r4, r4 8001824: 44c2 add sl, r8 8001826: 44d1 add r9, sl 8001828: 4252 negs r2, r2 800182a: 4264 negs r4, r4 800182c: 4314 orrs r4, r2 800182e: 4599 cmp r9, r3 8001830: 419b sbcs r3, r3 8001832: 4582 cmp sl, r0 8001834: 4192 sbcs r2, r2 8001836: 425b negs r3, r3 8001838: 4252 negs r2, r2 800183a: 4313 orrs r3, r2 800183c: 464a mov r2, r9 800183e: 0c36 lsrs r6, r6, #16 8001840: 19a4 adds r4, r4, r6 8001842: 18e3 adds r3, r4, r3 8001844: 4463 add r3, ip 8001846: 025b lsls r3, r3, #9 8001848: 0dd2 lsrs r2, r2, #23 800184a: 431a orrs r2, r3 800184c: 9901 ldr r1, [sp, #4] 800184e: 4692 mov sl, r2 8001850: 027a lsls r2, r7, #9 8001852: 430a orrs r2, r1 8001854: 1e50 subs r0, r2, #1 8001856: 4182 sbcs r2, r0 8001858: 0dff lsrs r7, r7, #23 800185a: 4317 orrs r7, r2 800185c: 464a mov r2, r9 800185e: 0252 lsls r2, r2, #9 8001860: 4317 orrs r7, r2 8001862: 46b8 mov r8, r7 8001864: 01db lsls r3, r3, #7 8001866: d500 bpl.n 800186a <__aeabi_dmul+0x336> 8001868: e6ed b.n 8001646 <__aeabi_dmul+0x112> 800186a: 4b0d ldr r3, [pc, #52] @ (80018a0 <__aeabi_dmul+0x36c>) 800186c: 9a03 ldr r2, [sp, #12] 800186e: 445b add r3, fp 8001870: 4691 mov r9, r2 8001872: 2b00 cmp r3, #0 8001874: dc00 bgt.n 8001878 <__aeabi_dmul+0x344> 8001876: e0ac b.n 80019d2 <__aeabi_dmul+0x49e> 8001878: 003a movs r2, r7 800187a: 0752 lsls r2, r2, #29 800187c: d100 bne.n 8001880 <__aeabi_dmul+0x34c> 800187e: e710 b.n 80016a2 <__aeabi_dmul+0x16e> 8001880: 220f movs r2, #15 8001882: 4658 mov r0, fp 8001884: 403a ands r2, r7 8001886: 2a04 cmp r2, #4 8001888: d000 beq.n 800188c <__aeabi_dmul+0x358> 800188a: e6f9 b.n 8001680 <__aeabi_dmul+0x14c> 800188c: e709 b.n 80016a2 <__aeabi_dmul+0x16e> 800188e: 46c0 nop @ (mov r8, r8) 8001890: 000007ff .word 0x000007ff 8001894: fffffc01 .word 0xfffffc01 8001898: feffffff .word 0xfeffffff 800189c: 000007fe .word 0x000007fe 80018a0: 000003ff .word 0x000003ff 80018a4: 0022 movs r2, r4 80018a6: 4332 orrs r2, r6 80018a8: d06f beq.n 800198a <__aeabi_dmul+0x456> 80018aa: 2c00 cmp r4, #0 80018ac: d100 bne.n 80018b0 <__aeabi_dmul+0x37c> 80018ae: e0c2 b.n 8001a36 <__aeabi_dmul+0x502> 80018b0: 0020 movs r0, r4 80018b2: f000 fe63 bl 800257c <__clzsi2> 80018b6: 0002 movs r2, r0 80018b8: 0003 movs r3, r0 80018ba: 3a0b subs r2, #11 80018bc: 201d movs r0, #29 80018be: 1a82 subs r2, r0, r2 80018c0: 0030 movs r0, r6 80018c2: 0019 movs r1, r3 80018c4: 40d0 lsrs r0, r2 80018c6: 3908 subs r1, #8 80018c8: 408c lsls r4, r1 80018ca: 0002 movs r2, r0 80018cc: 4322 orrs r2, r4 80018ce: 0034 movs r4, r6 80018d0: 408c lsls r4, r1 80018d2: 4659 mov r1, fp 80018d4: 1acb subs r3, r1, r3 80018d6: 4986 ldr r1, [pc, #536] @ (8001af0 <__aeabi_dmul+0x5bc>) 80018d8: 468b mov fp, r1 80018da: 449b add fp, r3 80018dc: 2d0a cmp r5, #10 80018de: dd00 ble.n 80018e2 <__aeabi_dmul+0x3ae> 80018e0: e6a4 b.n 800162c <__aeabi_dmul+0xf8> 80018e2: 4649 mov r1, r9 80018e4: 9b00 ldr r3, [sp, #0] 80018e6: 9401 str r4, [sp, #4] 80018e8: 4059 eors r1, r3 80018ea: b2cb uxtb r3, r1 80018ec: 0014 movs r4, r2 80018ee: 2000 movs r0, #0 80018f0: 9303 str r3, [sp, #12] 80018f2: 2d02 cmp r5, #2 80018f4: dd00 ble.n 80018f8 <__aeabi_dmul+0x3c4> 80018f6: e667 b.n 80015c8 <__aeabi_dmul+0x94> 80018f8: e6fb b.n 80016f2 <__aeabi_dmul+0x1be> 80018fa: 4653 mov r3, sl 80018fc: 4303 orrs r3, r0 80018fe: 4698 mov r8, r3 8001900: d03c beq.n 800197c <__aeabi_dmul+0x448> 8001902: 4653 mov r3, sl 8001904: 2b00 cmp r3, #0 8001906: d100 bne.n 800190a <__aeabi_dmul+0x3d6> 8001908: e0a3 b.n 8001a52 <__aeabi_dmul+0x51e> 800190a: 4650 mov r0, sl 800190c: f000 fe36 bl 800257c <__clzsi2> 8001910: 230b movs r3, #11 8001912: 425b negs r3, r3 8001914: 469c mov ip, r3 8001916: 0002 movs r2, r0 8001918: 4484 add ip, r0 800191a: 0011 movs r1, r2 800191c: 4650 mov r0, sl 800191e: 3908 subs r1, #8 8001920: 4088 lsls r0, r1 8001922: 231d movs r3, #29 8001924: 4680 mov r8, r0 8001926: 4660 mov r0, ip 8001928: 1a1b subs r3, r3, r0 800192a: 0020 movs r0, r4 800192c: 40d8 lsrs r0, r3 800192e: 0003 movs r3, r0 8001930: 4640 mov r0, r8 8001932: 4303 orrs r3, r0 8001934: 469a mov sl, r3 8001936: 0023 movs r3, r4 8001938: 408b lsls r3, r1 800193a: 4698 mov r8, r3 800193c: 4b6c ldr r3, [pc, #432] @ (8001af0 <__aeabi_dmul+0x5bc>) 800193e: 2500 movs r5, #0 8001940: 1a9b subs r3, r3, r2 8001942: 469b mov fp, r3 8001944: 2300 movs r3, #0 8001946: 9302 str r3, [sp, #8] 8001948: e61a b.n 8001580 <__aeabi_dmul+0x4c> 800194a: 2d0f cmp r5, #15 800194c: d000 beq.n 8001950 <__aeabi_dmul+0x41c> 800194e: e0c9 b.n 8001ae4 <__aeabi_dmul+0x5b0> 8001950: 2380 movs r3, #128 @ 0x80 8001952: 4652 mov r2, sl 8001954: 031b lsls r3, r3, #12 8001956: 421a tst r2, r3 8001958: d002 beq.n 8001960 <__aeabi_dmul+0x42c> 800195a: 421c tst r4, r3 800195c: d100 bne.n 8001960 <__aeabi_dmul+0x42c> 800195e: e092 b.n 8001a86 <__aeabi_dmul+0x552> 8001960: 2480 movs r4, #128 @ 0x80 8001962: 4653 mov r3, sl 8001964: 0324 lsls r4, r4, #12 8001966: 431c orrs r4, r3 8001968: 0324 lsls r4, r4, #12 800196a: 4642 mov r2, r8 800196c: 0b24 lsrs r4, r4, #12 800196e: e63e b.n 80015ee <__aeabi_dmul+0xba> 8001970: 469b mov fp, r3 8001972: 2303 movs r3, #3 8001974: 4680 mov r8, r0 8001976: 250c movs r5, #12 8001978: 9302 str r3, [sp, #8] 800197a: e601 b.n 8001580 <__aeabi_dmul+0x4c> 800197c: 2300 movs r3, #0 800197e: 469a mov sl, r3 8001980: 469b mov fp, r3 8001982: 3301 adds r3, #1 8001984: 2504 movs r5, #4 8001986: 9302 str r3, [sp, #8] 8001988: e5fa b.n 8001580 <__aeabi_dmul+0x4c> 800198a: 2101 movs r1, #1 800198c: 430d orrs r5, r1 800198e: 2d0a cmp r5, #10 8001990: dd00 ble.n 8001994 <__aeabi_dmul+0x460> 8001992: e64b b.n 800162c <__aeabi_dmul+0xf8> 8001994: 4649 mov r1, r9 8001996: 9800 ldr r0, [sp, #0] 8001998: 4041 eors r1, r0 800199a: b2c9 uxtb r1, r1 800199c: 9103 str r1, [sp, #12] 800199e: 2d02 cmp r5, #2 80019a0: dc00 bgt.n 80019a4 <__aeabi_dmul+0x470> 80019a2: e096 b.n 8001ad2 <__aeabi_dmul+0x59e> 80019a4: 2300 movs r3, #0 80019a6: 2400 movs r4, #0 80019a8: 2001 movs r0, #1 80019aa: 9301 str r3, [sp, #4] 80019ac: e60c b.n 80015c8 <__aeabi_dmul+0x94> 80019ae: 4649 mov r1, r9 80019b0: 2302 movs r3, #2 80019b2: 9a00 ldr r2, [sp, #0] 80019b4: 432b orrs r3, r5 80019b6: 4051 eors r1, r2 80019b8: b2ca uxtb r2, r1 80019ba: 9203 str r2, [sp, #12] 80019bc: 2b0a cmp r3, #10 80019be: dd00 ble.n 80019c2 <__aeabi_dmul+0x48e> 80019c0: e634 b.n 800162c <__aeabi_dmul+0xf8> 80019c2: 2d00 cmp r5, #0 80019c4: d157 bne.n 8001a76 <__aeabi_dmul+0x542> 80019c6: 9b03 ldr r3, [sp, #12] 80019c8: 4699 mov r9, r3 80019ca: 2400 movs r4, #0 80019cc: 2200 movs r2, #0 80019ce: 4b49 ldr r3, [pc, #292] @ (8001af4 <__aeabi_dmul+0x5c0>) 80019d0: e60e b.n 80015f0 <__aeabi_dmul+0xbc> 80019d2: 4658 mov r0, fp 80019d4: 2101 movs r1, #1 80019d6: 1ac9 subs r1, r1, r3 80019d8: 2938 cmp r1, #56 @ 0x38 80019da: dd00 ble.n 80019de <__aeabi_dmul+0x4aa> 80019dc: e62f b.n 800163e <__aeabi_dmul+0x10a> 80019de: 291f cmp r1, #31 80019e0: dd56 ble.n 8001a90 <__aeabi_dmul+0x55c> 80019e2: 221f movs r2, #31 80019e4: 4654 mov r4, sl 80019e6: 4252 negs r2, r2 80019e8: 1ad3 subs r3, r2, r3 80019ea: 40dc lsrs r4, r3 80019ec: 2920 cmp r1, #32 80019ee: d007 beq.n 8001a00 <__aeabi_dmul+0x4cc> 80019f0: 4b41 ldr r3, [pc, #260] @ (8001af8 <__aeabi_dmul+0x5c4>) 80019f2: 4642 mov r2, r8 80019f4: 469c mov ip, r3 80019f6: 4653 mov r3, sl 80019f8: 4460 add r0, ip 80019fa: 4083 lsls r3, r0 80019fc: 431a orrs r2, r3 80019fe: 4690 mov r8, r2 8001a00: 4642 mov r2, r8 8001a02: 2107 movs r1, #7 8001a04: 1e53 subs r3, r2, #1 8001a06: 419a sbcs r2, r3 8001a08: 000b movs r3, r1 8001a0a: 4322 orrs r2, r4 8001a0c: 4013 ands r3, r2 8001a0e: 2400 movs r4, #0 8001a10: 4211 tst r1, r2 8001a12: d009 beq.n 8001a28 <__aeabi_dmul+0x4f4> 8001a14: 230f movs r3, #15 8001a16: 4013 ands r3, r2 8001a18: 2b04 cmp r3, #4 8001a1a: d05d beq.n 8001ad8 <__aeabi_dmul+0x5a4> 8001a1c: 1d11 adds r1, r2, #4 8001a1e: 4291 cmp r1, r2 8001a20: 419b sbcs r3, r3 8001a22: 000a movs r2, r1 8001a24: 425b negs r3, r3 8001a26: 075b lsls r3, r3, #29 8001a28: 08d2 lsrs r2, r2, #3 8001a2a: 431a orrs r2, r3 8001a2c: 2300 movs r3, #0 8001a2e: e5df b.n 80015f0 <__aeabi_dmul+0xbc> 8001a30: 9b03 ldr r3, [sp, #12] 8001a32: 4699 mov r9, r3 8001a34: e5fa b.n 800162c <__aeabi_dmul+0xf8> 8001a36: 9801 ldr r0, [sp, #4] 8001a38: f000 fda0 bl 800257c <__clzsi2> 8001a3c: 0002 movs r2, r0 8001a3e: 0003 movs r3, r0 8001a40: 3215 adds r2, #21 8001a42: 3320 adds r3, #32 8001a44: 2a1c cmp r2, #28 8001a46: dc00 bgt.n 8001a4a <__aeabi_dmul+0x516> 8001a48: e738 b.n 80018bc <__aeabi_dmul+0x388> 8001a4a: 9a01 ldr r2, [sp, #4] 8001a4c: 3808 subs r0, #8 8001a4e: 4082 lsls r2, r0 8001a50: e73f b.n 80018d2 <__aeabi_dmul+0x39e> 8001a52: f000 fd93 bl 800257c <__clzsi2> 8001a56: 2315 movs r3, #21 8001a58: 469c mov ip, r3 8001a5a: 4484 add ip, r0 8001a5c: 0002 movs r2, r0 8001a5e: 4663 mov r3, ip 8001a60: 3220 adds r2, #32 8001a62: 2b1c cmp r3, #28 8001a64: dc00 bgt.n 8001a68 <__aeabi_dmul+0x534> 8001a66: e758 b.n 800191a <__aeabi_dmul+0x3e6> 8001a68: 2300 movs r3, #0 8001a6a: 4698 mov r8, r3 8001a6c: 0023 movs r3, r4 8001a6e: 3808 subs r0, #8 8001a70: 4083 lsls r3, r0 8001a72: 469a mov sl, r3 8001a74: e762 b.n 800193c <__aeabi_dmul+0x408> 8001a76: 001d movs r5, r3 8001a78: 2300 movs r3, #0 8001a7a: 2400 movs r4, #0 8001a7c: 2002 movs r0, #2 8001a7e: 9301 str r3, [sp, #4] 8001a80: e5a2 b.n 80015c8 <__aeabi_dmul+0x94> 8001a82: 9002 str r0, [sp, #8] 8001a84: e632 b.n 80016ec <__aeabi_dmul+0x1b8> 8001a86: 431c orrs r4, r3 8001a88: 9b00 ldr r3, [sp, #0] 8001a8a: 9a01 ldr r2, [sp, #4] 8001a8c: 4699 mov r9, r3 8001a8e: e5ae b.n 80015ee <__aeabi_dmul+0xba> 8001a90: 4b1a ldr r3, [pc, #104] @ (8001afc <__aeabi_dmul+0x5c8>) 8001a92: 4652 mov r2, sl 8001a94: 18c3 adds r3, r0, r3 8001a96: 4640 mov r0, r8 8001a98: 409a lsls r2, r3 8001a9a: 40c8 lsrs r0, r1 8001a9c: 4302 orrs r2, r0 8001a9e: 4640 mov r0, r8 8001aa0: 4098 lsls r0, r3 8001aa2: 0003 movs r3, r0 8001aa4: 1e58 subs r0, r3, #1 8001aa6: 4183 sbcs r3, r0 8001aa8: 4654 mov r4, sl 8001aaa: 431a orrs r2, r3 8001aac: 40cc lsrs r4, r1 8001aae: 0753 lsls r3, r2, #29 8001ab0: d009 beq.n 8001ac6 <__aeabi_dmul+0x592> 8001ab2: 230f movs r3, #15 8001ab4: 4013 ands r3, r2 8001ab6: 2b04 cmp r3, #4 8001ab8: d005 beq.n 8001ac6 <__aeabi_dmul+0x592> 8001aba: 1d13 adds r3, r2, #4 8001abc: 4293 cmp r3, r2 8001abe: 4192 sbcs r2, r2 8001ac0: 4252 negs r2, r2 8001ac2: 18a4 adds r4, r4, r2 8001ac4: 001a movs r2, r3 8001ac6: 0223 lsls r3, r4, #8 8001ac8: d508 bpl.n 8001adc <__aeabi_dmul+0x5a8> 8001aca: 2301 movs r3, #1 8001acc: 2400 movs r4, #0 8001ace: 2200 movs r2, #0 8001ad0: e58e b.n 80015f0 <__aeabi_dmul+0xbc> 8001ad2: 4689 mov r9, r1 8001ad4: 2400 movs r4, #0 8001ad6: e58b b.n 80015f0 <__aeabi_dmul+0xbc> 8001ad8: 2300 movs r3, #0 8001ada: e7a5 b.n 8001a28 <__aeabi_dmul+0x4f4> 8001adc: 0763 lsls r3, r4, #29 8001ade: 0264 lsls r4, r4, #9 8001ae0: 0b24 lsrs r4, r4, #12 8001ae2: e7a1 b.n 8001a28 <__aeabi_dmul+0x4f4> 8001ae4: 9b00 ldr r3, [sp, #0] 8001ae6: 46a2 mov sl, r4 8001ae8: 4699 mov r9, r3 8001aea: 9b01 ldr r3, [sp, #4] 8001aec: 4698 mov r8, r3 8001aee: e737 b.n 8001960 <__aeabi_dmul+0x42c> 8001af0: fffffc0d .word 0xfffffc0d 8001af4: 000007ff .word 0x000007ff 8001af8: 0000043e .word 0x0000043e 8001afc: 0000041e .word 0x0000041e 08001b00 <__aeabi_dsub>: 8001b00: b5f0 push {r4, r5, r6, r7, lr} 8001b02: 4657 mov r7, sl 8001b04: 464e mov r6, r9 8001b06: 4645 mov r5, r8 8001b08: 46de mov lr, fp 8001b0a: b5e0 push {r5, r6, r7, lr} 8001b0c: b083 sub sp, #12 8001b0e: 9000 str r0, [sp, #0] 8001b10: 9101 str r1, [sp, #4] 8001b12: 030c lsls r4, r1, #12 8001b14: 004d lsls r5, r1, #1 8001b16: 0fce lsrs r6, r1, #31 8001b18: 0a61 lsrs r1, r4, #9 8001b1a: 9c00 ldr r4, [sp, #0] 8001b1c: 005f lsls r7, r3, #1 8001b1e: 0f64 lsrs r4, r4, #29 8001b20: 430c orrs r4, r1 8001b22: 9900 ldr r1, [sp, #0] 8001b24: 9200 str r2, [sp, #0] 8001b26: 9301 str r3, [sp, #4] 8001b28: 00c8 lsls r0, r1, #3 8001b2a: 0319 lsls r1, r3, #12 8001b2c: 0d7b lsrs r3, r7, #21 8001b2e: 4699 mov r9, r3 8001b30: 9b01 ldr r3, [sp, #4] 8001b32: 4fcc ldr r7, [pc, #816] @ (8001e64 <__aeabi_dsub+0x364>) 8001b34: 0fdb lsrs r3, r3, #31 8001b36: 469c mov ip, r3 8001b38: 0a4b lsrs r3, r1, #9 8001b3a: 9900 ldr r1, [sp, #0] 8001b3c: 4680 mov r8, r0 8001b3e: 0f49 lsrs r1, r1, #29 8001b40: 4319 orrs r1, r3 8001b42: 9b00 ldr r3, [sp, #0] 8001b44: 468b mov fp, r1 8001b46: 00da lsls r2, r3, #3 8001b48: 4692 mov sl, r2 8001b4a: 0d6d lsrs r5, r5, #21 8001b4c: 45b9 cmp r9, r7 8001b4e: d100 bne.n 8001b52 <__aeabi_dsub+0x52> 8001b50: e0bf b.n 8001cd2 <__aeabi_dsub+0x1d2> 8001b52: 2301 movs r3, #1 8001b54: 4661 mov r1, ip 8001b56: 4059 eors r1, r3 8001b58: 464b mov r3, r9 8001b5a: 468c mov ip, r1 8001b5c: 1aeb subs r3, r5, r3 8001b5e: 428e cmp r6, r1 8001b60: d075 beq.n 8001c4e <__aeabi_dsub+0x14e> 8001b62: 2b00 cmp r3, #0 8001b64: dc00 bgt.n 8001b68 <__aeabi_dsub+0x68> 8001b66: e2a3 b.n 80020b0 <__aeabi_dsub+0x5b0> 8001b68: 4649 mov r1, r9 8001b6a: 2900 cmp r1, #0 8001b6c: d100 bne.n 8001b70 <__aeabi_dsub+0x70> 8001b6e: e0ce b.n 8001d0e <__aeabi_dsub+0x20e> 8001b70: 42bd cmp r5, r7 8001b72: d100 bne.n 8001b76 <__aeabi_dsub+0x76> 8001b74: e200 b.n 8001f78 <__aeabi_dsub+0x478> 8001b76: 2701 movs r7, #1 8001b78: 2b38 cmp r3, #56 @ 0x38 8001b7a: dc19 bgt.n 8001bb0 <__aeabi_dsub+0xb0> 8001b7c: 2780 movs r7, #128 @ 0x80 8001b7e: 4659 mov r1, fp 8001b80: 043f lsls r7, r7, #16 8001b82: 4339 orrs r1, r7 8001b84: 468b mov fp, r1 8001b86: 2b1f cmp r3, #31 8001b88: dd00 ble.n 8001b8c <__aeabi_dsub+0x8c> 8001b8a: e1fa b.n 8001f82 <__aeabi_dsub+0x482> 8001b8c: 2720 movs r7, #32 8001b8e: 1af9 subs r1, r7, r3 8001b90: 468c mov ip, r1 8001b92: 4659 mov r1, fp 8001b94: 4667 mov r7, ip 8001b96: 40b9 lsls r1, r7 8001b98: 000f movs r7, r1 8001b9a: 0011 movs r1, r2 8001b9c: 40d9 lsrs r1, r3 8001b9e: 430f orrs r7, r1 8001ba0: 4661 mov r1, ip 8001ba2: 408a lsls r2, r1 8001ba4: 1e51 subs r1, r2, #1 8001ba6: 418a sbcs r2, r1 8001ba8: 4659 mov r1, fp 8001baa: 40d9 lsrs r1, r3 8001bac: 4317 orrs r7, r2 8001bae: 1a64 subs r4, r4, r1 8001bb0: 1bc7 subs r7, r0, r7 8001bb2: 42b8 cmp r0, r7 8001bb4: 4180 sbcs r0, r0 8001bb6: 4240 negs r0, r0 8001bb8: 1a24 subs r4, r4, r0 8001bba: 0223 lsls r3, r4, #8 8001bbc: d400 bmi.n 8001bc0 <__aeabi_dsub+0xc0> 8001bbe: e140 b.n 8001e42 <__aeabi_dsub+0x342> 8001bc0: 0264 lsls r4, r4, #9 8001bc2: 0a64 lsrs r4, r4, #9 8001bc4: 2c00 cmp r4, #0 8001bc6: d100 bne.n 8001bca <__aeabi_dsub+0xca> 8001bc8: e154 b.n 8001e74 <__aeabi_dsub+0x374> 8001bca: 0020 movs r0, r4 8001bcc: f000 fcd6 bl 800257c <__clzsi2> 8001bd0: 0003 movs r3, r0 8001bd2: 3b08 subs r3, #8 8001bd4: 2120 movs r1, #32 8001bd6: 0038 movs r0, r7 8001bd8: 1aca subs r2, r1, r3 8001bda: 40d0 lsrs r0, r2 8001bdc: 409c lsls r4, r3 8001bde: 0002 movs r2, r0 8001be0: 409f lsls r7, r3 8001be2: 4322 orrs r2, r4 8001be4: 429d cmp r5, r3 8001be6: dd00 ble.n 8001bea <__aeabi_dsub+0xea> 8001be8: e1a6 b.n 8001f38 <__aeabi_dsub+0x438> 8001bea: 1b58 subs r0, r3, r5 8001bec: 3001 adds r0, #1 8001bee: 1a09 subs r1, r1, r0 8001bf0: 003c movs r4, r7 8001bf2: 408f lsls r7, r1 8001bf4: 40c4 lsrs r4, r0 8001bf6: 1e7b subs r3, r7, #1 8001bf8: 419f sbcs r7, r3 8001bfa: 0013 movs r3, r2 8001bfc: 408b lsls r3, r1 8001bfe: 4327 orrs r7, r4 8001c00: 431f orrs r7, r3 8001c02: 40c2 lsrs r2, r0 8001c04: 003b movs r3, r7 8001c06: 0014 movs r4, r2 8001c08: 2500 movs r5, #0 8001c0a: 4313 orrs r3, r2 8001c0c: d100 bne.n 8001c10 <__aeabi_dsub+0x110> 8001c0e: e1f7 b.n 8002000 <__aeabi_dsub+0x500> 8001c10: 077b lsls r3, r7, #29 8001c12: d100 bne.n 8001c16 <__aeabi_dsub+0x116> 8001c14: e377 b.n 8002306 <__aeabi_dsub+0x806> 8001c16: 230f movs r3, #15 8001c18: 0038 movs r0, r7 8001c1a: 403b ands r3, r7 8001c1c: 2b04 cmp r3, #4 8001c1e: d004 beq.n 8001c2a <__aeabi_dsub+0x12a> 8001c20: 1d38 adds r0, r7, #4 8001c22: 42b8 cmp r0, r7 8001c24: 41bf sbcs r7, r7 8001c26: 427f negs r7, r7 8001c28: 19e4 adds r4, r4, r7 8001c2a: 0223 lsls r3, r4, #8 8001c2c: d400 bmi.n 8001c30 <__aeabi_dsub+0x130> 8001c2e: e368 b.n 8002302 <__aeabi_dsub+0x802> 8001c30: 4b8c ldr r3, [pc, #560] @ (8001e64 <__aeabi_dsub+0x364>) 8001c32: 3501 adds r5, #1 8001c34: 429d cmp r5, r3 8001c36: d100 bne.n 8001c3a <__aeabi_dsub+0x13a> 8001c38: e0f4 b.n 8001e24 <__aeabi_dsub+0x324> 8001c3a: 4b8b ldr r3, [pc, #556] @ (8001e68 <__aeabi_dsub+0x368>) 8001c3c: 056d lsls r5, r5, #21 8001c3e: 401c ands r4, r3 8001c40: 0d6d lsrs r5, r5, #21 8001c42: 0767 lsls r7, r4, #29 8001c44: 08c0 lsrs r0, r0, #3 8001c46: 0264 lsls r4, r4, #9 8001c48: 4307 orrs r7, r0 8001c4a: 0b24 lsrs r4, r4, #12 8001c4c: e0ec b.n 8001e28 <__aeabi_dsub+0x328> 8001c4e: 2b00 cmp r3, #0 8001c50: dc00 bgt.n 8001c54 <__aeabi_dsub+0x154> 8001c52: e329 b.n 80022a8 <__aeabi_dsub+0x7a8> 8001c54: 4649 mov r1, r9 8001c56: 2900 cmp r1, #0 8001c58: d000 beq.n 8001c5c <__aeabi_dsub+0x15c> 8001c5a: e0d6 b.n 8001e0a <__aeabi_dsub+0x30a> 8001c5c: 4659 mov r1, fp 8001c5e: 4311 orrs r1, r2 8001c60: d100 bne.n 8001c64 <__aeabi_dsub+0x164> 8001c62: e12e b.n 8001ec2 <__aeabi_dsub+0x3c2> 8001c64: 1e59 subs r1, r3, #1 8001c66: 2b01 cmp r3, #1 8001c68: d100 bne.n 8001c6c <__aeabi_dsub+0x16c> 8001c6a: e1e6 b.n 800203a <__aeabi_dsub+0x53a> 8001c6c: 42bb cmp r3, r7 8001c6e: d100 bne.n 8001c72 <__aeabi_dsub+0x172> 8001c70: e182 b.n 8001f78 <__aeabi_dsub+0x478> 8001c72: 2701 movs r7, #1 8001c74: 000b movs r3, r1 8001c76: 2938 cmp r1, #56 @ 0x38 8001c78: dc14 bgt.n 8001ca4 <__aeabi_dsub+0x1a4> 8001c7a: 2b1f cmp r3, #31 8001c7c: dd00 ble.n 8001c80 <__aeabi_dsub+0x180> 8001c7e: e23c b.n 80020fa <__aeabi_dsub+0x5fa> 8001c80: 2720 movs r7, #32 8001c82: 1af9 subs r1, r7, r3 8001c84: 468c mov ip, r1 8001c86: 4659 mov r1, fp 8001c88: 4667 mov r7, ip 8001c8a: 40b9 lsls r1, r7 8001c8c: 000f movs r7, r1 8001c8e: 0011 movs r1, r2 8001c90: 40d9 lsrs r1, r3 8001c92: 430f orrs r7, r1 8001c94: 4661 mov r1, ip 8001c96: 408a lsls r2, r1 8001c98: 1e51 subs r1, r2, #1 8001c9a: 418a sbcs r2, r1 8001c9c: 4659 mov r1, fp 8001c9e: 40d9 lsrs r1, r3 8001ca0: 4317 orrs r7, r2 8001ca2: 1864 adds r4, r4, r1 8001ca4: 183f adds r7, r7, r0 8001ca6: 4287 cmp r7, r0 8001ca8: 4180 sbcs r0, r0 8001caa: 4240 negs r0, r0 8001cac: 1824 adds r4, r4, r0 8001cae: 0223 lsls r3, r4, #8 8001cb0: d400 bmi.n 8001cb4 <__aeabi_dsub+0x1b4> 8001cb2: e0c6 b.n 8001e42 <__aeabi_dsub+0x342> 8001cb4: 4b6b ldr r3, [pc, #428] @ (8001e64 <__aeabi_dsub+0x364>) 8001cb6: 3501 adds r5, #1 8001cb8: 429d cmp r5, r3 8001cba: d100 bne.n 8001cbe <__aeabi_dsub+0x1be> 8001cbc: e0b2 b.n 8001e24 <__aeabi_dsub+0x324> 8001cbe: 2101 movs r1, #1 8001cc0: 4b69 ldr r3, [pc, #420] @ (8001e68 <__aeabi_dsub+0x368>) 8001cc2: 087a lsrs r2, r7, #1 8001cc4: 401c ands r4, r3 8001cc6: 4039 ands r1, r7 8001cc8: 430a orrs r2, r1 8001cca: 07e7 lsls r7, r4, #31 8001ccc: 4317 orrs r7, r2 8001cce: 0864 lsrs r4, r4, #1 8001cd0: e79e b.n 8001c10 <__aeabi_dsub+0x110> 8001cd2: 4b66 ldr r3, [pc, #408] @ (8001e6c <__aeabi_dsub+0x36c>) 8001cd4: 4311 orrs r1, r2 8001cd6: 468a mov sl, r1 8001cd8: 18eb adds r3, r5, r3 8001cda: 2900 cmp r1, #0 8001cdc: d028 beq.n 8001d30 <__aeabi_dsub+0x230> 8001cde: 4566 cmp r6, ip 8001ce0: d02c beq.n 8001d3c <__aeabi_dsub+0x23c> 8001ce2: 2b00 cmp r3, #0 8001ce4: d05b beq.n 8001d9e <__aeabi_dsub+0x29e> 8001ce6: 2d00 cmp r5, #0 8001ce8: d100 bne.n 8001cec <__aeabi_dsub+0x1ec> 8001cea: e12c b.n 8001f46 <__aeabi_dsub+0x446> 8001cec: 465b mov r3, fp 8001cee: 4666 mov r6, ip 8001cf0: 075f lsls r7, r3, #29 8001cf2: 08d2 lsrs r2, r2, #3 8001cf4: 4317 orrs r7, r2 8001cf6: 08dd lsrs r5, r3, #3 8001cf8: 003b movs r3, r7 8001cfa: 432b orrs r3, r5 8001cfc: d100 bne.n 8001d00 <__aeabi_dsub+0x200> 8001cfe: e0e2 b.n 8001ec6 <__aeabi_dsub+0x3c6> 8001d00: 2480 movs r4, #128 @ 0x80 8001d02: 0324 lsls r4, r4, #12 8001d04: 432c orrs r4, r5 8001d06: 0324 lsls r4, r4, #12 8001d08: 4d56 ldr r5, [pc, #344] @ (8001e64 <__aeabi_dsub+0x364>) 8001d0a: 0b24 lsrs r4, r4, #12 8001d0c: e08c b.n 8001e28 <__aeabi_dsub+0x328> 8001d0e: 4659 mov r1, fp 8001d10: 4311 orrs r1, r2 8001d12: d100 bne.n 8001d16 <__aeabi_dsub+0x216> 8001d14: e0d5 b.n 8001ec2 <__aeabi_dsub+0x3c2> 8001d16: 1e59 subs r1, r3, #1 8001d18: 2b01 cmp r3, #1 8001d1a: d100 bne.n 8001d1e <__aeabi_dsub+0x21e> 8001d1c: e1b9 b.n 8002092 <__aeabi_dsub+0x592> 8001d1e: 42bb cmp r3, r7 8001d20: d100 bne.n 8001d24 <__aeabi_dsub+0x224> 8001d22: e1b1 b.n 8002088 <__aeabi_dsub+0x588> 8001d24: 2701 movs r7, #1 8001d26: 000b movs r3, r1 8001d28: 2938 cmp r1, #56 @ 0x38 8001d2a: dd00 ble.n 8001d2e <__aeabi_dsub+0x22e> 8001d2c: e740 b.n 8001bb0 <__aeabi_dsub+0xb0> 8001d2e: e72a b.n 8001b86 <__aeabi_dsub+0x86> 8001d30: 4661 mov r1, ip 8001d32: 2701 movs r7, #1 8001d34: 4079 eors r1, r7 8001d36: 468c mov ip, r1 8001d38: 4566 cmp r6, ip 8001d3a: d1d2 bne.n 8001ce2 <__aeabi_dsub+0x1e2> 8001d3c: 2b00 cmp r3, #0 8001d3e: d100 bne.n 8001d42 <__aeabi_dsub+0x242> 8001d40: e0c5 b.n 8001ece <__aeabi_dsub+0x3ce> 8001d42: 2d00 cmp r5, #0 8001d44: d000 beq.n 8001d48 <__aeabi_dsub+0x248> 8001d46: e155 b.n 8001ff4 <__aeabi_dsub+0x4f4> 8001d48: 464b mov r3, r9 8001d4a: 0025 movs r5, r4 8001d4c: 4305 orrs r5, r0 8001d4e: d100 bne.n 8001d52 <__aeabi_dsub+0x252> 8001d50: e212 b.n 8002178 <__aeabi_dsub+0x678> 8001d52: 1e59 subs r1, r3, #1 8001d54: 468c mov ip, r1 8001d56: 2b01 cmp r3, #1 8001d58: d100 bne.n 8001d5c <__aeabi_dsub+0x25c> 8001d5a: e249 b.n 80021f0 <__aeabi_dsub+0x6f0> 8001d5c: 4d41 ldr r5, [pc, #260] @ (8001e64 <__aeabi_dsub+0x364>) 8001d5e: 42ab cmp r3, r5 8001d60: d100 bne.n 8001d64 <__aeabi_dsub+0x264> 8001d62: e28f b.n 8002284 <__aeabi_dsub+0x784> 8001d64: 2701 movs r7, #1 8001d66: 2938 cmp r1, #56 @ 0x38 8001d68: dc11 bgt.n 8001d8e <__aeabi_dsub+0x28e> 8001d6a: 4663 mov r3, ip 8001d6c: 2b1f cmp r3, #31 8001d6e: dd00 ble.n 8001d72 <__aeabi_dsub+0x272> 8001d70: e25b b.n 800222a <__aeabi_dsub+0x72a> 8001d72: 4661 mov r1, ip 8001d74: 2320 movs r3, #32 8001d76: 0027 movs r7, r4 8001d78: 1a5b subs r3, r3, r1 8001d7a: 0005 movs r5, r0 8001d7c: 4098 lsls r0, r3 8001d7e: 409f lsls r7, r3 8001d80: 40cd lsrs r5, r1 8001d82: 1e43 subs r3, r0, #1 8001d84: 4198 sbcs r0, r3 8001d86: 40cc lsrs r4, r1 8001d88: 432f orrs r7, r5 8001d8a: 4307 orrs r7, r0 8001d8c: 44a3 add fp, r4 8001d8e: 18bf adds r7, r7, r2 8001d90: 4297 cmp r7, r2 8001d92: 4192 sbcs r2, r2 8001d94: 4252 negs r2, r2 8001d96: 445a add r2, fp 8001d98: 0014 movs r4, r2 8001d9a: 464d mov r5, r9 8001d9c: e787 b.n 8001cae <__aeabi_dsub+0x1ae> 8001d9e: 4f34 ldr r7, [pc, #208] @ (8001e70 <__aeabi_dsub+0x370>) 8001da0: 1c6b adds r3, r5, #1 8001da2: 423b tst r3, r7 8001da4: d000 beq.n 8001da8 <__aeabi_dsub+0x2a8> 8001da6: e0b6 b.n 8001f16 <__aeabi_dsub+0x416> 8001da8: 4659 mov r1, fp 8001daa: 0023 movs r3, r4 8001dac: 4311 orrs r1, r2 8001dae: 000f movs r7, r1 8001db0: 4303 orrs r3, r0 8001db2: 2d00 cmp r5, #0 8001db4: d000 beq.n 8001db8 <__aeabi_dsub+0x2b8> 8001db6: e126 b.n 8002006 <__aeabi_dsub+0x506> 8001db8: 2b00 cmp r3, #0 8001dba: d100 bne.n 8001dbe <__aeabi_dsub+0x2be> 8001dbc: e1c0 b.n 8002140 <__aeabi_dsub+0x640> 8001dbe: 2900 cmp r1, #0 8001dc0: d100 bne.n 8001dc4 <__aeabi_dsub+0x2c4> 8001dc2: e0a1 b.n 8001f08 <__aeabi_dsub+0x408> 8001dc4: 1a83 subs r3, r0, r2 8001dc6: 4698 mov r8, r3 8001dc8: 465b mov r3, fp 8001dca: 4540 cmp r0, r8 8001dcc: 41ad sbcs r5, r5 8001dce: 1ae3 subs r3, r4, r3 8001dd0: 426d negs r5, r5 8001dd2: 1b5b subs r3, r3, r5 8001dd4: 2580 movs r5, #128 @ 0x80 8001dd6: 042d lsls r5, r5, #16 8001dd8: 422b tst r3, r5 8001dda: d100 bne.n 8001dde <__aeabi_dsub+0x2de> 8001ddc: e14b b.n 8002076 <__aeabi_dsub+0x576> 8001dde: 465b mov r3, fp 8001de0: 1a10 subs r0, r2, r0 8001de2: 4282 cmp r2, r0 8001de4: 4192 sbcs r2, r2 8001de6: 1b1c subs r4, r3, r4 8001de8: 0007 movs r7, r0 8001dea: 2601 movs r6, #1 8001dec: 4663 mov r3, ip 8001dee: 4252 negs r2, r2 8001df0: 1aa4 subs r4, r4, r2 8001df2: 4327 orrs r7, r4 8001df4: 401e ands r6, r3 8001df6: 2f00 cmp r7, #0 8001df8: d100 bne.n 8001dfc <__aeabi_dsub+0x2fc> 8001dfa: e142 b.n 8002082 <__aeabi_dsub+0x582> 8001dfc: 422c tst r4, r5 8001dfe: d100 bne.n 8001e02 <__aeabi_dsub+0x302> 8001e00: e26d b.n 80022de <__aeabi_dsub+0x7de> 8001e02: 4b19 ldr r3, [pc, #100] @ (8001e68 <__aeabi_dsub+0x368>) 8001e04: 2501 movs r5, #1 8001e06: 401c ands r4, r3 8001e08: e71b b.n 8001c42 <__aeabi_dsub+0x142> 8001e0a: 42bd cmp r5, r7 8001e0c: d100 bne.n 8001e10 <__aeabi_dsub+0x310> 8001e0e: e13b b.n 8002088 <__aeabi_dsub+0x588> 8001e10: 2701 movs r7, #1 8001e12: 2b38 cmp r3, #56 @ 0x38 8001e14: dd00 ble.n 8001e18 <__aeabi_dsub+0x318> 8001e16: e745 b.n 8001ca4 <__aeabi_dsub+0x1a4> 8001e18: 2780 movs r7, #128 @ 0x80 8001e1a: 4659 mov r1, fp 8001e1c: 043f lsls r7, r7, #16 8001e1e: 4339 orrs r1, r7 8001e20: 468b mov fp, r1 8001e22: e72a b.n 8001c7a <__aeabi_dsub+0x17a> 8001e24: 2400 movs r4, #0 8001e26: 2700 movs r7, #0 8001e28: 052d lsls r5, r5, #20 8001e2a: 4325 orrs r5, r4 8001e2c: 07f6 lsls r6, r6, #31 8001e2e: 4335 orrs r5, r6 8001e30: 0038 movs r0, r7 8001e32: 0029 movs r1, r5 8001e34: b003 add sp, #12 8001e36: bcf0 pop {r4, r5, r6, r7} 8001e38: 46bb mov fp, r7 8001e3a: 46b2 mov sl, r6 8001e3c: 46a9 mov r9, r5 8001e3e: 46a0 mov r8, r4 8001e40: bdf0 pop {r4, r5, r6, r7, pc} 8001e42: 077b lsls r3, r7, #29 8001e44: d004 beq.n 8001e50 <__aeabi_dsub+0x350> 8001e46: 230f movs r3, #15 8001e48: 403b ands r3, r7 8001e4a: 2b04 cmp r3, #4 8001e4c: d000 beq.n 8001e50 <__aeabi_dsub+0x350> 8001e4e: e6e7 b.n 8001c20 <__aeabi_dsub+0x120> 8001e50: 002b movs r3, r5 8001e52: 08f8 lsrs r0, r7, #3 8001e54: 4a03 ldr r2, [pc, #12] @ (8001e64 <__aeabi_dsub+0x364>) 8001e56: 0767 lsls r7, r4, #29 8001e58: 4307 orrs r7, r0 8001e5a: 08e5 lsrs r5, r4, #3 8001e5c: 4293 cmp r3, r2 8001e5e: d100 bne.n 8001e62 <__aeabi_dsub+0x362> 8001e60: e74a b.n 8001cf8 <__aeabi_dsub+0x1f8> 8001e62: e0a5 b.n 8001fb0 <__aeabi_dsub+0x4b0> 8001e64: 000007ff .word 0x000007ff 8001e68: ff7fffff .word 0xff7fffff 8001e6c: fffff801 .word 0xfffff801 8001e70: 000007fe .word 0x000007fe 8001e74: 0038 movs r0, r7 8001e76: f000 fb81 bl 800257c <__clzsi2> 8001e7a: 0003 movs r3, r0 8001e7c: 3318 adds r3, #24 8001e7e: 2b1f cmp r3, #31 8001e80: dc00 bgt.n 8001e84 <__aeabi_dsub+0x384> 8001e82: e6a7 b.n 8001bd4 <__aeabi_dsub+0xd4> 8001e84: 003a movs r2, r7 8001e86: 3808 subs r0, #8 8001e88: 4082 lsls r2, r0 8001e8a: 429d cmp r5, r3 8001e8c: dd00 ble.n 8001e90 <__aeabi_dsub+0x390> 8001e8e: e08a b.n 8001fa6 <__aeabi_dsub+0x4a6> 8001e90: 1b5b subs r3, r3, r5 8001e92: 1c58 adds r0, r3, #1 8001e94: 281f cmp r0, #31 8001e96: dc00 bgt.n 8001e9a <__aeabi_dsub+0x39a> 8001e98: e1d8 b.n 800224c <__aeabi_dsub+0x74c> 8001e9a: 0017 movs r7, r2 8001e9c: 3b1f subs r3, #31 8001e9e: 40df lsrs r7, r3 8001ea0: 2820 cmp r0, #32 8001ea2: d005 beq.n 8001eb0 <__aeabi_dsub+0x3b0> 8001ea4: 2340 movs r3, #64 @ 0x40 8001ea6: 1a1b subs r3, r3, r0 8001ea8: 409a lsls r2, r3 8001eaa: 1e53 subs r3, r2, #1 8001eac: 419a sbcs r2, r3 8001eae: 4317 orrs r7, r2 8001eb0: 2500 movs r5, #0 8001eb2: 2f00 cmp r7, #0 8001eb4: d100 bne.n 8001eb8 <__aeabi_dsub+0x3b8> 8001eb6: e0e5 b.n 8002084 <__aeabi_dsub+0x584> 8001eb8: 077b lsls r3, r7, #29 8001eba: d000 beq.n 8001ebe <__aeabi_dsub+0x3be> 8001ebc: e6ab b.n 8001c16 <__aeabi_dsub+0x116> 8001ebe: 002c movs r4, r5 8001ec0: e7c6 b.n 8001e50 <__aeabi_dsub+0x350> 8001ec2: 08c0 lsrs r0, r0, #3 8001ec4: e7c6 b.n 8001e54 <__aeabi_dsub+0x354> 8001ec6: 2700 movs r7, #0 8001ec8: 2400 movs r4, #0 8001eca: 4dd1 ldr r5, [pc, #836] @ (8002210 <__aeabi_dsub+0x710>) 8001ecc: e7ac b.n 8001e28 <__aeabi_dsub+0x328> 8001ece: 4fd1 ldr r7, [pc, #836] @ (8002214 <__aeabi_dsub+0x714>) 8001ed0: 1c6b adds r3, r5, #1 8001ed2: 423b tst r3, r7 8001ed4: d171 bne.n 8001fba <__aeabi_dsub+0x4ba> 8001ed6: 0023 movs r3, r4 8001ed8: 4303 orrs r3, r0 8001eda: 2d00 cmp r5, #0 8001edc: d000 beq.n 8001ee0 <__aeabi_dsub+0x3e0> 8001ede: e14e b.n 800217e <__aeabi_dsub+0x67e> 8001ee0: 4657 mov r7, sl 8001ee2: 2b00 cmp r3, #0 8001ee4: d100 bne.n 8001ee8 <__aeabi_dsub+0x3e8> 8001ee6: e1b5 b.n 8002254 <__aeabi_dsub+0x754> 8001ee8: 2f00 cmp r7, #0 8001eea: d00d beq.n 8001f08 <__aeabi_dsub+0x408> 8001eec: 1883 adds r3, r0, r2 8001eee: 4283 cmp r3, r0 8001ef0: 4180 sbcs r0, r0 8001ef2: 445c add r4, fp 8001ef4: 4240 negs r0, r0 8001ef6: 1824 adds r4, r4, r0 8001ef8: 0222 lsls r2, r4, #8 8001efa: d500 bpl.n 8001efe <__aeabi_dsub+0x3fe> 8001efc: e1c8 b.n 8002290 <__aeabi_dsub+0x790> 8001efe: 001f movs r7, r3 8001f00: 4698 mov r8, r3 8001f02: 4327 orrs r7, r4 8001f04: d100 bne.n 8001f08 <__aeabi_dsub+0x408> 8001f06: e0bc b.n 8002082 <__aeabi_dsub+0x582> 8001f08: 4643 mov r3, r8 8001f0a: 0767 lsls r7, r4, #29 8001f0c: 08db lsrs r3, r3, #3 8001f0e: 431f orrs r7, r3 8001f10: 08e5 lsrs r5, r4, #3 8001f12: 2300 movs r3, #0 8001f14: e04c b.n 8001fb0 <__aeabi_dsub+0x4b0> 8001f16: 1a83 subs r3, r0, r2 8001f18: 4698 mov r8, r3 8001f1a: 465b mov r3, fp 8001f1c: 4540 cmp r0, r8 8001f1e: 41bf sbcs r7, r7 8001f20: 1ae3 subs r3, r4, r3 8001f22: 427f negs r7, r7 8001f24: 1bdb subs r3, r3, r7 8001f26: 021f lsls r7, r3, #8 8001f28: d47c bmi.n 8002024 <__aeabi_dsub+0x524> 8001f2a: 4647 mov r7, r8 8001f2c: 431f orrs r7, r3 8001f2e: d100 bne.n 8001f32 <__aeabi_dsub+0x432> 8001f30: e0a6 b.n 8002080 <__aeabi_dsub+0x580> 8001f32: 001c movs r4, r3 8001f34: 4647 mov r7, r8 8001f36: e645 b.n 8001bc4 <__aeabi_dsub+0xc4> 8001f38: 4cb7 ldr r4, [pc, #732] @ (8002218 <__aeabi_dsub+0x718>) 8001f3a: 1aed subs r5, r5, r3 8001f3c: 4014 ands r4, r2 8001f3e: 077b lsls r3, r7, #29 8001f40: d000 beq.n 8001f44 <__aeabi_dsub+0x444> 8001f42: e780 b.n 8001e46 <__aeabi_dsub+0x346> 8001f44: e784 b.n 8001e50 <__aeabi_dsub+0x350> 8001f46: 464b mov r3, r9 8001f48: 0025 movs r5, r4 8001f4a: 4305 orrs r5, r0 8001f4c: d066 beq.n 800201c <__aeabi_dsub+0x51c> 8001f4e: 1e5f subs r7, r3, #1 8001f50: 2b01 cmp r3, #1 8001f52: d100 bne.n 8001f56 <__aeabi_dsub+0x456> 8001f54: e0fc b.n 8002150 <__aeabi_dsub+0x650> 8001f56: 4dae ldr r5, [pc, #696] @ (8002210 <__aeabi_dsub+0x710>) 8001f58: 42ab cmp r3, r5 8001f5a: d100 bne.n 8001f5e <__aeabi_dsub+0x45e> 8001f5c: e15e b.n 800221c <__aeabi_dsub+0x71c> 8001f5e: 4666 mov r6, ip 8001f60: 2f38 cmp r7, #56 @ 0x38 8001f62: dc00 bgt.n 8001f66 <__aeabi_dsub+0x466> 8001f64: e0b4 b.n 80020d0 <__aeabi_dsub+0x5d0> 8001f66: 2001 movs r0, #1 8001f68: 1a17 subs r7, r2, r0 8001f6a: 42ba cmp r2, r7 8001f6c: 4192 sbcs r2, r2 8001f6e: 465b mov r3, fp 8001f70: 4252 negs r2, r2 8001f72: 464d mov r5, r9 8001f74: 1a9c subs r4, r3, r2 8001f76: e620 b.n 8001bba <__aeabi_dsub+0xba> 8001f78: 0767 lsls r7, r4, #29 8001f7a: 08c0 lsrs r0, r0, #3 8001f7c: 4307 orrs r7, r0 8001f7e: 08e5 lsrs r5, r4, #3 8001f80: e6ba b.n 8001cf8 <__aeabi_dsub+0x1f8> 8001f82: 001f movs r7, r3 8001f84: 4659 mov r1, fp 8001f86: 3f20 subs r7, #32 8001f88: 40f9 lsrs r1, r7 8001f8a: 000f movs r7, r1 8001f8c: 2b20 cmp r3, #32 8001f8e: d005 beq.n 8001f9c <__aeabi_dsub+0x49c> 8001f90: 2140 movs r1, #64 @ 0x40 8001f92: 1acb subs r3, r1, r3 8001f94: 4659 mov r1, fp 8001f96: 4099 lsls r1, r3 8001f98: 430a orrs r2, r1 8001f9a: 4692 mov sl, r2 8001f9c: 4653 mov r3, sl 8001f9e: 1e5a subs r2, r3, #1 8001fa0: 4193 sbcs r3, r2 8001fa2: 431f orrs r7, r3 8001fa4: e604 b.n 8001bb0 <__aeabi_dsub+0xb0> 8001fa6: 1aeb subs r3, r5, r3 8001fa8: 4d9b ldr r5, [pc, #620] @ (8002218 <__aeabi_dsub+0x718>) 8001faa: 4015 ands r5, r2 8001fac: 076f lsls r7, r5, #29 8001fae: 08ed lsrs r5, r5, #3 8001fb0: 032c lsls r4, r5, #12 8001fb2: 055d lsls r5, r3, #21 8001fb4: 0b24 lsrs r4, r4, #12 8001fb6: 0d6d lsrs r5, r5, #21 8001fb8: e736 b.n 8001e28 <__aeabi_dsub+0x328> 8001fba: 4d95 ldr r5, [pc, #596] @ (8002210 <__aeabi_dsub+0x710>) 8001fbc: 42ab cmp r3, r5 8001fbe: d100 bne.n 8001fc2 <__aeabi_dsub+0x4c2> 8001fc0: e0d6 b.n 8002170 <__aeabi_dsub+0x670> 8001fc2: 1882 adds r2, r0, r2 8001fc4: 0021 movs r1, r4 8001fc6: 4282 cmp r2, r0 8001fc8: 4180 sbcs r0, r0 8001fca: 4459 add r1, fp 8001fcc: 4240 negs r0, r0 8001fce: 1808 adds r0, r1, r0 8001fd0: 07c7 lsls r7, r0, #31 8001fd2: 0852 lsrs r2, r2, #1 8001fd4: 4317 orrs r7, r2 8001fd6: 0844 lsrs r4, r0, #1 8001fd8: 0752 lsls r2, r2, #29 8001fda: d400 bmi.n 8001fde <__aeabi_dsub+0x4de> 8001fdc: e185 b.n 80022ea <__aeabi_dsub+0x7ea> 8001fde: 220f movs r2, #15 8001fe0: 001d movs r5, r3 8001fe2: 403a ands r2, r7 8001fe4: 2a04 cmp r2, #4 8001fe6: d000 beq.n 8001fea <__aeabi_dsub+0x4ea> 8001fe8: e61a b.n 8001c20 <__aeabi_dsub+0x120> 8001fea: 08ff lsrs r7, r7, #3 8001fec: 0764 lsls r4, r4, #29 8001fee: 4327 orrs r7, r4 8001ff0: 0905 lsrs r5, r0, #4 8001ff2: e7dd b.n 8001fb0 <__aeabi_dsub+0x4b0> 8001ff4: 465b mov r3, fp 8001ff6: 08d2 lsrs r2, r2, #3 8001ff8: 075f lsls r7, r3, #29 8001ffa: 4317 orrs r7, r2 8001ffc: 08dd lsrs r5, r3, #3 8001ffe: e67b b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002000: 2700 movs r7, #0 8002002: 2400 movs r4, #0 8002004: e710 b.n 8001e28 <__aeabi_dsub+0x328> 8002006: 2b00 cmp r3, #0 8002008: d000 beq.n 800200c <__aeabi_dsub+0x50c> 800200a: e0d6 b.n 80021ba <__aeabi_dsub+0x6ba> 800200c: 2900 cmp r1, #0 800200e: d000 beq.n 8002012 <__aeabi_dsub+0x512> 8002010: e12f b.n 8002272 <__aeabi_dsub+0x772> 8002012: 2480 movs r4, #128 @ 0x80 8002014: 2600 movs r6, #0 8002016: 4d7e ldr r5, [pc, #504] @ (8002210 <__aeabi_dsub+0x710>) 8002018: 0324 lsls r4, r4, #12 800201a: e705 b.n 8001e28 <__aeabi_dsub+0x328> 800201c: 4666 mov r6, ip 800201e: 465c mov r4, fp 8002020: 08d0 lsrs r0, r2, #3 8002022: e717 b.n 8001e54 <__aeabi_dsub+0x354> 8002024: 465b mov r3, fp 8002026: 1a17 subs r7, r2, r0 8002028: 42ba cmp r2, r7 800202a: 4192 sbcs r2, r2 800202c: 1b1c subs r4, r3, r4 800202e: 2601 movs r6, #1 8002030: 4663 mov r3, ip 8002032: 4252 negs r2, r2 8002034: 1aa4 subs r4, r4, r2 8002036: 401e ands r6, r3 8002038: e5c4 b.n 8001bc4 <__aeabi_dsub+0xc4> 800203a: 1883 adds r3, r0, r2 800203c: 4283 cmp r3, r0 800203e: 4180 sbcs r0, r0 8002040: 445c add r4, fp 8002042: 4240 negs r0, r0 8002044: 1825 adds r5, r4, r0 8002046: 022a lsls r2, r5, #8 8002048: d400 bmi.n 800204c <__aeabi_dsub+0x54c> 800204a: e0da b.n 8002202 <__aeabi_dsub+0x702> 800204c: 4a72 ldr r2, [pc, #456] @ (8002218 <__aeabi_dsub+0x718>) 800204e: 085b lsrs r3, r3, #1 8002050: 4015 ands r5, r2 8002052: 07ea lsls r2, r5, #31 8002054: 431a orrs r2, r3 8002056: 0869 lsrs r1, r5, #1 8002058: 075b lsls r3, r3, #29 800205a: d400 bmi.n 800205e <__aeabi_dsub+0x55e> 800205c: e14a b.n 80022f4 <__aeabi_dsub+0x7f4> 800205e: 230f movs r3, #15 8002060: 4013 ands r3, r2 8002062: 2b04 cmp r3, #4 8002064: d100 bne.n 8002068 <__aeabi_dsub+0x568> 8002066: e0fc b.n 8002262 <__aeabi_dsub+0x762> 8002068: 1d17 adds r7, r2, #4 800206a: 4297 cmp r7, r2 800206c: 41a4 sbcs r4, r4 800206e: 4264 negs r4, r4 8002070: 2502 movs r5, #2 8002072: 1864 adds r4, r4, r1 8002074: e6ec b.n 8001e50 <__aeabi_dsub+0x350> 8002076: 4647 mov r7, r8 8002078: 001c movs r4, r3 800207a: 431f orrs r7, r3 800207c: d000 beq.n 8002080 <__aeabi_dsub+0x580> 800207e: e743 b.n 8001f08 <__aeabi_dsub+0x408> 8002080: 2600 movs r6, #0 8002082: 2500 movs r5, #0 8002084: 2400 movs r4, #0 8002086: e6cf b.n 8001e28 <__aeabi_dsub+0x328> 8002088: 08c0 lsrs r0, r0, #3 800208a: 0767 lsls r7, r4, #29 800208c: 4307 orrs r7, r0 800208e: 08e5 lsrs r5, r4, #3 8002090: e632 b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002092: 1a87 subs r7, r0, r2 8002094: 465b mov r3, fp 8002096: 42b8 cmp r0, r7 8002098: 4180 sbcs r0, r0 800209a: 1ae4 subs r4, r4, r3 800209c: 4240 negs r0, r0 800209e: 1a24 subs r4, r4, r0 80020a0: 0223 lsls r3, r4, #8 80020a2: d428 bmi.n 80020f6 <__aeabi_dsub+0x5f6> 80020a4: 0763 lsls r3, r4, #29 80020a6: 08ff lsrs r7, r7, #3 80020a8: 431f orrs r7, r3 80020aa: 08e5 lsrs r5, r4, #3 80020ac: 2301 movs r3, #1 80020ae: e77f b.n 8001fb0 <__aeabi_dsub+0x4b0> 80020b0: 2b00 cmp r3, #0 80020b2: d100 bne.n 80020b6 <__aeabi_dsub+0x5b6> 80020b4: e673 b.n 8001d9e <__aeabi_dsub+0x29e> 80020b6: 464b mov r3, r9 80020b8: 1b5f subs r7, r3, r5 80020ba: 003b movs r3, r7 80020bc: 2d00 cmp r5, #0 80020be: d100 bne.n 80020c2 <__aeabi_dsub+0x5c2> 80020c0: e742 b.n 8001f48 <__aeabi_dsub+0x448> 80020c2: 2f38 cmp r7, #56 @ 0x38 80020c4: dd00 ble.n 80020c8 <__aeabi_dsub+0x5c8> 80020c6: e0ec b.n 80022a2 <__aeabi_dsub+0x7a2> 80020c8: 2380 movs r3, #128 @ 0x80 80020ca: 000e movs r6, r1 80020cc: 041b lsls r3, r3, #16 80020ce: 431c orrs r4, r3 80020d0: 2f1f cmp r7, #31 80020d2: dc25 bgt.n 8002120 <__aeabi_dsub+0x620> 80020d4: 2520 movs r5, #32 80020d6: 0023 movs r3, r4 80020d8: 1bed subs r5, r5, r7 80020da: 0001 movs r1, r0 80020dc: 40a8 lsls r0, r5 80020de: 40ab lsls r3, r5 80020e0: 40f9 lsrs r1, r7 80020e2: 1e45 subs r5, r0, #1 80020e4: 41a8 sbcs r0, r5 80020e6: 430b orrs r3, r1 80020e8: 40fc lsrs r4, r7 80020ea: 4318 orrs r0, r3 80020ec: 465b mov r3, fp 80020ee: 1b1b subs r3, r3, r4 80020f0: 469b mov fp, r3 80020f2: e739 b.n 8001f68 <__aeabi_dsub+0x468> 80020f4: 4666 mov r6, ip 80020f6: 2501 movs r5, #1 80020f8: e562 b.n 8001bc0 <__aeabi_dsub+0xc0> 80020fa: 001f movs r7, r3 80020fc: 4659 mov r1, fp 80020fe: 3f20 subs r7, #32 8002100: 40f9 lsrs r1, r7 8002102: 468c mov ip, r1 8002104: 2b20 cmp r3, #32 8002106: d005 beq.n 8002114 <__aeabi_dsub+0x614> 8002108: 2740 movs r7, #64 @ 0x40 800210a: 4659 mov r1, fp 800210c: 1afb subs r3, r7, r3 800210e: 4099 lsls r1, r3 8002110: 430a orrs r2, r1 8002112: 4692 mov sl, r2 8002114: 4657 mov r7, sl 8002116: 1e7b subs r3, r7, #1 8002118: 419f sbcs r7, r3 800211a: 4663 mov r3, ip 800211c: 431f orrs r7, r3 800211e: e5c1 b.n 8001ca4 <__aeabi_dsub+0x1a4> 8002120: 003b movs r3, r7 8002122: 0025 movs r5, r4 8002124: 3b20 subs r3, #32 8002126: 40dd lsrs r5, r3 8002128: 2f20 cmp r7, #32 800212a: d004 beq.n 8002136 <__aeabi_dsub+0x636> 800212c: 2340 movs r3, #64 @ 0x40 800212e: 1bdb subs r3, r3, r7 8002130: 409c lsls r4, r3 8002132: 4320 orrs r0, r4 8002134: 4680 mov r8, r0 8002136: 4640 mov r0, r8 8002138: 1e43 subs r3, r0, #1 800213a: 4198 sbcs r0, r3 800213c: 4328 orrs r0, r5 800213e: e713 b.n 8001f68 <__aeabi_dsub+0x468> 8002140: 2900 cmp r1, #0 8002142: d09d beq.n 8002080 <__aeabi_dsub+0x580> 8002144: 2601 movs r6, #1 8002146: 4663 mov r3, ip 8002148: 465c mov r4, fp 800214a: 4690 mov r8, r2 800214c: 401e ands r6, r3 800214e: e6db b.n 8001f08 <__aeabi_dsub+0x408> 8002150: 1a17 subs r7, r2, r0 8002152: 465b mov r3, fp 8002154: 42ba cmp r2, r7 8002156: 4192 sbcs r2, r2 8002158: 1b1c subs r4, r3, r4 800215a: 4252 negs r2, r2 800215c: 1aa4 subs r4, r4, r2 800215e: 0223 lsls r3, r4, #8 8002160: d4c8 bmi.n 80020f4 <__aeabi_dsub+0x5f4> 8002162: 0763 lsls r3, r4, #29 8002164: 08ff lsrs r7, r7, #3 8002166: 431f orrs r7, r3 8002168: 4666 mov r6, ip 800216a: 2301 movs r3, #1 800216c: 08e5 lsrs r5, r4, #3 800216e: e71f b.n 8001fb0 <__aeabi_dsub+0x4b0> 8002170: 001d movs r5, r3 8002172: 2400 movs r4, #0 8002174: 2700 movs r7, #0 8002176: e657 b.n 8001e28 <__aeabi_dsub+0x328> 8002178: 465c mov r4, fp 800217a: 08d0 lsrs r0, r2, #3 800217c: e66a b.n 8001e54 <__aeabi_dsub+0x354> 800217e: 2b00 cmp r3, #0 8002180: d100 bne.n 8002184 <__aeabi_dsub+0x684> 8002182: e737 b.n 8001ff4 <__aeabi_dsub+0x4f4> 8002184: 4653 mov r3, sl 8002186: 08c0 lsrs r0, r0, #3 8002188: 0767 lsls r7, r4, #29 800218a: 4307 orrs r7, r0 800218c: 08e5 lsrs r5, r4, #3 800218e: 2b00 cmp r3, #0 8002190: d100 bne.n 8002194 <__aeabi_dsub+0x694> 8002192: e5b1 b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002194: 2380 movs r3, #128 @ 0x80 8002196: 031b lsls r3, r3, #12 8002198: 421d tst r5, r3 800219a: d008 beq.n 80021ae <__aeabi_dsub+0x6ae> 800219c: 4659 mov r1, fp 800219e: 08c8 lsrs r0, r1, #3 80021a0: 4218 tst r0, r3 80021a2: d104 bne.n 80021ae <__aeabi_dsub+0x6ae> 80021a4: 08d2 lsrs r2, r2, #3 80021a6: 0749 lsls r1, r1, #29 80021a8: 430a orrs r2, r1 80021aa: 0017 movs r7, r2 80021ac: 0005 movs r5, r0 80021ae: 0f7b lsrs r3, r7, #29 80021b0: 00ff lsls r7, r7, #3 80021b2: 08ff lsrs r7, r7, #3 80021b4: 075b lsls r3, r3, #29 80021b6: 431f orrs r7, r3 80021b8: e59e b.n 8001cf8 <__aeabi_dsub+0x1f8> 80021ba: 08c0 lsrs r0, r0, #3 80021bc: 0763 lsls r3, r4, #29 80021be: 4318 orrs r0, r3 80021c0: 08e5 lsrs r5, r4, #3 80021c2: 2900 cmp r1, #0 80021c4: d053 beq.n 800226e <__aeabi_dsub+0x76e> 80021c6: 2380 movs r3, #128 @ 0x80 80021c8: 031b lsls r3, r3, #12 80021ca: 421d tst r5, r3 80021cc: d00a beq.n 80021e4 <__aeabi_dsub+0x6e4> 80021ce: 4659 mov r1, fp 80021d0: 08cc lsrs r4, r1, #3 80021d2: 421c tst r4, r3 80021d4: d106 bne.n 80021e4 <__aeabi_dsub+0x6e4> 80021d6: 2601 movs r6, #1 80021d8: 4663 mov r3, ip 80021da: 0025 movs r5, r4 80021dc: 08d0 lsrs r0, r2, #3 80021de: 0749 lsls r1, r1, #29 80021e0: 4308 orrs r0, r1 80021e2: 401e ands r6, r3 80021e4: 0f47 lsrs r7, r0, #29 80021e6: 00c0 lsls r0, r0, #3 80021e8: 08c0 lsrs r0, r0, #3 80021ea: 077f lsls r7, r7, #29 80021ec: 4307 orrs r7, r0 80021ee: e583 b.n 8001cf8 <__aeabi_dsub+0x1f8> 80021f0: 1883 adds r3, r0, r2 80021f2: 4293 cmp r3, r2 80021f4: 4192 sbcs r2, r2 80021f6: 445c add r4, fp 80021f8: 4252 negs r2, r2 80021fa: 18a5 adds r5, r4, r2 80021fc: 022a lsls r2, r5, #8 80021fe: d500 bpl.n 8002202 <__aeabi_dsub+0x702> 8002200: e724 b.n 800204c <__aeabi_dsub+0x54c> 8002202: 076f lsls r7, r5, #29 8002204: 08db lsrs r3, r3, #3 8002206: 431f orrs r7, r3 8002208: 08ed lsrs r5, r5, #3 800220a: 2301 movs r3, #1 800220c: e6d0 b.n 8001fb0 <__aeabi_dsub+0x4b0> 800220e: 46c0 nop @ (mov r8, r8) 8002210: 000007ff .word 0x000007ff 8002214: 000007fe .word 0x000007fe 8002218: ff7fffff .word 0xff7fffff 800221c: 465b mov r3, fp 800221e: 08d2 lsrs r2, r2, #3 8002220: 075f lsls r7, r3, #29 8002222: 4666 mov r6, ip 8002224: 4317 orrs r7, r2 8002226: 08dd lsrs r5, r3, #3 8002228: e566 b.n 8001cf8 <__aeabi_dsub+0x1f8> 800222a: 0025 movs r5, r4 800222c: 3b20 subs r3, #32 800222e: 40dd lsrs r5, r3 8002230: 4663 mov r3, ip 8002232: 2b20 cmp r3, #32 8002234: d005 beq.n 8002242 <__aeabi_dsub+0x742> 8002236: 2340 movs r3, #64 @ 0x40 8002238: 4661 mov r1, ip 800223a: 1a5b subs r3, r3, r1 800223c: 409c lsls r4, r3 800223e: 4320 orrs r0, r4 8002240: 4680 mov r8, r0 8002242: 4647 mov r7, r8 8002244: 1e7b subs r3, r7, #1 8002246: 419f sbcs r7, r3 8002248: 432f orrs r7, r5 800224a: e5a0 b.n 8001d8e <__aeabi_dsub+0x28e> 800224c: 2120 movs r1, #32 800224e: 2700 movs r7, #0 8002250: 1a09 subs r1, r1, r0 8002252: e4d2 b.n 8001bfa <__aeabi_dsub+0xfa> 8002254: 2f00 cmp r7, #0 8002256: d100 bne.n 800225a <__aeabi_dsub+0x75a> 8002258: e713 b.n 8002082 <__aeabi_dsub+0x582> 800225a: 465c mov r4, fp 800225c: 0017 movs r7, r2 800225e: 2500 movs r5, #0 8002260: e5f6 b.n 8001e50 <__aeabi_dsub+0x350> 8002262: 08d7 lsrs r7, r2, #3 8002264: 0749 lsls r1, r1, #29 8002266: 2302 movs r3, #2 8002268: 430f orrs r7, r1 800226a: 092d lsrs r5, r5, #4 800226c: e6a0 b.n 8001fb0 <__aeabi_dsub+0x4b0> 800226e: 0007 movs r7, r0 8002270: e542 b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002272: 465b mov r3, fp 8002274: 2601 movs r6, #1 8002276: 075f lsls r7, r3, #29 8002278: 08dd lsrs r5, r3, #3 800227a: 4663 mov r3, ip 800227c: 08d2 lsrs r2, r2, #3 800227e: 4317 orrs r7, r2 8002280: 401e ands r6, r3 8002282: e539 b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002284: 465b mov r3, fp 8002286: 08d2 lsrs r2, r2, #3 8002288: 075f lsls r7, r3, #29 800228a: 4317 orrs r7, r2 800228c: 08dd lsrs r5, r3, #3 800228e: e533 b.n 8001cf8 <__aeabi_dsub+0x1f8> 8002290: 4a1e ldr r2, [pc, #120] @ (800230c <__aeabi_dsub+0x80c>) 8002292: 08db lsrs r3, r3, #3 8002294: 4022 ands r2, r4 8002296: 0757 lsls r7, r2, #29 8002298: 0252 lsls r2, r2, #9 800229a: 2501 movs r5, #1 800229c: 431f orrs r7, r3 800229e: 0b14 lsrs r4, r2, #12 80022a0: e5c2 b.n 8001e28 <__aeabi_dsub+0x328> 80022a2: 000e movs r6, r1 80022a4: 2001 movs r0, #1 80022a6: e65f b.n 8001f68 <__aeabi_dsub+0x468> 80022a8: 2b00 cmp r3, #0 80022aa: d00d beq.n 80022c8 <__aeabi_dsub+0x7c8> 80022ac: 464b mov r3, r9 80022ae: 1b5b subs r3, r3, r5 80022b0: 469c mov ip, r3 80022b2: 2d00 cmp r5, #0 80022b4: d100 bne.n 80022b8 <__aeabi_dsub+0x7b8> 80022b6: e548 b.n 8001d4a <__aeabi_dsub+0x24a> 80022b8: 2701 movs r7, #1 80022ba: 2b38 cmp r3, #56 @ 0x38 80022bc: dd00 ble.n 80022c0 <__aeabi_dsub+0x7c0> 80022be: e566 b.n 8001d8e <__aeabi_dsub+0x28e> 80022c0: 2380 movs r3, #128 @ 0x80 80022c2: 041b lsls r3, r3, #16 80022c4: 431c orrs r4, r3 80022c6: e550 b.n 8001d6a <__aeabi_dsub+0x26a> 80022c8: 1c6b adds r3, r5, #1 80022ca: 4d11 ldr r5, [pc, #68] @ (8002310 <__aeabi_dsub+0x810>) 80022cc: 422b tst r3, r5 80022ce: d000 beq.n 80022d2 <__aeabi_dsub+0x7d2> 80022d0: e673 b.n 8001fba <__aeabi_dsub+0x4ba> 80022d2: 4659 mov r1, fp 80022d4: 0023 movs r3, r4 80022d6: 4311 orrs r1, r2 80022d8: 468a mov sl, r1 80022da: 4303 orrs r3, r0 80022dc: e600 b.n 8001ee0 <__aeabi_dsub+0x3e0> 80022de: 0767 lsls r7, r4, #29 80022e0: 08c0 lsrs r0, r0, #3 80022e2: 2300 movs r3, #0 80022e4: 4307 orrs r7, r0 80022e6: 08e5 lsrs r5, r4, #3 80022e8: e662 b.n 8001fb0 <__aeabi_dsub+0x4b0> 80022ea: 0764 lsls r4, r4, #29 80022ec: 08ff lsrs r7, r7, #3 80022ee: 4327 orrs r7, r4 80022f0: 0905 lsrs r5, r0, #4 80022f2: e65d b.n 8001fb0 <__aeabi_dsub+0x4b0> 80022f4: 08d2 lsrs r2, r2, #3 80022f6: 0749 lsls r1, r1, #29 80022f8: 4311 orrs r1, r2 80022fa: 000f movs r7, r1 80022fc: 2302 movs r3, #2 80022fe: 092d lsrs r5, r5, #4 8002300: e656 b.n 8001fb0 <__aeabi_dsub+0x4b0> 8002302: 0007 movs r7, r0 8002304: e5a4 b.n 8001e50 <__aeabi_dsub+0x350> 8002306: 0038 movs r0, r7 8002308: e48f b.n 8001c2a <__aeabi_dsub+0x12a> 800230a: 46c0 nop @ (mov r8, r8) 800230c: ff7fffff .word 0xff7fffff 8002310: 000007fe .word 0x000007fe 08002314 <__aeabi_d2iz>: 8002314: 000b movs r3, r1 8002316: 0002 movs r2, r0 8002318: b570 push {r4, r5, r6, lr} 800231a: 4d16 ldr r5, [pc, #88] @ (8002374 <__aeabi_d2iz+0x60>) 800231c: 030c lsls r4, r1, #12 800231e: b082 sub sp, #8 8002320: 0049 lsls r1, r1, #1 8002322: 2000 movs r0, #0 8002324: 9200 str r2, [sp, #0] 8002326: 9301 str r3, [sp, #4] 8002328: 0b24 lsrs r4, r4, #12 800232a: 0d49 lsrs r1, r1, #21 800232c: 0fde lsrs r6, r3, #31 800232e: 42a9 cmp r1, r5 8002330: dd04 ble.n 800233c <__aeabi_d2iz+0x28> 8002332: 4811 ldr r0, [pc, #68] @ (8002378 <__aeabi_d2iz+0x64>) 8002334: 4281 cmp r1, r0 8002336: dd03 ble.n 8002340 <__aeabi_d2iz+0x2c> 8002338: 4b10 ldr r3, [pc, #64] @ (800237c <__aeabi_d2iz+0x68>) 800233a: 18f0 adds r0, r6, r3 800233c: b002 add sp, #8 800233e: bd70 pop {r4, r5, r6, pc} 8002340: 2080 movs r0, #128 @ 0x80 8002342: 0340 lsls r0, r0, #13 8002344: 4320 orrs r0, r4 8002346: 4c0e ldr r4, [pc, #56] @ (8002380 <__aeabi_d2iz+0x6c>) 8002348: 1a64 subs r4, r4, r1 800234a: 2c1f cmp r4, #31 800234c: dd08 ble.n 8002360 <__aeabi_d2iz+0x4c> 800234e: 4b0d ldr r3, [pc, #52] @ (8002384 <__aeabi_d2iz+0x70>) 8002350: 1a5b subs r3, r3, r1 8002352: 40d8 lsrs r0, r3 8002354: 0003 movs r3, r0 8002356: 4258 negs r0, r3 8002358: 2e00 cmp r6, #0 800235a: d1ef bne.n 800233c <__aeabi_d2iz+0x28> 800235c: 0018 movs r0, r3 800235e: e7ed b.n 800233c <__aeabi_d2iz+0x28> 8002360: 4b09 ldr r3, [pc, #36] @ (8002388 <__aeabi_d2iz+0x74>) 8002362: 9a00 ldr r2, [sp, #0] 8002364: 469c mov ip, r3 8002366: 0003 movs r3, r0 8002368: 4461 add r1, ip 800236a: 408b lsls r3, r1 800236c: 40e2 lsrs r2, r4 800236e: 4313 orrs r3, r2 8002370: e7f1 b.n 8002356 <__aeabi_d2iz+0x42> 8002372: 46c0 nop @ (mov r8, r8) 8002374: 000003fe .word 0x000003fe 8002378: 0000041d .word 0x0000041d 800237c: 7fffffff .word 0x7fffffff 8002380: 00000433 .word 0x00000433 8002384: 00000413 .word 0x00000413 8002388: fffffbed .word 0xfffffbed 0800238c <__aeabi_i2d>: 800238c: b570 push {r4, r5, r6, lr} 800238e: 2800 cmp r0, #0 8002390: d016 beq.n 80023c0 <__aeabi_i2d+0x34> 8002392: 17c3 asrs r3, r0, #31 8002394: 18c5 adds r5, r0, r3 8002396: 405d eors r5, r3 8002398: 0fc4 lsrs r4, r0, #31 800239a: 0028 movs r0, r5 800239c: f000 f8ee bl 800257c <__clzsi2> 80023a0: 4b10 ldr r3, [pc, #64] @ (80023e4 <__aeabi_i2d+0x58>) 80023a2: 1a1b subs r3, r3, r0 80023a4: 055b lsls r3, r3, #21 80023a6: 0d5b lsrs r3, r3, #21 80023a8: 280a cmp r0, #10 80023aa: dc14 bgt.n 80023d6 <__aeabi_i2d+0x4a> 80023ac: 0002 movs r2, r0 80023ae: 002e movs r6, r5 80023b0: 3215 adds r2, #21 80023b2: 4096 lsls r6, r2 80023b4: 220b movs r2, #11 80023b6: 1a12 subs r2, r2, r0 80023b8: 40d5 lsrs r5, r2 80023ba: 032d lsls r5, r5, #12 80023bc: 0b2d lsrs r5, r5, #12 80023be: e003 b.n 80023c8 <__aeabi_i2d+0x3c> 80023c0: 2400 movs r4, #0 80023c2: 2300 movs r3, #0 80023c4: 2500 movs r5, #0 80023c6: 2600 movs r6, #0 80023c8: 051b lsls r3, r3, #20 80023ca: 432b orrs r3, r5 80023cc: 07e4 lsls r4, r4, #31 80023ce: 4323 orrs r3, r4 80023d0: 0030 movs r0, r6 80023d2: 0019 movs r1, r3 80023d4: bd70 pop {r4, r5, r6, pc} 80023d6: 380b subs r0, #11 80023d8: 4085 lsls r5, r0 80023da: 032d lsls r5, r5, #12 80023dc: 2600 movs r6, #0 80023de: 0b2d lsrs r5, r5, #12 80023e0: e7f2 b.n 80023c8 <__aeabi_i2d+0x3c> 80023e2: 46c0 nop @ (mov r8, r8) 80023e4: 0000041e .word 0x0000041e 080023e8 <__aeabi_f2d>: 80023e8: b570 push {r4, r5, r6, lr} 80023ea: 0242 lsls r2, r0, #9 80023ec: 0043 lsls r3, r0, #1 80023ee: 0fc4 lsrs r4, r0, #31 80023f0: 20fe movs r0, #254 @ 0xfe 80023f2: 0e1b lsrs r3, r3, #24 80023f4: 1c59 adds r1, r3, #1 80023f6: 0a55 lsrs r5, r2, #9 80023f8: 4208 tst r0, r1 80023fa: d00c beq.n 8002416 <__aeabi_f2d+0x2e> 80023fc: 21e0 movs r1, #224 @ 0xe0 80023fe: 0089 lsls r1, r1, #2 8002400: 468c mov ip, r1 8002402: 076d lsls r5, r5, #29 8002404: 0b12 lsrs r2, r2, #12 8002406: 4463 add r3, ip 8002408: 051b lsls r3, r3, #20 800240a: 4313 orrs r3, r2 800240c: 07e4 lsls r4, r4, #31 800240e: 4323 orrs r3, r4 8002410: 0028 movs r0, r5 8002412: 0019 movs r1, r3 8002414: bd70 pop {r4, r5, r6, pc} 8002416: 2b00 cmp r3, #0 8002418: d114 bne.n 8002444 <__aeabi_f2d+0x5c> 800241a: 2d00 cmp r5, #0 800241c: d01b beq.n 8002456 <__aeabi_f2d+0x6e> 800241e: 0028 movs r0, r5 8002420: f000 f8ac bl 800257c <__clzsi2> 8002424: 280a cmp r0, #10 8002426: dc1c bgt.n 8002462 <__aeabi_f2d+0x7a> 8002428: 230b movs r3, #11 800242a: 002a movs r2, r5 800242c: 1a1b subs r3, r3, r0 800242e: 40da lsrs r2, r3 8002430: 0003 movs r3, r0 8002432: 3315 adds r3, #21 8002434: 409d lsls r5, r3 8002436: 4b0e ldr r3, [pc, #56] @ (8002470 <__aeabi_f2d+0x88>) 8002438: 0312 lsls r2, r2, #12 800243a: 1a1b subs r3, r3, r0 800243c: 055b lsls r3, r3, #21 800243e: 0b12 lsrs r2, r2, #12 8002440: 0d5b lsrs r3, r3, #21 8002442: e7e1 b.n 8002408 <__aeabi_f2d+0x20> 8002444: 2d00 cmp r5, #0 8002446: d009 beq.n 800245c <__aeabi_f2d+0x74> 8002448: 0b13 lsrs r3, r2, #12 800244a: 2280 movs r2, #128 @ 0x80 800244c: 0312 lsls r2, r2, #12 800244e: 431a orrs r2, r3 8002450: 076d lsls r5, r5, #29 8002452: 4b08 ldr r3, [pc, #32] @ (8002474 <__aeabi_f2d+0x8c>) 8002454: e7d8 b.n 8002408 <__aeabi_f2d+0x20> 8002456: 2300 movs r3, #0 8002458: 2200 movs r2, #0 800245a: e7d5 b.n 8002408 <__aeabi_f2d+0x20> 800245c: 2200 movs r2, #0 800245e: 4b05 ldr r3, [pc, #20] @ (8002474 <__aeabi_f2d+0x8c>) 8002460: e7d2 b.n 8002408 <__aeabi_f2d+0x20> 8002462: 0003 movs r3, r0 8002464: 002a movs r2, r5 8002466: 3b0b subs r3, #11 8002468: 409a lsls r2, r3 800246a: 2500 movs r5, #0 800246c: e7e3 b.n 8002436 <__aeabi_f2d+0x4e> 800246e: 46c0 nop @ (mov r8, r8) 8002470: 00000389 .word 0x00000389 8002474: 000007ff .word 0x000007ff 08002478 <__aeabi_d2f>: 8002478: b5f0 push {r4, r5, r6, r7, lr} 800247a: 004b lsls r3, r1, #1 800247c: 030f lsls r7, r1, #12 800247e: 0d5b lsrs r3, r3, #21 8002480: 4c3a ldr r4, [pc, #232] @ (800256c <__aeabi_d2f+0xf4>) 8002482: 0f45 lsrs r5, r0, #29 8002484: b083 sub sp, #12 8002486: 0a7f lsrs r7, r7, #9 8002488: 1c5e adds r6, r3, #1 800248a: 432f orrs r7, r5 800248c: 9000 str r0, [sp, #0] 800248e: 9101 str r1, [sp, #4] 8002490: 0fca lsrs r2, r1, #31 8002492: 00c5 lsls r5, r0, #3 8002494: 4226 tst r6, r4 8002496: d00b beq.n 80024b0 <__aeabi_d2f+0x38> 8002498: 4935 ldr r1, [pc, #212] @ (8002570 <__aeabi_d2f+0xf8>) 800249a: 185c adds r4, r3, r1 800249c: 2cfe cmp r4, #254 @ 0xfe 800249e: dd13 ble.n 80024c8 <__aeabi_d2f+0x50> 80024a0: 20ff movs r0, #255 @ 0xff 80024a2: 2300 movs r3, #0 80024a4: 05c0 lsls r0, r0, #23 80024a6: 4318 orrs r0, r3 80024a8: 07d2 lsls r2, r2, #31 80024aa: 4310 orrs r0, r2 80024ac: b003 add sp, #12 80024ae: bdf0 pop {r4, r5, r6, r7, pc} 80024b0: 433d orrs r5, r7 80024b2: 2b00 cmp r3, #0 80024b4: d101 bne.n 80024ba <__aeabi_d2f+0x42> 80024b6: 2000 movs r0, #0 80024b8: e7f4 b.n 80024a4 <__aeabi_d2f+0x2c> 80024ba: 2d00 cmp r5, #0 80024bc: d0f0 beq.n 80024a0 <__aeabi_d2f+0x28> 80024be: 2380 movs r3, #128 @ 0x80 80024c0: 03db lsls r3, r3, #15 80024c2: 20ff movs r0, #255 @ 0xff 80024c4: 433b orrs r3, r7 80024c6: e7ed b.n 80024a4 <__aeabi_d2f+0x2c> 80024c8: 2c00 cmp r4, #0 80024ca: dd0c ble.n 80024e6 <__aeabi_d2f+0x6e> 80024cc: 9b00 ldr r3, [sp, #0] 80024ce: 00ff lsls r7, r7, #3 80024d0: 019b lsls r3, r3, #6 80024d2: 1e58 subs r0, r3, #1 80024d4: 4183 sbcs r3, r0 80024d6: 0f69 lsrs r1, r5, #29 80024d8: 433b orrs r3, r7 80024da: 430b orrs r3, r1 80024dc: 0759 lsls r1, r3, #29 80024de: d127 bne.n 8002530 <__aeabi_d2f+0xb8> 80024e0: 08db lsrs r3, r3, #3 80024e2: b2e0 uxtb r0, r4 80024e4: e7de b.n 80024a4 <__aeabi_d2f+0x2c> 80024e6: 0021 movs r1, r4 80024e8: 3117 adds r1, #23 80024ea: db31 blt.n 8002550 <__aeabi_d2f+0xd8> 80024ec: 2180 movs r1, #128 @ 0x80 80024ee: 201e movs r0, #30 80024f0: 0409 lsls r1, r1, #16 80024f2: 4339 orrs r1, r7 80024f4: 1b00 subs r0, r0, r4 80024f6: 281f cmp r0, #31 80024f8: dd2d ble.n 8002556 <__aeabi_d2f+0xde> 80024fa: 2602 movs r6, #2 80024fc: 4276 negs r6, r6 80024fe: 1b34 subs r4, r6, r4 8002500: 000e movs r6, r1 8002502: 40e6 lsrs r6, r4 8002504: 0034 movs r4, r6 8002506: 2820 cmp r0, #32 8002508: d004 beq.n 8002514 <__aeabi_d2f+0x9c> 800250a: 481a ldr r0, [pc, #104] @ (8002574 <__aeabi_d2f+0xfc>) 800250c: 4684 mov ip, r0 800250e: 4463 add r3, ip 8002510: 4099 lsls r1, r3 8002512: 430d orrs r5, r1 8002514: 002b movs r3, r5 8002516: 1e59 subs r1, r3, #1 8002518: 418b sbcs r3, r1 800251a: 4323 orrs r3, r4 800251c: 0759 lsls r1, r3, #29 800251e: d003 beq.n 8002528 <__aeabi_d2f+0xb0> 8002520: 210f movs r1, #15 8002522: 4019 ands r1, r3 8002524: 2904 cmp r1, #4 8002526: d10b bne.n 8002540 <__aeabi_d2f+0xc8> 8002528: 019b lsls r3, r3, #6 800252a: 2000 movs r0, #0 800252c: 0a5b lsrs r3, r3, #9 800252e: e7b9 b.n 80024a4 <__aeabi_d2f+0x2c> 8002530: 210f movs r1, #15 8002532: 4019 ands r1, r3 8002534: 2904 cmp r1, #4 8002536: d104 bne.n 8002542 <__aeabi_d2f+0xca> 8002538: 019b lsls r3, r3, #6 800253a: 0a5b lsrs r3, r3, #9 800253c: b2e0 uxtb r0, r4 800253e: e7b1 b.n 80024a4 <__aeabi_d2f+0x2c> 8002540: 2400 movs r4, #0 8002542: 3304 adds r3, #4 8002544: 0159 lsls r1, r3, #5 8002546: d5f7 bpl.n 8002538 <__aeabi_d2f+0xc0> 8002548: 3401 adds r4, #1 800254a: 2300 movs r3, #0 800254c: b2e0 uxtb r0, r4 800254e: e7a9 b.n 80024a4 <__aeabi_d2f+0x2c> 8002550: 2000 movs r0, #0 8002552: 2300 movs r3, #0 8002554: e7a6 b.n 80024a4 <__aeabi_d2f+0x2c> 8002556: 4c08 ldr r4, [pc, #32] @ (8002578 <__aeabi_d2f+0x100>) 8002558: 191c adds r4, r3, r4 800255a: 002b movs r3, r5 800255c: 40a5 lsls r5, r4 800255e: 40c3 lsrs r3, r0 8002560: 40a1 lsls r1, r4 8002562: 1e68 subs r0, r5, #1 8002564: 4185 sbcs r5, r0 8002566: 4329 orrs r1, r5 8002568: 430b orrs r3, r1 800256a: e7d7 b.n 800251c <__aeabi_d2f+0xa4> 800256c: 000007fe .word 0x000007fe 8002570: fffffc80 .word 0xfffffc80 8002574: fffffca2 .word 0xfffffca2 8002578: fffffc82 .word 0xfffffc82 0800257c <__clzsi2>: 800257c: 211c movs r1, #28 800257e: 2301 movs r3, #1 8002580: 041b lsls r3, r3, #16 8002582: 4298 cmp r0, r3 8002584: d301 bcc.n 800258a <__clzsi2+0xe> 8002586: 0c00 lsrs r0, r0, #16 8002588: 3910 subs r1, #16 800258a: 0a1b lsrs r3, r3, #8 800258c: 4298 cmp r0, r3 800258e: d301 bcc.n 8002594 <__clzsi2+0x18> 8002590: 0a00 lsrs r0, r0, #8 8002592: 3908 subs r1, #8 8002594: 091b lsrs r3, r3, #4 8002596: 4298 cmp r0, r3 8002598: d301 bcc.n 800259e <__clzsi2+0x22> 800259a: 0900 lsrs r0, r0, #4 800259c: 3904 subs r1, #4 800259e: a202 add r2, pc, #8 @ (adr r2, 80025a8 <__clzsi2+0x2c>) 80025a0: 5c10 ldrb r0, [r2, r0] 80025a2: 1840 adds r0, r0, r1 80025a4: 4770 bx lr 80025a6: 46c0 nop @ (mov r8, r8) 80025a8: 02020304 .word 0x02020304 80025ac: 01010101 .word 0x01010101 ... 080025b8 <main>: /** * @brief The application entry point. * @retval int */ int main(void) { 80025b8: b580 push {r7, lr} 80025ba: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80025bc: f000 fdc4 bl 8003148 <HAL_Init> /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80025c0: f000 f928 bl 8002814 <SystemClock_Config> /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80025c4: f000 f9d4 bl 8002970 <MX_GPIO_Init> MX_SPI1_Init(); 80025c8: f000 f96c bl 80028a4 <MX_SPI1_Init> MX_TIM17_Init(); 80025cc: f000 f9a8 bl 8002920 <MX_TIM17_Init> /* USER CODE BEGIN 2 */ flag_change_signal = 0; 80025d0: 4b80 ldr r3, [pc, #512] @ (80027d4 <main+0x21c>) 80025d2: 2200 movs r2, #0 80025d4: 701a strb r2, [r3, #0] flag_freq_increase = 0; 80025d6: 4b80 ldr r3, [pc, #512] @ (80027d8 <main+0x220>) 80025d8: 2200 movs r2, #0 80025da: 701a strb r2, [r3, #0] flag_freq_decrease = 0; 80025dc: 4b7f ldr r3, [pc, #508] @ (80027dc <main+0x224>) 80025de: 2200 movs r2, #0 80025e0: 701a strb r2, [r3, #0] flag_tim17_overflow = 0; 80025e2: 4b7f ldr r3, [pc, #508] @ (80027e0 <main+0x228>) 80025e4: 2200 movs r2, #0 80025e6: 701a strb r2, [r3, #0] signal_form = 0; 80025e8: 4b7e ldr r3, [pc, #504] @ (80027e4 <main+0x22c>) 80025ea: 2200 movs r2, #0 80025ec: 701a strb r2, [r3, #0] n = 10; // Nbr de pts dans une période A DEFINIR SELON LA FREQ 80025ee: 4b7e ldr r3, [pc, #504] @ (80027e8 <main+0x230>) 80025f0: 220a movs r2, #10 80025f2: 701a strb r2, [r3, #0] i = 0; // Le point numéro i 80025f4: 4b7d ldr r3, [pc, #500] @ (80027ec <main+0x234>) 80025f6: 2200 movs r2, #0 80025f8: 701a strb r2, [r3, #0] HAL_TIM_Base_Start_IT(&htim17); 80025fa: 4b7d ldr r3, [pc, #500] @ (80027f0 <main+0x238>) 80025fc: 0018 movs r0, r3 80025fe: f002 f85b bl 80046b8 <HAL_TIM_Base_Start_IT> SPI1->CR1 |= 0x904 ; /* 100 1000 0100 ou 0x904 */ 8002602: 4b7c ldr r3, [pc, #496] @ (80027f4 <main+0x23c>) 8002604: 681a ldr r2, [r3, #0] 8002606: 4b7b ldr r3, [pc, #492] @ (80027f4 <main+0x23c>) 8002608: 497b ldr r1, [pc, #492] @ (80027f8 <main+0x240>) 800260a: 430a orrs r2, r1 800260c: 601a str r2, [r3, #0] /* RXONLY = 1 ;SSM=0 ;SSI = 0 ;LSBFIRST=1; SPE=0 ;BR=000 ;MSTR = 1 ;CPOL = 0 ;CPHA = 0 */ SPI1->CR2 = 3852 ; 800260e: 4b79 ldr r3, [pc, #484] @ (80027f4 <main+0x23c>) 8002610: 4a7a ldr r2, [pc, #488] @ (80027fc <main+0x244>) 8002612: 605a str r2, [r3, #4] /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { if (flag_tim17_overflow) 8002614: 4b72 ldr r3, [pc, #456] @ (80027e0 <main+0x228>) 8002616: 781b ldrb r3, [r3, #0] 8002618: b2db uxtb r3, r3 800261a: 2b00 cmp r3, #0 800261c: d0fa beq.n 8002614 <main+0x5c> { flag_tim17_overflow = 0; 800261e: 4b70 ldr r3, [pc, #448] @ (80027e0 <main+0x228>) 8002620: 2200 movs r2, #0 8002622: 701a strb r2, [r3, #0] if(flag_change_signal) 8002624: 4b6b ldr r3, [pc, #428] @ (80027d4 <main+0x21c>) 8002626: 781b ldrb r3, [r3, #0] 8002628: 2b00 cmp r3, #0 800262a: d00f beq.n 800264c <main+0x94> { flag_change_signal = 0; 800262c: 4b69 ldr r3, [pc, #420] @ (80027d4 <main+0x21c>) 800262e: 2200 movs r2, #0 8002630: 701a strb r2, [r3, #0] signal_form ++ ; 8002632: 4b6c ldr r3, [pc, #432] @ (80027e4 <main+0x22c>) 8002634: 781b ldrb r3, [r3, #0] 8002636: 3301 adds r3, #1 8002638: b2da uxtb r2, r3 800263a: 4b6a ldr r3, [pc, #424] @ (80027e4 <main+0x22c>) 800263c: 701a strb r2, [r3, #0] if(signal_form > 2) 800263e: 4b69 ldr r3, [pc, #420] @ (80027e4 <main+0x22c>) 8002640: 781b ldrb r3, [r3, #0] 8002642: 2b02 cmp r3, #2 8002644: d902 bls.n 800264c <main+0x94> { signal_form = 0; 8002646: 4b67 ldr r3, [pc, #412] @ (80027e4 <main+0x22c>) 8002648: 2200 movs r2, #0 800264a: 701a strb r2, [r3, #0] } } if (signal_form == 0) 800264c: 4b65 ldr r3, [pc, #404] @ (80027e4 <main+0x22c>) 800264e: 781b ldrb r3, [r3, #0] 8002650: 2b00 cmp r3, #0 8002652: d104 bne.n 800265e <main+0xa6> { // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_RESET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET); Signal_square(msg_spi, 2); 8002654: 4b6a ldr r3, [pc, #424] @ (8002800 <main+0x248>) 8002656: 2102 movs r1, #2 8002658: 0018 movs r0, r3 800265a: f000 fa05 bl 8002a68 <Signal_square> } if (signal_form == 1) 800265e: 4b61 ldr r3, [pc, #388] @ (80027e4 <main+0x22c>) 8002660: 781b ldrb r3, [r3, #0] 8002662: 2b01 cmp r3, #1 8002664: d127 bne.n 80026b6 <main+0xfe> { // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET); Signal_triangle(default_bits, bits, n, i); 8002666: 4b60 ldr r3, [pc, #384] @ (80027e8 <main+0x230>) 8002668: 781a ldrb r2, [r3, #0] 800266a: 4b60 ldr r3, [pc, #384] @ (80027ec <main+0x234>) 800266c: 781b ldrb r3, [r3, #0] 800266e: 4965 ldr r1, [pc, #404] @ (8002804 <main+0x24c>) 8002670: 4865 ldr r0, [pc, #404] @ (8002808 <main+0x250>) 8002672: f000 fa39 bl 8002ae8 <Signal_triangle> i++; 8002676: 4b5d ldr r3, [pc, #372] @ (80027ec <main+0x234>) 8002678: 781b ldrb r3, [r3, #0] 800267a: 3301 adds r3, #1 800267c: b2da uxtb r2, r3 800267e: 4b5b ldr r3, [pc, #364] @ (80027ec <main+0x234>) 8002680: 701a strb r2, [r3, #0] if (n%2) // si impair 8002682: 4b59 ldr r3, [pc, #356] @ (80027e8 <main+0x230>) 8002684: 781b ldrb r3, [r3, #0] 8002686: 2201 movs r2, #1 8002688: 4013 ands r3, r2 800268a: b2db uxtb r3, r3 800268c: 2b00 cmp r3, #0 800268e: d009 beq.n 80026a4 <main+0xec> { if(i > n) 8002690: 4b56 ldr r3, [pc, #344] @ (80027ec <main+0x234>) 8002692: 781a ldrb r2, [r3, #0] 8002694: 4b54 ldr r3, [pc, #336] @ (80027e8 <main+0x230>) 8002696: 781b ldrb r3, [r3, #0] 8002698: 429a cmp r2, r3 800269a: d90c bls.n 80026b6 <main+0xfe> { i = 0; 800269c: 4b53 ldr r3, [pc, #332] @ (80027ec <main+0x234>) 800269e: 2200 movs r2, #0 80026a0: 701a strb r2, [r3, #0] 80026a2: e008 b.n 80026b6 <main+0xfe> } } else // si pair { if(i >= n) 80026a4: 4b51 ldr r3, [pc, #324] @ (80027ec <main+0x234>) 80026a6: 781a ldrb r2, [r3, #0] 80026a8: 4b4f ldr r3, [pc, #316] @ (80027e8 <main+0x230>) 80026aa: 781b ldrb r3, [r3, #0] 80026ac: 429a cmp r2, r3 80026ae: d302 bcc.n 80026b6 <main+0xfe> { i = 0; 80026b0: 4b4e ldr r3, [pc, #312] @ (80027ec <main+0x234>) 80026b2: 2200 movs r2, #0 80026b4: 701a strb r2, [r3, #0] } } } if (signal_form == 2) 80026b6: 4b4b ldr r3, [pc, #300] @ (80027e4 <main+0x22c>) 80026b8: 781b ldrb r3, [r3, #0] 80026ba: 2b02 cmp r3, #2 80026bc: d116 bne.n 80026ec <main+0x134> { // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_RESET); // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_SET); Signal_sine(default_bits, bits, n, i); 80026be: 4b4a ldr r3, [pc, #296] @ (80027e8 <main+0x230>) 80026c0: 781a ldrb r2, [r3, #0] 80026c2: 4b4a ldr r3, [pc, #296] @ (80027ec <main+0x234>) 80026c4: 781b ldrb r3, [r3, #0] 80026c6: 494f ldr r1, [pc, #316] @ (8002804 <main+0x24c>) 80026c8: 484f ldr r0, [pc, #316] @ (8002808 <main+0x250>) 80026ca: f000 faa3 bl 8002c14 <Signal_sine> i++; 80026ce: 4b47 ldr r3, [pc, #284] @ (80027ec <main+0x234>) 80026d0: 781b ldrb r3, [r3, #0] 80026d2: 3301 adds r3, #1 80026d4: b2da uxtb r2, r3 80026d6: 4b45 ldr r3, [pc, #276] @ (80027ec <main+0x234>) 80026d8: 701a strb r2, [r3, #0] if(i > n) 80026da: 4b44 ldr r3, [pc, #272] @ (80027ec <main+0x234>) 80026dc: 781a ldrb r2, [r3, #0] 80026de: 4b42 ldr r3, [pc, #264] @ (80027e8 <main+0x230>) 80026e0: 781b ldrb r3, [r3, #0] 80026e2: 429a cmp r2, r3 80026e4: d902 bls.n 80026ec <main+0x134> { i = 0; 80026e6: 4b41 ldr r3, [pc, #260] @ (80027ec <main+0x234>) 80026e8: 2200 movs r2, #0 80026ea: 701a strb r2, [r3, #0] } } if(flag_freq_decrease) 80026ec: 4b3b ldr r3, [pc, #236] @ (80027dc <main+0x224>) 80026ee: 781b ldrb r3, [r3, #0] 80026f0: 2b00 cmp r3, #0 80026f2: d036 beq.n 8002762 <main+0x1aa> { flag_freq_decrease = 0; 80026f4: 4b39 ldr r3, [pc, #228] @ (80027dc <main+0x224>) 80026f6: 2200 movs r2, #0 80026f8: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); 80026fa: 23a0 movs r3, #160 @ 0xa0 80026fc: 05db lsls r3, r3, #23 80026fe: 2200 movs r2, #0 8002700: 2120 movs r1, #32 8002702: 0018 movs r0, r3 8002704: f001 f876 bl 80037f4 <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); 8002708: 23a0 movs r3, #160 @ 0xa0 800270a: 05db lsls r3, r3, #23 800270c: 2201 movs r2, #1 800270e: 2140 movs r1, #64 @ 0x40 8002710: 0018 movs r0, r3 8002712: f001 f86f bl 80037f4 <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET); 8002716: 23a0 movs r3, #160 @ 0xa0 8002718: 05db lsls r3, r3, #23 800271a: 2200 movs r2, #0 800271c: 2180 movs r1, #128 @ 0x80 800271e: 0018 movs r0, r3 8002720: f001 f868 bl 80037f4 <HAL_GPIO_WritePin> new_prescaler = (htim17.Init.Prescaler + 1) * 2; 8002724: 4b32 ldr r3, [pc, #200] @ (80027f0 <main+0x238>) 8002726: 685b ldr r3, [r3, #4] 8002728: 3301 adds r3, #1 800272a: b29b uxth r3, r3 800272c: 18db adds r3, r3, r3 800272e: b29a uxth r2, r3 8002730: 4b36 ldr r3, [pc, #216] @ (800280c <main+0x254>) 8002732: 801a strh r2, [r3, #0] if(new_prescaler >= 65535) 8002734: 4b35 ldr r3, [pc, #212] @ (800280c <main+0x254>) 8002736: 881b ldrh r3, [r3, #0] 8002738: 4a35 ldr r2, [pc, #212] @ (8002810 <main+0x258>) 800273a: 4293 cmp r3, r2 800273c: d103 bne.n 8002746 <main+0x18e> { new_prescaler = 65535; 800273e: 4b33 ldr r3, [pc, #204] @ (800280c <main+0x254>) 8002740: 2201 movs r2, #1 8002742: 4252 negs r2, r2 8002744: 801a strh r2, [r3, #0] } htim17.Init.Prescaler = new_prescaler - 2; 8002746: 4b31 ldr r3, [pc, #196] @ (800280c <main+0x254>) 8002748: 881b ldrh r3, [r3, #0] 800274a: 3b02 subs r3, #2 800274c: 001a movs r2, r3 800274e: 4b28 ldr r3, [pc, #160] @ (80027f0 <main+0x238>) 8002750: 605a str r2, [r3, #4] HAL_TIM_Base_Init(&htim17); 8002752: 4b27 ldr r3, [pc, #156] @ (80027f0 <main+0x238>) 8002754: 0018 movs r0, r3 8002756: f001 ff57 bl 8004608 <HAL_TIM_Base_Init> HAL_TIM_Base_Start_IT(&htim17); 800275a: 4b25 ldr r3, [pc, #148] @ (80027f0 <main+0x238>) 800275c: 0018 movs r0, r3 800275e: f001 ffab bl 80046b8 <HAL_TIM_Base_Start_IT> } if(flag_freq_increase) 8002762: 4b1d ldr r3, [pc, #116] @ (80027d8 <main+0x220>) 8002764: 781b ldrb r3, [r3, #0] 8002766: 2b00 cmp r3, #0 8002768: d100 bne.n 800276c <main+0x1b4> 800276a: e753 b.n 8002614 <main+0x5c> { flag_freq_increase = 0; 800276c: 4b1a ldr r3, [pc, #104] @ (80027d8 <main+0x220>) 800276e: 2200 movs r2, #0 8002770: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); 8002772: 23a0 movs r3, #160 @ 0xa0 8002774: 05db lsls r3, r3, #23 8002776: 2201 movs r2, #1 8002778: 2120 movs r1, #32 800277a: 0018 movs r0, r3 800277c: f001 f83a bl 80037f4 <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_RESET); 8002780: 23a0 movs r3, #160 @ 0xa0 8002782: 05db lsls r3, r3, #23 8002784: 2200 movs r2, #0 8002786: 2140 movs r1, #64 @ 0x40 8002788: 0018 movs r0, r3 800278a: f001 f833 bl 80037f4 <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET); 800278e: 23a0 movs r3, #160 @ 0xa0 8002790: 05db lsls r3, r3, #23 8002792: 2200 movs r2, #0 8002794: 2180 movs r1, #128 @ 0x80 8002796: 0018 movs r0, r3 8002798: f001 f82c bl 80037f4 <HAL_GPIO_WritePin> new_prescaler = (htim17.Init.Prescaler + 1) / 2; 800279c: 4b14 ldr r3, [pc, #80] @ (80027f0 <main+0x238>) 800279e: 685b ldr r3, [r3, #4] 80027a0: 3301 adds r3, #1 80027a2: 085b lsrs r3, r3, #1 80027a4: b29a uxth r2, r3 80027a6: 4b19 ldr r3, [pc, #100] @ (800280c <main+0x254>) 80027a8: 801a strh r2, [r3, #0] if(new_prescaler <= 2) 80027aa: 4b18 ldr r3, [pc, #96] @ (800280c <main+0x254>) 80027ac: 881b ldrh r3, [r3, #0] 80027ae: 2b02 cmp r3, #2 80027b0: d802 bhi.n 80027b8 <main+0x200> { new_prescaler = 2; 80027b2: 4b16 ldr r3, [pc, #88] @ (800280c <main+0x254>) 80027b4: 2202 movs r2, #2 80027b6: 801a strh r2, [r3, #0] } htim17.Init.Prescaler = new_prescaler; 80027b8: 4b14 ldr r3, [pc, #80] @ (800280c <main+0x254>) 80027ba: 881b ldrh r3, [r3, #0] 80027bc: 001a movs r2, r3 80027be: 4b0c ldr r3, [pc, #48] @ (80027f0 <main+0x238>) 80027c0: 605a str r2, [r3, #4] HAL_TIM_Base_Init(&htim17); 80027c2: 4b0b ldr r3, [pc, #44] @ (80027f0 <main+0x238>) 80027c4: 0018 movs r0, r3 80027c6: f001 ff1f bl 8004608 <HAL_TIM_Base_Init> HAL_TIM_Base_Start_IT(&htim17); 80027ca: 4b09 ldr r3, [pc, #36] @ (80027f0 <main+0x238>) 80027cc: 0018 movs r0, r3 80027ce: f001 ff73 bl 80046b8 <HAL_TIM_Base_Start_IT> if (flag_tim17_overflow) 80027d2: e71f b.n 8002614 <main+0x5c> 80027d4: 200000fa .word 0x200000fa 80027d8: 200000fb .word 0x200000fb 80027dc: 200000fc .word 0x200000fc 80027e0: 200000fd .word 0x200000fd 80027e4: 200000f4 .word 0x200000f4 80027e8: 200000f5 .word 0x200000f5 80027ec: 200000f6 .word 0x200000f6 80027f0: 200000a0 .word 0x200000a0 80027f4: 40013000 .word 0x40013000 80027f8: 00000904 .word 0x00000904 80027fc: 00000f0c .word 0x00000f0c 8002800: 20000000 .word 0x20000000 8002804: 200000ec .word 0x200000ec 8002808: 20000004 .word 0x20000004 800280c: 200000f8 .word 0x200000f8 8002810: 0000ffff .word 0x0000ffff 08002814 <SystemClock_Config>: /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8002814: b590 push {r4, r7, lr} 8002816: b093 sub sp, #76 @ 0x4c 8002818: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800281a: 2410 movs r4, #16 800281c: 193b adds r3, r7, r4 800281e: 0018 movs r0, r3 8002820: 2338 movs r3, #56 @ 0x38 8002822: 001a movs r2, r3 8002824: 2100 movs r1, #0 8002826: f002 f95f bl 8004ae8 <memset> RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800282a: 003b movs r3, r7 800282c: 0018 movs r0, r3 800282e: 2310 movs r3, #16 8002830: 001a movs r2, r3 8002832: 2100 movs r1, #0 8002834: f002 f958 bl 8004ae8 <memset> /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8002838: 2380 movs r3, #128 @ 0x80 800283a: 009b lsls r3, r3, #2 800283c: 0018 movs r0, r3 800283e: f001 f82b bl 8003898 <HAL_PWREx_ControlVoltageScaling> /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8002842: 193b adds r3, r7, r4 8002844: 2202 movs r2, #2 8002846: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8002848: 193b adds r3, r7, r4 800284a: 2280 movs r2, #128 @ 0x80 800284c: 0052 lsls r2, r2, #1 800284e: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; 8002850: 193b adds r3, r7, r4 8002852: 2200 movs r2, #0 8002854: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8002856: 193b adds r3, r7, r4 8002858: 2240 movs r2, #64 @ 0x40 800285a: 615a str r2, [r3, #20] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 800285c: 193b adds r3, r7, r4 800285e: 2200 movs r2, #0 8002860: 61da str r2, [r3, #28] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8002862: 193b adds r3, r7, r4 8002864: 0018 movs r0, r3 8002866: f001 f857 bl 8003918 <HAL_RCC_OscConfig> 800286a: 1e03 subs r3, r0, #0 800286c: d001 beq.n 8002872 <SystemClock_Config+0x5e> { Error_Handler(); 800286e: f000 fb13 bl 8002e98 <Error_Handler> } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8002872: 003b movs r3, r7 8002874: 2207 movs r2, #7 8002876: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 8002878: 003b movs r3, r7 800287a: 2200 movs r2, #0 800287c: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800287e: 003b movs r3, r7 8002880: 2200 movs r2, #0 8002882: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8002884: 003b movs r3, r7 8002886: 2200 movs r2, #0 8002888: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 800288a: 003b movs r3, r7 800288c: 2100 movs r1, #0 800288e: 0018 movs r0, r3 8002890: f001 fb5c bl 8003f4c <HAL_RCC_ClockConfig> 8002894: 1e03 subs r3, r0, #0 8002896: d001 beq.n 800289c <SystemClock_Config+0x88> { Error_Handler(); 8002898: f000 fafe bl 8002e98 <Error_Handler> } } 800289c: 46c0 nop @ (mov r8, r8) 800289e: 46bd mov sp, r7 80028a0: b013 add sp, #76 @ 0x4c 80028a2: bd90 pop {r4, r7, pc} 080028a4 <MX_SPI1_Init>: * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 80028a4: b580 push {r7, lr} 80028a6: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 80028a8: 4b1b ldr r3, [pc, #108] @ (8002918 <MX_SPI1_Init+0x74>) 80028aa: 4a1c ldr r2, [pc, #112] @ (800291c <MX_SPI1_Init+0x78>) 80028ac: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 80028ae: 4b1a ldr r3, [pc, #104] @ (8002918 <MX_SPI1_Init+0x74>) 80028b0: 2282 movs r2, #130 @ 0x82 80028b2: 0052 lsls r2, r2, #1 80028b4: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 80028b6: 4b18 ldr r3, [pc, #96] @ (8002918 <MX_SPI1_Init+0x74>) 80028b8: 2200 movs r2, #0 80028ba: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_16BIT; 80028bc: 4b16 ldr r3, [pc, #88] @ (8002918 <MX_SPI1_Init+0x74>) 80028be: 22f0 movs r2, #240 @ 0xf0 80028c0: 0112 lsls r2, r2, #4 80028c2: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; 80028c4: 4b14 ldr r3, [pc, #80] @ (8002918 <MX_SPI1_Init+0x74>) 80028c6: 2202 movs r2, #2 80028c8: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_2EDGE; 80028ca: 4b13 ldr r3, [pc, #76] @ (8002918 <MX_SPI1_Init+0x74>) 80028cc: 2201 movs r2, #1 80028ce: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; 80028d0: 4b11 ldr r3, [pc, #68] @ (8002918 <MX_SPI1_Init+0x74>) 80028d2: 2280 movs r2, #128 @ 0x80 80028d4: 02d2 lsls r2, r2, #11 80028d6: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 80028d8: 4b0f ldr r3, [pc, #60] @ (8002918 <MX_SPI1_Init+0x74>) 80028da: 2200 movs r2, #0 80028dc: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 80028de: 4b0e ldr r3, [pc, #56] @ (8002918 <MX_SPI1_Init+0x74>) 80028e0: 2200 movs r2, #0 80028e2: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 80028e4: 4b0c ldr r3, [pc, #48] @ (8002918 <MX_SPI1_Init+0x74>) 80028e6: 2200 movs r2, #0 80028e8: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80028ea: 4b0b ldr r3, [pc, #44] @ (8002918 <MX_SPI1_Init+0x74>) 80028ec: 2200 movs r2, #0 80028ee: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 7; 80028f0: 4b09 ldr r3, [pc, #36] @ (8002918 <MX_SPI1_Init+0x74>) 80028f2: 2207 movs r2, #7 80028f4: 62da str r2, [r3, #44] @ 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 80028f6: 4b08 ldr r3, [pc, #32] @ (8002918 <MX_SPI1_Init+0x74>) 80028f8: 2200 movs r2, #0 80028fa: 631a str r2, [r3, #48] @ 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; 80028fc: 4b06 ldr r3, [pc, #24] @ (8002918 <MX_SPI1_Init+0x74>) 80028fe: 2200 movs r2, #0 8002900: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 8002902: 4b05 ldr r3, [pc, #20] @ (8002918 <MX_SPI1_Init+0x74>) 8002904: 0018 movs r0, r3 8002906: f001 fcab bl 8004260 <HAL_SPI_Init> 800290a: 1e03 subs r3, r0, #0 800290c: d001 beq.n 8002912 <MX_SPI1_Init+0x6e> { Error_Handler(); 800290e: f000 fac3 bl 8002e98 <Error_Handler> } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8002912: 46c0 nop @ (mov r8, r8) 8002914: 46bd mov sp, r7 8002916: bd80 pop {r7, pc} 8002918: 2000003c .word 0x2000003c 800291c: 40013000 .word 0x40013000 08002920 <MX_TIM17_Init>: * @brief TIM17 Initialization Function * @param None * @retval None */ static void MX_TIM17_Init(void) { 8002920: b580 push {r7, lr} 8002922: af00 add r7, sp, #0 /* USER CODE END TIM17_Init 0 */ /* USER CODE BEGIN TIM17_Init 1 */ /* USER CODE END TIM17_Init 1 */ htim17.Instance = TIM17; 8002924: 4b10 ldr r3, [pc, #64] @ (8002968 <MX_TIM17_Init+0x48>) 8002926: 4a11 ldr r2, [pc, #68] @ (800296c <MX_TIM17_Init+0x4c>) 8002928: 601a str r2, [r3, #0] htim17.Init.Prescaler = 32000; 800292a: 4b0f ldr r3, [pc, #60] @ (8002968 <MX_TIM17_Init+0x48>) 800292c: 22fa movs r2, #250 @ 0xfa 800292e: 01d2 lsls r2, r2, #7 8002930: 605a str r2, [r3, #4] htim17.Init.CounterMode = TIM_COUNTERMODE_UP; 8002932: 4b0d ldr r3, [pc, #52] @ (8002968 <MX_TIM17_Init+0x48>) 8002934: 2200 movs r2, #0 8002936: 609a str r2, [r3, #8] htim17.Init.Period = 500; 8002938: 4b0b ldr r3, [pc, #44] @ (8002968 <MX_TIM17_Init+0x48>) 800293a: 22fa movs r2, #250 @ 0xfa 800293c: 0052 lsls r2, r2, #1 800293e: 60da str r2, [r3, #12] htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002940: 4b09 ldr r3, [pc, #36] @ (8002968 <MX_TIM17_Init+0x48>) 8002942: 2200 movs r2, #0 8002944: 611a str r2, [r3, #16] htim17.Init.RepetitionCounter = 0; 8002946: 4b08 ldr r3, [pc, #32] @ (8002968 <MX_TIM17_Init+0x48>) 8002948: 2200 movs r2, #0 800294a: 615a str r2, [r3, #20] htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800294c: 4b06 ldr r3, [pc, #24] @ (8002968 <MX_TIM17_Init+0x48>) 800294e: 2200 movs r2, #0 8002950: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim17) != HAL_OK) 8002952: 4b05 ldr r3, [pc, #20] @ (8002968 <MX_TIM17_Init+0x48>) 8002954: 0018 movs r0, r3 8002956: f001 fe57 bl 8004608 <HAL_TIM_Base_Init> 800295a: 1e03 subs r3, r0, #0 800295c: d001 beq.n 8002962 <MX_TIM17_Init+0x42> { Error_Handler(); 800295e: f000 fa9b bl 8002e98 <Error_Handler> } /* USER CODE BEGIN TIM17_Init 2 */ /* USER CODE END TIM17_Init 2 */ } 8002962: 46c0 nop @ (mov r8, r8) 8002964: 46bd mov sp, r7 8002966: bd80 pop {r7, pc} 8002968: 200000a0 .word 0x200000a0 800296c: 40014800 .word 0x40014800 08002970 <MX_GPIO_Init>: * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8002970: b590 push {r4, r7, lr} 8002972: b089 sub sp, #36 @ 0x24 8002974: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002976: 240c movs r4, #12 8002978: 193b adds r3, r7, r4 800297a: 0018 movs r0, r3 800297c: 2314 movs r3, #20 800297e: 001a movs r2, r3 8002980: 2100 movs r1, #0 8002982: f002 f8b1 bl 8004ae8 <memset> /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8002986: 4b36 ldr r3, [pc, #216] @ (8002a60 <MX_GPIO_Init+0xf0>) 8002988: 6b5a ldr r2, [r3, #52] @ 0x34 800298a: 4b35 ldr r3, [pc, #212] @ (8002a60 <MX_GPIO_Init+0xf0>) 800298c: 2104 movs r1, #4 800298e: 430a orrs r2, r1 8002990: 635a str r2, [r3, #52] @ 0x34 8002992: 4b33 ldr r3, [pc, #204] @ (8002a60 <MX_GPIO_Init+0xf0>) 8002994: 6b5b ldr r3, [r3, #52] @ 0x34 8002996: 2204 movs r2, #4 8002998: 4013 ands r3, r2 800299a: 60bb str r3, [r7, #8] 800299c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 800299e: 4b30 ldr r3, [pc, #192] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029a0: 6b5a ldr r2, [r3, #52] @ 0x34 80029a2: 4b2f ldr r3, [pc, #188] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029a4: 2101 movs r1, #1 80029a6: 430a orrs r2, r1 80029a8: 635a str r2, [r3, #52] @ 0x34 80029aa: 4b2d ldr r3, [pc, #180] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029ac: 6b5b ldr r3, [r3, #52] @ 0x34 80029ae: 2201 movs r2, #1 80029b0: 4013 ands r3, r2 80029b2: 607b str r3, [r7, #4] 80029b4: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 80029b6: 4b2a ldr r3, [pc, #168] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029b8: 6b5a ldr r2, [r3, #52] @ 0x34 80029ba: 4b29 ldr r3, [pc, #164] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029bc: 2102 movs r1, #2 80029be: 430a orrs r2, r1 80029c0: 635a str r2, [r3, #52] @ 0x34 80029c2: 4b27 ldr r3, [pc, #156] @ (8002a60 <MX_GPIO_Init+0xf0>) 80029c4: 6b5b ldr r3, [r3, #52] @ 0x34 80029c6: 2202 movs r2, #2 80029c8: 4013 ands r3, r2 80029ca: 603b str r3, [r7, #0] 80029cc: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 80029ce: 23a0 movs r3, #160 @ 0xa0 80029d0: 05db lsls r3, r3, #23 80029d2: 2200 movs r2, #0 80029d4: 21e0 movs r1, #224 @ 0xe0 80029d6: 0018 movs r0, r3 80029d8: f000 ff0c bl 80037f4 <HAL_GPIO_WritePin> /*Configure GPIO pins : PA5 PA6 PA7 */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 80029dc: 193b adds r3, r7, r4 80029de: 22e0 movs r2, #224 @ 0xe0 80029e0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80029e2: 193b adds r3, r7, r4 80029e4: 2201 movs r2, #1 80029e6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80029e8: 193b adds r3, r7, r4 80029ea: 2200 movs r2, #0 80029ec: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80029ee: 193b adds r3, r7, r4 80029f0: 2200 movs r2, #0 80029f2: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80029f4: 193a adds r2, r7, r4 80029f6: 23a0 movs r3, #160 @ 0xa0 80029f8: 05db lsls r3, r3, #23 80029fa: 0011 movs r1, r2 80029fc: 0018 movs r0, r3 80029fe: f000 fd95 bl 800352c <HAL_GPIO_Init> /*Configure GPIO pin : PB2 */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8002a02: 193b adds r3, r7, r4 8002a04: 2204 movs r2, #4 8002a06: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002a08: 193b adds r3, r7, r4 8002a0a: 2200 movs r2, #0 8002a0c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002a0e: 193b adds r3, r7, r4 8002a10: 2200 movs r2, #0 8002a12: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002a14: 193b adds r3, r7, r4 8002a16: 4a13 ldr r2, [pc, #76] @ (8002a64 <MX_GPIO_Init+0xf4>) 8002a18: 0019 movs r1, r3 8002a1a: 0010 movs r0, r2 8002a1c: f000 fd86 bl 800352c <HAL_GPIO_Init> /*Configure GPIO pins : PA8 PA9 PA10 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; 8002a20: 0021 movs r1, r4 8002a22: 187b adds r3, r7, r1 8002a24: 22e0 movs r2, #224 @ 0xe0 8002a26: 00d2 lsls r2, r2, #3 8002a28: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8002a2a: 187b adds r3, r7, r1 8002a2c: 2284 movs r2, #132 @ 0x84 8002a2e: 0392 lsls r2, r2, #14 8002a30: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002a32: 187b adds r3, r7, r1 8002a34: 2201 movs r2, #1 8002a36: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002a38: 187a adds r2, r7, r1 8002a3a: 23a0 movs r3, #160 @ 0xa0 8002a3c: 05db lsls r3, r3, #23 8002a3e: 0011 movs r1, r2 8002a40: 0018 movs r0, r3 8002a42: f000 fd73 bl 800352c <HAL_GPIO_Init> /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0); 8002a46: 2200 movs r2, #0 8002a48: 2100 movs r1, #0 8002a4a: 2007 movs r0, #7 8002a4c: f000 fcd2 bl 80033f4 <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(EXTI4_15_IRQn); 8002a50: 2007 movs r0, #7 8002a52: f000 fce4 bl 800341e <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8002a56: 46c0 nop @ (mov r8, r8) 8002a58: 46bd mov sp, r7 8002a5a: b009 add sp, #36 @ 0x24 8002a5c: bd90 pop {r4, r7, pc} 8002a5e: 46c0 nop @ (mov r8, r8) 8002a60: 40021000 .word 0x40021000 8002a64: 50000400 .word 0x50000400 08002a68 <Signal_square>: /* USER CODE BEGIN 4 */ void Signal_square(uint16_t *msg_spi, uint8_t n) { 8002a68: b580 push {r7, lr} 8002a6a: b082 sub sp, #8 8002a6c: af00 add r7, sp, #0 8002a6e: 6078 str r0, [r7, #4] 8002a70: 000a movs r2, r1 8002a72: 1cfb adds r3, r7, #3 8002a74: 701a strb r2, [r3, #0] static uint8_t i = 0; while (!(SPI1->SR & 2)) {} 8002a76: 46c0 nop @ (mov r8, r8) 8002a78: 4b19 ldr r3, [pc, #100] @ (8002ae0 <Signal_square+0x78>) 8002a7a: 689b ldr r3, [r3, #8] 8002a7c: 2202 movs r2, #2 8002a7e: 4013 ands r3, r2 8002a80: d0fa beq.n 8002a78 <Signal_square+0x10> SPI1->CR1 |= 0x0040; 8002a82: 4b17 ldr r3, [pc, #92] @ (8002ae0 <Signal_square+0x78>) 8002a84: 681a ldr r2, [r3, #0] 8002a86: 4b16 ldr r3, [pc, #88] @ (8002ae0 <Signal_square+0x78>) 8002a88: 2140 movs r1, #64 @ 0x40 8002a8a: 430a orrs r2, r1 8002a8c: 601a str r2, [r3, #0] SPI1->DR = msg_spi[i]; 8002a8e: 4b15 ldr r3, [pc, #84] @ (8002ae4 <Signal_square+0x7c>) 8002a90: 781b ldrb r3, [r3, #0] 8002a92: 005b lsls r3, r3, #1 8002a94: 687a ldr r2, [r7, #4] 8002a96: 18d3 adds r3, r2, r3 8002a98: 881a ldrh r2, [r3, #0] 8002a9a: 4b11 ldr r3, [pc, #68] @ (8002ae0 <Signal_square+0x78>) 8002a9c: 60da str r2, [r3, #12] i = (i + 1) % n; 8002a9e: 4b11 ldr r3, [pc, #68] @ (8002ae4 <Signal_square+0x7c>) 8002aa0: 781b ldrb r3, [r3, #0] 8002aa2: 1c5a adds r2, r3, #1 8002aa4: 1cfb adds r3, r7, #3 8002aa6: 781b ldrb r3, [r3, #0] 8002aa8: 0019 movs r1, r3 8002aaa: 0010 movs r0, r2 8002aac: f7fd fc9a bl 80003e4 <__aeabi_idivmod> 8002ab0: 000b movs r3, r1 8002ab2: b2da uxtb r2, r3 8002ab4: 4b0b ldr r3, [pc, #44] @ (8002ae4 <Signal_square+0x7c>) 8002ab6: 701a strb r2, [r3, #0] while (SPI1->SR & 0x80) {} 8002ab8: 46c0 nop @ (mov r8, r8) 8002aba: 4b09 ldr r3, [pc, #36] @ (8002ae0 <Signal_square+0x78>) 8002abc: 689b ldr r3, [r3, #8] 8002abe: 2280 movs r2, #128 @ 0x80 8002ac0: 4013 ands r3, r2 8002ac2: d1fa bne.n 8002aba <Signal_square+0x52> // Désactive SPI (SPE = 0) -> fait remonter NSS SPI1->CR1 &= ~0x0040; 8002ac4: 4b06 ldr r3, [pc, #24] @ (8002ae0 <Signal_square+0x78>) 8002ac6: 681a ldr r2, [r3, #0] 8002ac8: 4b05 ldr r3, [pc, #20] @ (8002ae0 <Signal_square+0x78>) 8002aca: 2140 movs r1, #64 @ 0x40 8002acc: 438a bics r2, r1 8002ace: 601a str r2, [r3, #0] // Petit délai entre transmissions HAL_Delay(10); // tu peux ajuster (en ms) 8002ad0: 200a movs r0, #10 8002ad2: f000 fbbf bl 8003254 <HAL_Delay> } 8002ad6: 46c0 nop @ (mov r8, r8) 8002ad8: 46bd mov sp, r7 8002ada: b002 add sp, #8 8002adc: bd80 pop {r7, pc} 8002ade: 46c0 nop @ (mov r8, r8) 8002ae0: 40013000 .word 0x40013000 8002ae4: 200000fe .word 0x200000fe 08002ae8 <Signal_triangle>: void Signal_triangle(uint8_t *default_bits, uint8_t *bits, uint8_t n, uint8_t i) { 8002ae8: b580 push {r7, lr} 8002aea: b086 sub sp, #24 8002aec: af00 add r7, sp, #0 8002aee: 60f8 str r0, [r7, #12] 8002af0: 60b9 str r1, [r7, #8] 8002af2: 0019 movs r1, r3 8002af4: 1dfb adds r3, r7, #7 8002af6: 701a strb r2, [r3, #0] 8002af8: 1dbb adds r3, r7, #6 8002afa: 1c0a adds r2, r1, #0 8002afc: 701a strb r2, [r3, #0] uint8_t value = 0; 8002afe: 2317 movs r3, #23 8002b00: 18fb adds r3, r7, r3 8002b02: 2200 movs r2, #0 8002b04: 701a strb r2, [r3, #0] uint8_t mid = 0; 8002b06: 2316 movs r3, #22 8002b08: 18fb adds r3, r7, r3 8002b0a: 2200 movs r2, #0 8002b0c: 701a strb r2, [r3, #0] if (n%2) 8002b0e: 1dfb adds r3, r7, #7 8002b10: 781b ldrb r3, [r3, #0] 8002b12: 2201 movs r2, #1 8002b14: 4013 ands r3, r2 8002b16: b2db uxtb r3, r3 8002b18: 2b00 cmp r3, #0 8002b1a: d00b beq.n 8002b34 <Signal_triangle+0x4c> { mid = (n+1)/2; 8002b1c: 1dfb adds r3, r7, #7 8002b1e: 781b ldrb r3, [r3, #0] 8002b20: 3301 adds r3, #1 8002b22: 2b00 cmp r3, #0 8002b24: da00 bge.n 8002b28 <Signal_triangle+0x40> 8002b26: 3301 adds r3, #1 8002b28: 105b asrs r3, r3, #1 8002b2a: 001a movs r2, r3 8002b2c: 2316 movs r3, #22 8002b2e: 18fb adds r3, r7, r3 8002b30: 701a strb r2, [r3, #0] 8002b32: e005 b.n 8002b40 <Signal_triangle+0x58> } else { mid = n/2; 8002b34: 2316 movs r3, #22 8002b36: 18fb adds r3, r7, r3 8002b38: 1dfa adds r2, r7, #7 8002b3a: 7812 ldrb r2, [r2, #0] 8002b3c: 0852 lsrs r2, r2, #1 8002b3e: 701a strb r2, [r3, #0] } while (!(SPI1->SR & 2)) {} 8002b40: 46c0 nop @ (mov r8, r8) 8002b42: 4b33 ldr r3, [pc, #204] @ (8002c10 <Signal_triangle+0x128>) 8002b44: 689b ldr r3, [r3, #8] 8002b46: 2202 movs r2, #2 8002b48: 4013 ands r3, r2 8002b4a: d0fa beq.n 8002b42 <Signal_triangle+0x5a> SPI1->CR1 |= 0x0040; 8002b4c: 4b30 ldr r3, [pc, #192] @ (8002c10 <Signal_triangle+0x128>) 8002b4e: 681a ldr r2, [r3, #0] 8002b50: 4b2f ldr r3, [pc, #188] @ (8002c10 <Signal_triangle+0x128>) 8002b52: 2140 movs r1, #64 @ 0x40 8002b54: 430a orrs r2, r1 8002b56: 601a str r2, [r3, #0] if(i<= mid) 8002b58: 1dba adds r2, r7, #6 8002b5a: 2116 movs r1, #22 8002b5c: 187b adds r3, r7, r1 8002b5e: 7812 ldrb r2, [r2, #0] 8002b60: 781b ldrb r3, [r3, #0] 8002b62: 429a cmp r2, r3 8002b64: d810 bhi.n 8002b88 <Signal_triangle+0xa0> value = 255*i/mid; 8002b66: 1dbb adds r3, r7, #6 8002b68: 781a ldrb r2, [r3, #0] 8002b6a: 0013 movs r3, r2 8002b6c: 021b lsls r3, r3, #8 8002b6e: 1a9a subs r2, r3, r2 8002b70: 187b adds r3, r7, r1 8002b72: 781b ldrb r3, [r3, #0] 8002b74: 0019 movs r1, r3 8002b76: 0010 movs r0, r2 8002b78: f7fd fb4e bl 8000218 <__divsi3> 8002b7c: 0003 movs r3, r0 8002b7e: 001a movs r2, r3 8002b80: 2317 movs r3, #23 8002b82: 18fb adds r3, r7, r3 8002b84: 701a strb r2, [r3, #0] 8002b86: e01a b.n 8002bbe <Signal_triangle+0xd6> else if(i > mid) 8002b88: 1dba adds r2, r7, #6 8002b8a: 2116 movs r1, #22 8002b8c: 187b adds r3, r7, r1 8002b8e: 7812 ldrb r2, [r2, #0] 8002b90: 781b ldrb r3, [r3, #0] 8002b92: 429a cmp r2, r3 8002b94: d913 bls.n 8002bbe <Signal_triangle+0xd6> { value = 255*(2*mid - i)/mid; 8002b96: 187b adds r3, r7, r1 8002b98: 781b ldrb r3, [r3, #0] 8002b9a: 005a lsls r2, r3, #1 8002b9c: 1dbb adds r3, r7, #6 8002b9e: 781b ldrb r3, [r3, #0] 8002ba0: 1ad2 subs r2, r2, r3 8002ba2: 0013 movs r3, r2 8002ba4: 021b lsls r3, r3, #8 8002ba6: 1a9a subs r2, r3, r2 8002ba8: 187b adds r3, r7, r1 8002baa: 781b ldrb r3, [r3, #0] 8002bac: 0019 movs r1, r3 8002bae: 0010 movs r0, r2 8002bb0: f7fd fb32 bl 8000218 <__divsi3> 8002bb4: 0003 movs r3, r0 8002bb6: 001a movs r2, r3 8002bb8: 2317 movs r3, #23 8002bba: 18fb adds r3, r7, r3 8002bbc: 701a strb r2, [r3, #0] } dec_to_bin(value, bits); 8002bbe: 68ba ldr r2, [r7, #8] 8002bc0: 2317 movs r3, #23 8002bc2: 18fb adds r3, r7, r3 8002bc4: 781b ldrb r3, [r3, #0] 8002bc6: 0011 movs r1, r2 8002bc8: 0018 movs r0, r3 8002bca: f000 f8b5 bl 8002d38 <dec_to_bin> copy_in_vector(bits, default_bits); 8002bce: 68fa ldr r2, [r7, #12] 8002bd0: 68bb ldr r3, [r7, #8] 8002bd2: 0011 movs r1, r2 8002bd4: 0018 movs r0, r3 8002bd6: f000 f8d4 bl 8002d82 <copy_in_vector> SPI1->DR = bin_to_dec(default_bits); 8002bda: 68fb ldr r3, [r7, #12] 8002bdc: 0018 movs r0, r3 8002bde: f000 f8ed bl 8002dbc <bin_to_dec> 8002be2: 0003 movs r3, r0 8002be4: 001a movs r2, r3 8002be6: 4b0a ldr r3, [pc, #40] @ (8002c10 <Signal_triangle+0x128>) 8002be8: 60da str r2, [r3, #12] while (SPI1->SR & 0x80) {} 8002bea: 46c0 nop @ (mov r8, r8) 8002bec: 4b08 ldr r3, [pc, #32] @ (8002c10 <Signal_triangle+0x128>) 8002bee: 689b ldr r3, [r3, #8] 8002bf0: 2280 movs r2, #128 @ 0x80 8002bf2: 4013 ands r3, r2 8002bf4: d1fa bne.n 8002bec <Signal_triangle+0x104> SPI1->CR1 &= ~0x0040; 8002bf6: 4b06 ldr r3, [pc, #24] @ (8002c10 <Signal_triangle+0x128>) 8002bf8: 681a ldr r2, [r3, #0] 8002bfa: 4b05 ldr r3, [pc, #20] @ (8002c10 <Signal_triangle+0x128>) 8002bfc: 2140 movs r1, #64 @ 0x40 8002bfe: 438a bics r2, r1 8002c00: 601a str r2, [r3, #0] HAL_Delay(10); 8002c02: 200a movs r0, #10 8002c04: f000 fb26 bl 8003254 <HAL_Delay> } 8002c08: 46c0 nop @ (mov r8, r8) 8002c0a: 46bd mov sp, r7 8002c0c: b006 add sp, #24 8002c0e: bd80 pop {r7, pc} 8002c10: 40013000 .word 0x40013000 08002c14 <Signal_sine>: void Signal_sine(uint8_t *default_bits, uint8_t *bits, uint8_t n, uint8_t i) { 8002c14: b5b0 push {r4, r5, r7, lr} 8002c16: b086 sub sp, #24 8002c18: af00 add r7, sp, #0 8002c1a: 60f8 str r0, [r7, #12] 8002c1c: 60b9 str r1, [r7, #8] 8002c1e: 0019 movs r1, r3 8002c20: 1dfb adds r3, r7, #7 8002c22: 701a strb r2, [r3, #0] 8002c24: 1dbb adds r3, r7, #6 8002c26: 1c0a adds r2, r1, #0 8002c28: 701a strb r2, [r3, #0] uint8_t value = 0; 8002c2a: 2317 movs r3, #23 8002c2c: 18fb adds r3, r7, r3 8002c2e: 2200 movs r2, #0 8002c30: 701a strb r2, [r3, #0] float angle = 0; 8002c32: 2300 movs r3, #0 8002c34: 613b str r3, [r7, #16] while (!(SPI1->SR & 2)) {} 8002c36: 46c0 nop @ (mov r8, r8) 8002c38: 4b3a ldr r3, [pc, #232] @ (8002d24 <Signal_sine+0x110>) 8002c3a: 689b ldr r3, [r3, #8] 8002c3c: 2202 movs r2, #2 8002c3e: 4013 ands r3, r2 8002c40: d0fa beq.n 8002c38 <Signal_sine+0x24> SPI1->CR1 |= 0x0040; 8002c42: 4b38 ldr r3, [pc, #224] @ (8002d24 <Signal_sine+0x110>) 8002c44: 681a ldr r2, [r3, #0] 8002c46: 4b37 ldr r3, [pc, #220] @ (8002d24 <Signal_sine+0x110>) 8002c48: 2140 movs r1, #64 @ 0x40 8002c4a: 430a orrs r2, r1 8002c4c: 601a str r2, [r3, #0] angle = (2*PI*i) / (float) n; 8002c4e: 1dbb adds r3, r7, #6 8002c50: 781b ldrb r3, [r3, #0] 8002c52: 0018 movs r0, r3 8002c54: f7ff fb9a bl 800238c <__aeabi_i2d> 8002c58: 4a33 ldr r2, [pc, #204] @ (8002d28 <Signal_sine+0x114>) 8002c5a: 4b34 ldr r3, [pc, #208] @ (8002d2c <Signal_sine+0x118>) 8002c5c: f7fe fc6a bl 8001534 <__aeabi_dmul> 8002c60: 0002 movs r2, r0 8002c62: 000b movs r3, r1 8002c64: 0014 movs r4, r2 8002c66: 001d movs r5, r3 8002c68: 1dfb adds r3, r7, #7 8002c6a: 781b ldrb r3, [r3, #0] 8002c6c: 0018 movs r0, r3 8002c6e: f7fd fc1b bl 80004a8 <__aeabi_ui2f> 8002c72: 1c03 adds r3, r0, #0 8002c74: 1c18 adds r0, r3, #0 8002c76: f7ff fbb7 bl 80023e8 <__aeabi_f2d> 8002c7a: 0002 movs r2, r0 8002c7c: 000b movs r3, r1 8002c7e: 0020 movs r0, r4 8002c80: 0029 movs r1, r5 8002c82: f7fe f81d bl 8000cc0 <__aeabi_ddiv> 8002c86: 0002 movs r2, r0 8002c88: 000b movs r3, r1 8002c8a: 0010 movs r0, r2 8002c8c: 0019 movs r1, r3 8002c8e: f7ff fbf3 bl 8002478 <__aeabi_d2f> 8002c92: 1c03 adds r3, r0, #0 8002c94: 613b str r3, [r7, #16] value = (255/2) * (sin(angle) + 1); 8002c96: 6938 ldr r0, [r7, #16] 8002c98: f7ff fba6 bl 80023e8 <__aeabi_f2d> 8002c9c: 0002 movs r2, r0 8002c9e: 000b movs r3, r1 8002ca0: 0010 movs r0, r2 8002ca2: 0019 movs r1, r3 8002ca4: f001 ff4c bl 8004b40 <sin> 8002ca8: 2200 movs r2, #0 8002caa: 4b21 ldr r3, [pc, #132] @ (8002d30 <Signal_sine+0x11c>) 8002cac: f7fd fc42 bl 8000534 <__aeabi_dadd> 8002cb0: 0002 movs r2, r0 8002cb2: 000b movs r3, r1 8002cb4: 0010 movs r0, r2 8002cb6: 0019 movs r1, r3 8002cb8: 2200 movs r2, #0 8002cba: 4b1e ldr r3, [pc, #120] @ (8002d34 <Signal_sine+0x120>) 8002cbc: f7fe fc3a bl 8001534 <__aeabi_dmul> 8002cc0: 0002 movs r2, r0 8002cc2: 000b movs r3, r1 8002cc4: 2517 movs r5, #23 8002cc6: 197c adds r4, r7, r5 8002cc8: 0010 movs r0, r2 8002cca: 0019 movs r1, r3 8002ccc: f7fd fbce bl 800046c <__aeabi_d2uiz> 8002cd0: 0003 movs r3, r0 8002cd2: 7023 strb r3, [r4, #0] dec_to_bin(value, bits); 8002cd4: 68ba ldr r2, [r7, #8] 8002cd6: 197b adds r3, r7, r5 8002cd8: 781b ldrb r3, [r3, #0] 8002cda: 0011 movs r1, r2 8002cdc: 0018 movs r0, r3 8002cde: f000 f82b bl 8002d38 <dec_to_bin> copy_in_vector(bits, default_bits); 8002ce2: 68fa ldr r2, [r7, #12] 8002ce4: 68bb ldr r3, [r7, #8] 8002ce6: 0011 movs r1, r2 8002ce8: 0018 movs r0, r3 8002cea: f000 f84a bl 8002d82 <copy_in_vector> SPI1->DR = bin_to_dec(default_bits); 8002cee: 68fb ldr r3, [r7, #12] 8002cf0: 0018 movs r0, r3 8002cf2: f000 f863 bl 8002dbc <bin_to_dec> 8002cf6: 0003 movs r3, r0 8002cf8: 001a movs r2, r3 8002cfa: 4b0a ldr r3, [pc, #40] @ (8002d24 <Signal_sine+0x110>) 8002cfc: 60da str r2, [r3, #12] while (SPI1->SR & 0x80) {} 8002cfe: 46c0 nop @ (mov r8, r8) 8002d00: 4b08 ldr r3, [pc, #32] @ (8002d24 <Signal_sine+0x110>) 8002d02: 689b ldr r3, [r3, #8] 8002d04: 2280 movs r2, #128 @ 0x80 8002d06: 4013 ands r3, r2 8002d08: d1fa bne.n 8002d00 <Signal_sine+0xec> SPI1->CR1 &= ~0x0040; 8002d0a: 4b06 ldr r3, [pc, #24] @ (8002d24 <Signal_sine+0x110>) 8002d0c: 681a ldr r2, [r3, #0] 8002d0e: 4b05 ldr r3, [pc, #20] @ (8002d24 <Signal_sine+0x110>) 8002d10: 2140 movs r1, #64 @ 0x40 8002d12: 438a bics r2, r1 8002d14: 601a str r2, [r3, #0] HAL_Delay(10); 8002d16: 200a movs r0, #10 8002d18: f000 fa9c bl 8003254 <HAL_Delay> } 8002d1c: 46c0 nop @ (mov r8, r8) 8002d1e: 46bd mov sp, r7 8002d20: b006 add sp, #24 8002d22: bdb0 pop {r4, r5, r7, pc} 8002d24: 40013000 .word 0x40013000 8002d28: 54442d18 .word 0x54442d18 8002d2c: 401921fb .word 0x401921fb 8002d30: 3ff00000 .word 0x3ff00000 8002d34: 405fc000 .word 0x405fc000 08002d38 <dec_to_bin>: void dec_to_bin(uint8_t value, uint8_t *bits) { 8002d38: b580 push {r7, lr} 8002d3a: b084 sub sp, #16 8002d3c: af00 add r7, sp, #0 8002d3e: 0002 movs r2, r0 8002d40: 6039 str r1, [r7, #0] 8002d42: 1dfb adds r3, r7, #7 8002d44: 701a strb r2, [r3, #0] for (int i = 7; i >= 0; i--) 8002d46: 2307 movs r3, #7 8002d48: 60fb str r3, [r7, #12] 8002d4a: e012 b.n 8002d72 <dec_to_bin+0x3a> { bits[7 - i] = (value & (1 << i)) ? 1 : 0; 8002d4c: 1dfb adds r3, r7, #7 8002d4e: 781a ldrb r2, [r3, #0] 8002d50: 68fb ldr r3, [r7, #12] 8002d52: 411a asrs r2, r3 8002d54: 0013 movs r3, r2 8002d56: b2da uxtb r2, r3 8002d58: 68fb ldr r3, [r7, #12] 8002d5a: 2107 movs r1, #7 8002d5c: 1acb subs r3, r1, r3 8002d5e: 0019 movs r1, r3 8002d60: 683b ldr r3, [r7, #0] 8002d62: 185b adds r3, r3, r1 8002d64: 2101 movs r1, #1 8002d66: 400a ands r2, r1 8002d68: b2d2 uxtb r2, r2 8002d6a: 701a strb r2, [r3, #0] for (int i = 7; i >= 0; i--) 8002d6c: 68fb ldr r3, [r7, #12] 8002d6e: 3b01 subs r3, #1 8002d70: 60fb str r3, [r7, #12] 8002d72: 68fb ldr r3, [r7, #12] 8002d74: 2b00 cmp r3, #0 8002d76: dae9 bge.n 8002d4c <dec_to_bin+0x14> } } 8002d78: 46c0 nop @ (mov r8, r8) 8002d7a: 46c0 nop @ (mov r8, r8) 8002d7c: 46bd mov sp, r7 8002d7e: b004 add sp, #16 8002d80: bd80 pop {r7, pc} 08002d82 <copy_in_vector>: void copy_in_vector(uint8_t *bits, uint8_t *default_bits) { 8002d82: b580 push {r7, lr} 8002d84: b084 sub sp, #16 8002d86: af00 add r7, sp, #0 8002d88: 6078 str r0, [r7, #4] 8002d8a: 6039 str r1, [r7, #0] for (int i = 0; i <= 7; i++) 8002d8c: 2300 movs r3, #0 8002d8e: 60fb str r3, [r7, #12] 8002d90: e00c b.n 8002dac <copy_in_vector+0x2a> { default_bits[4 + i] = bits[i]; 8002d92: 68fb ldr r3, [r7, #12] 8002d94: 687a ldr r2, [r7, #4] 8002d96: 18d2 adds r2, r2, r3 8002d98: 68fb ldr r3, [r7, #12] 8002d9a: 3304 adds r3, #4 8002d9c: 0019 movs r1, r3 8002d9e: 683b ldr r3, [r7, #0] 8002da0: 185b adds r3, r3, r1 8002da2: 7812 ldrb r2, [r2, #0] 8002da4: 701a strb r2, [r3, #0] for (int i = 0; i <= 7; i++) 8002da6: 68fb ldr r3, [r7, #12] 8002da8: 3301 adds r3, #1 8002daa: 60fb str r3, [r7, #12] 8002dac: 68fb ldr r3, [r7, #12] 8002dae: 2b07 cmp r3, #7 8002db0: ddef ble.n 8002d92 <copy_in_vector+0x10> } } 8002db2: 46c0 nop @ (mov r8, r8) 8002db4: 46c0 nop @ (mov r8, r8) 8002db6: 46bd mov sp, r7 8002db8: b004 add sp, #16 8002dba: bd80 pop {r7, pc} 08002dbc <bin_to_dec>: uint16_t bin_to_dec(uint8_t *bits) { 8002dbc: b580 push {r7, lr} 8002dbe: b084 sub sp, #16 8002dc0: af00 add r7, sp, #0 8002dc2: 6078 str r0, [r7, #4] uint16_t value = 0; 8002dc4: 230e movs r3, #14 8002dc6: 18fb adds r3, r7, r3 8002dc8: 2200 movs r2, #0 8002dca: 801a strh r2, [r3, #0] for (int i = 0; i < 16; i++) 8002dcc: 2300 movs r3, #0 8002dce: 60bb str r3, [r7, #8] 8002dd0: e017 b.n 8002e02 <bin_to_dec+0x46> { value |= (bits[i] & 0x01) << (15 - i); 8002dd2: 68bb ldr r3, [r7, #8] 8002dd4: 687a ldr r2, [r7, #4] 8002dd6: 18d3 adds r3, r2, r3 8002dd8: 781b ldrb r3, [r3, #0] 8002dda: 001a movs r2, r3 8002ddc: 2301 movs r3, #1 8002dde: 401a ands r2, r3 8002de0: 68bb ldr r3, [r7, #8] 8002de2: 210f movs r1, #15 8002de4: 1acb subs r3, r1, r3 8002de6: 409a lsls r2, r3 8002de8: 0013 movs r3, r2 8002dea: b21a sxth r2, r3 8002dec: 210e movs r1, #14 8002dee: 187b adds r3, r7, r1 8002df0: 2000 movs r0, #0 8002df2: 5e1b ldrsh r3, [r3, r0] 8002df4: 4313 orrs r3, r2 8002df6: b21a sxth r2, r3 8002df8: 187b adds r3, r7, r1 8002dfa: 801a strh r2, [r3, #0] for (int i = 0; i < 16; i++) 8002dfc: 68bb ldr r3, [r7, #8] 8002dfe: 3301 adds r3, #1 8002e00: 60bb str r3, [r7, #8] 8002e02: 68bb ldr r3, [r7, #8] 8002e04: 2b0f cmp r3, #15 8002e06: dde4 ble.n 8002dd2 <bin_to_dec+0x16> } return value; 8002e08: 230e movs r3, #14 8002e0a: 18fb adds r3, r7, r3 8002e0c: 881b ldrh r3, [r3, #0] } 8002e0e: 0018 movs r0, r3 8002e10: 46bd mov sp, r7 8002e12: b004 add sp, #16 8002e14: bd80 pop {r7, pc} ... 08002e18 <HAL_GPIO_EXTI_Falling_Callback>: void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) { 8002e18: b580 push {r7, lr} 8002e1a: b082 sub sp, #8 8002e1c: af00 add r7, sp, #0 8002e1e: 0002 movs r2, r0 8002e20: 1dbb adds r3, r7, #6 8002e22: 801a strh r2, [r3, #0] if(GPIO_Pin == GPIO_PIN_8) 8002e24: 1dbb adds r3, r7, #6 8002e26: 881a ldrh r2, [r3, #0] 8002e28: 2380 movs r3, #128 @ 0x80 8002e2a: 005b lsls r3, r3, #1 8002e2c: 429a cmp r2, r3 8002e2e: d102 bne.n 8002e36 <HAL_GPIO_EXTI_Falling_Callback+0x1e> { flag_change_signal = 1; 8002e30: 4b0c ldr r3, [pc, #48] @ (8002e64 <HAL_GPIO_EXTI_Falling_Callback+0x4c>) 8002e32: 2201 movs r2, #1 8002e34: 701a strb r2, [r3, #0] } if(GPIO_Pin == GPIO_PIN_9) 8002e36: 1dbb adds r3, r7, #6 8002e38: 881a ldrh r2, [r3, #0] 8002e3a: 2380 movs r3, #128 @ 0x80 8002e3c: 009b lsls r3, r3, #2 8002e3e: 429a cmp r2, r3 8002e40: d102 bne.n 8002e48 <HAL_GPIO_EXTI_Falling_Callback+0x30> { flag_freq_decrease = 1; 8002e42: 4b09 ldr r3, [pc, #36] @ (8002e68 <HAL_GPIO_EXTI_Falling_Callback+0x50>) 8002e44: 2201 movs r2, #1 8002e46: 701a strb r2, [r3, #0] } if(GPIO_Pin == GPIO_PIN_10) 8002e48: 1dbb adds r3, r7, #6 8002e4a: 881a ldrh r2, [r3, #0] 8002e4c: 2380 movs r3, #128 @ 0x80 8002e4e: 00db lsls r3, r3, #3 8002e50: 429a cmp r2, r3 8002e52: d102 bne.n 8002e5a <HAL_GPIO_EXTI_Falling_Callback+0x42> { flag_freq_increase = 1; 8002e54: 4b05 ldr r3, [pc, #20] @ (8002e6c <HAL_GPIO_EXTI_Falling_Callback+0x54>) 8002e56: 2201 movs r2, #1 8002e58: 701a strb r2, [r3, #0] } } 8002e5a: 46c0 nop @ (mov r8, r8) 8002e5c: 46bd mov sp, r7 8002e5e: b002 add sp, #8 8002e60: bd80 pop {r7, pc} 8002e62: 46c0 nop @ (mov r8, r8) 8002e64: 200000fa .word 0x200000fa 8002e68: 200000fc .word 0x200000fc 8002e6c: 200000fb .word 0x200000fb 08002e70 <HAL_TIM_PeriodElapsedCallback>: void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8002e70: b580 push {r7, lr} 8002e72: b082 sub sp, #8 8002e74: af00 add r7, sp, #0 8002e76: 6078 str r0, [r7, #4] if (htim->Instance == TIM17) 8002e78: 687b ldr r3, [r7, #4] 8002e7a: 681b ldr r3, [r3, #0] 8002e7c: 4a04 ldr r2, [pc, #16] @ (8002e90 <HAL_TIM_PeriodElapsedCallback+0x20>) 8002e7e: 4293 cmp r3, r2 8002e80: d102 bne.n 8002e88 <HAL_TIM_PeriodElapsedCallback+0x18> { flag_tim17_overflow = 1; 8002e82: 4b04 ldr r3, [pc, #16] @ (8002e94 <HAL_TIM_PeriodElapsedCallback+0x24>) 8002e84: 2201 movs r2, #1 8002e86: 701a strb r2, [r3, #0] } } 8002e88: 46c0 nop @ (mov r8, r8) 8002e8a: 46bd mov sp, r7 8002e8c: b002 add sp, #8 8002e8e: bd80 pop {r7, pc} 8002e90: 40014800 .word 0x40014800 8002e94: 200000fd .word 0x200000fd 08002e98 <Error_Handler>: /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002e98: b580 push {r7, lr} 8002e9a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8002e9c: b672 cpsid i } 8002e9e: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8002ea0: 46c0 nop @ (mov r8, r8) 8002ea2: e7fd b.n 8002ea0 <Error_Handler+0x8> 08002ea4 <HAL_MspInit>: /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002ea4: b580 push {r7, lr} 8002ea6: b082 sub sp, #8 8002ea8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002eaa: 4b0f ldr r3, [pc, #60] @ (8002ee8 <HAL_MspInit+0x44>) 8002eac: 6c1a ldr r2, [r3, #64] @ 0x40 8002eae: 4b0e ldr r3, [pc, #56] @ (8002ee8 <HAL_MspInit+0x44>) 8002eb0: 2101 movs r1, #1 8002eb2: 430a orrs r2, r1 8002eb4: 641a str r2, [r3, #64] @ 0x40 8002eb6: 4b0c ldr r3, [pc, #48] @ (8002ee8 <HAL_MspInit+0x44>) 8002eb8: 6c1b ldr r3, [r3, #64] @ 0x40 8002eba: 2201 movs r2, #1 8002ebc: 4013 ands r3, r2 8002ebe: 607b str r3, [r7, #4] 8002ec0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8002ec2: 4b09 ldr r3, [pc, #36] @ (8002ee8 <HAL_MspInit+0x44>) 8002ec4: 6bda ldr r2, [r3, #60] @ 0x3c 8002ec6: 4b08 ldr r3, [pc, #32] @ (8002ee8 <HAL_MspInit+0x44>) 8002ec8: 2180 movs r1, #128 @ 0x80 8002eca: 0549 lsls r1, r1, #21 8002ecc: 430a orrs r2, r1 8002ece: 63da str r2, [r3, #60] @ 0x3c 8002ed0: 4b05 ldr r3, [pc, #20] @ (8002ee8 <HAL_MspInit+0x44>) 8002ed2: 6bda ldr r2, [r3, #60] @ 0x3c 8002ed4: 2380 movs r3, #128 @ 0x80 8002ed6: 055b lsls r3, r3, #21 8002ed8: 4013 ands r3, r2 8002eda: 603b str r3, [r7, #0] 8002edc: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002ede: 46c0 nop @ (mov r8, r8) 8002ee0: 46bd mov sp, r7 8002ee2: b002 add sp, #8 8002ee4: bd80 pop {r7, pc} 8002ee6: 46c0 nop @ (mov r8, r8) 8002ee8: 40021000 .word 0x40021000 08002eec <HAL_SPI_MspInit>: * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8002eec: b590 push {r4, r7, lr} 8002eee: b08b sub sp, #44 @ 0x2c 8002ef0: af00 add r7, sp, #0 8002ef2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002ef4: 2414 movs r4, #20 8002ef6: 193b adds r3, r7, r4 8002ef8: 0018 movs r0, r3 8002efa: 2314 movs r3, #20 8002efc: 001a movs r2, r3 8002efe: 2100 movs r1, #0 8002f00: f001 fdf2 bl 8004ae8 <memset> if(hspi->Instance==SPI1) 8002f04: 687b ldr r3, [r7, #4] 8002f06: 681b ldr r3, [r3, #0] 8002f08: 4a3d ldr r2, [pc, #244] @ (8003000 <HAL_SPI_MspInit+0x114>) 8002f0a: 4293 cmp r3, r2 8002f0c: d173 bne.n 8002ff6 <HAL_SPI_MspInit+0x10a> { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8002f0e: 4b3d ldr r3, [pc, #244] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f10: 6c1a ldr r2, [r3, #64] @ 0x40 8002f12: 4b3c ldr r3, [pc, #240] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f14: 2180 movs r1, #128 @ 0x80 8002f16: 0149 lsls r1, r1, #5 8002f18: 430a orrs r2, r1 8002f1a: 641a str r2, [r3, #64] @ 0x40 8002f1c: 4b39 ldr r3, [pc, #228] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f1e: 6c1a ldr r2, [r3, #64] @ 0x40 8002f20: 2380 movs r3, #128 @ 0x80 8002f22: 015b lsls r3, r3, #5 8002f24: 4013 ands r3, r2 8002f26: 613b str r3, [r7, #16] 8002f28: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002f2a: 4b36 ldr r3, [pc, #216] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f2c: 6b5a ldr r2, [r3, #52] @ 0x34 8002f2e: 4b35 ldr r3, [pc, #212] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f30: 2101 movs r1, #1 8002f32: 430a orrs r2, r1 8002f34: 635a str r2, [r3, #52] @ 0x34 8002f36: 4b33 ldr r3, [pc, #204] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f38: 6b5b ldr r3, [r3, #52] @ 0x34 8002f3a: 2201 movs r2, #1 8002f3c: 4013 ands r3, r2 8002f3e: 60fb str r3, [r7, #12] 8002f40: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002f42: 4b30 ldr r3, [pc, #192] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f44: 6b5a ldr r2, [r3, #52] @ 0x34 8002f46: 4b2f ldr r3, [pc, #188] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f48: 2102 movs r1, #2 8002f4a: 430a orrs r2, r1 8002f4c: 635a str r2, [r3, #52] @ 0x34 8002f4e: 4b2d ldr r3, [pc, #180] @ (8003004 <HAL_SPI_MspInit+0x118>) 8002f50: 6b5b ldr r3, [r3, #52] @ 0x34 8002f52: 2202 movs r2, #2 8002f54: 4013 ands r3, r2 8002f56: 60bb str r3, [r7, #8] 8002f58: 68bb ldr r3, [r7, #8] /**SPI1 GPIO Configuration PA12 [PA10] ------> SPI1_MOSI PA15 ------> SPI1_NSS PB3 ------> SPI1_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_12; 8002f5a: 193b adds r3, r7, r4 8002f5c: 2280 movs r2, #128 @ 0x80 8002f5e: 0152 lsls r2, r2, #5 8002f60: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002f62: 193b adds r3, r7, r4 8002f64: 2202 movs r2, #2 8002f66: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002f68: 193b adds r3, r7, r4 8002f6a: 2200 movs r2, #0 8002f6c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002f6e: 193b adds r3, r7, r4 8002f70: 2200 movs r2, #0 8002f72: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; 8002f74: 193b adds r3, r7, r4 8002f76: 2200 movs r2, #0 8002f78: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002f7a: 193a adds r2, r7, r4 8002f7c: 23a0 movs r3, #160 @ 0xa0 8002f7e: 05db lsls r3, r3, #23 8002f80: 0011 movs r1, r2 8002f82: 0018 movs r0, r3 8002f84: f000 fad2 bl 800352c <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_15; 8002f88: 0021 movs r1, r4 8002f8a: 187b adds r3, r7, r1 8002f8c: 2280 movs r2, #128 @ 0x80 8002f8e: 0212 lsls r2, r2, #8 8002f90: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002f92: 000c movs r4, r1 8002f94: 193b adds r3, r7, r4 8002f96: 2202 movs r2, #2 8002f98: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002f9a: 193b adds r3, r7, r4 8002f9c: 2201 movs r2, #1 8002f9e: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002fa0: 193b adds r3, r7, r4 8002fa2: 2200 movs r2, #0 8002fa4: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; 8002fa6: 193b adds r3, r7, r4 8002fa8: 2200 movs r2, #0 8002faa: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002fac: 193a adds r2, r7, r4 8002fae: 23a0 movs r3, #160 @ 0xa0 8002fb0: 05db lsls r3, r3, #23 8002fb2: 0011 movs r1, r2 8002fb4: 0018 movs r0, r3 8002fb6: f000 fab9 bl 800352c <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_3; 8002fba: 0021 movs r1, r4 8002fbc: 187b adds r3, r7, r1 8002fbe: 2208 movs r2, #8 8002fc0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002fc2: 187b adds r3, r7, r1 8002fc4: 2202 movs r2, #2 8002fc6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002fc8: 187b adds r3, r7, r1 8002fca: 2200 movs r2, #0 8002fcc: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002fce: 187b adds r3, r7, r1 8002fd0: 2200 movs r2, #0 8002fd2: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; 8002fd4: 187b adds r3, r7, r1 8002fd6: 2200 movs r2, #0 8002fd8: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002fda: 187b adds r3, r7, r1 8002fdc: 4a0a ldr r2, [pc, #40] @ (8003008 <HAL_SPI_MspInit+0x11c>) 8002fde: 0019 movs r1, r3 8002fe0: 0010 movs r0, r2 8002fe2: f000 faa3 bl 800352c <HAL_GPIO_Init> /* SPI1 interrupt Init */ HAL_NVIC_SetPriority(SPI1_IRQn, 0, 0); 8002fe6: 2200 movs r2, #0 8002fe8: 2100 movs r1, #0 8002fea: 2019 movs r0, #25 8002fec: f000 fa02 bl 80033f4 <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(SPI1_IRQn); 8002ff0: 2019 movs r0, #25 8002ff2: f000 fa14 bl 800341e <HAL_NVIC_EnableIRQ> /* USER CODE END SPI1_MspInit 1 */ } } 8002ff6: 46c0 nop @ (mov r8, r8) 8002ff8: 46bd mov sp, r7 8002ffa: b00b add sp, #44 @ 0x2c 8002ffc: bd90 pop {r4, r7, pc} 8002ffe: 46c0 nop @ (mov r8, r8) 8003000: 40013000 .word 0x40013000 8003004: 40021000 .word 0x40021000 8003008: 50000400 .word 0x50000400 0800300c <HAL_TIM_Base_MspInit>: * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 800300c: b580 push {r7, lr} 800300e: b084 sub sp, #16 8003010: af00 add r7, sp, #0 8003012: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM17) 8003014: 687b ldr r3, [r7, #4] 8003016: 681b ldr r3, [r3, #0] 8003018: 4a0e ldr r2, [pc, #56] @ (8003054 <HAL_TIM_Base_MspInit+0x48>) 800301a: 4293 cmp r3, r2 800301c: d115 bne.n 800304a <HAL_TIM_Base_MspInit+0x3e> { /* USER CODE BEGIN TIM17_MspInit 0 */ /* USER CODE END TIM17_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM17_CLK_ENABLE(); 800301e: 4b0e ldr r3, [pc, #56] @ (8003058 <HAL_TIM_Base_MspInit+0x4c>) 8003020: 6c1a ldr r2, [r3, #64] @ 0x40 8003022: 4b0d ldr r3, [pc, #52] @ (8003058 <HAL_TIM_Base_MspInit+0x4c>) 8003024: 2180 movs r1, #128 @ 0x80 8003026: 02c9 lsls r1, r1, #11 8003028: 430a orrs r2, r1 800302a: 641a str r2, [r3, #64] @ 0x40 800302c: 4b0a ldr r3, [pc, #40] @ (8003058 <HAL_TIM_Base_MspInit+0x4c>) 800302e: 6c1a ldr r2, [r3, #64] @ 0x40 8003030: 2380 movs r3, #128 @ 0x80 8003032: 02db lsls r3, r3, #11 8003034: 4013 ands r3, r2 8003036: 60fb str r3, [r7, #12] 8003038: 68fb ldr r3, [r7, #12] /* TIM17 interrupt Init */ HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0); 800303a: 2200 movs r2, #0 800303c: 2100 movs r1, #0 800303e: 2016 movs r0, #22 8003040: f000 f9d8 bl 80033f4 <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(TIM17_IRQn); 8003044: 2016 movs r0, #22 8003046: f000 f9ea bl 800341e <HAL_NVIC_EnableIRQ> /* USER CODE END TIM17_MspInit 1 */ } } 800304a: 46c0 nop @ (mov r8, r8) 800304c: 46bd mov sp, r7 800304e: b004 add sp, #16 8003050: bd80 pop {r7, pc} 8003052: 46c0 nop @ (mov r8, r8) 8003054: 40014800 .word 0x40014800 8003058: 40021000 .word 0x40021000 0800305c <NMI_Handler>: /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800305c: b580 push {r7, lr} 800305e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8003060: 46c0 nop @ (mov r8, r8) 8003062: e7fd b.n 8003060 <NMI_Handler+0x4> 08003064 <HardFault_Handler>: /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8003064: b580 push {r7, lr} 8003066: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8003068: 46c0 nop @ (mov r8, r8) 800306a: e7fd b.n 8003068 <HardFault_Handler+0x4> 0800306c <SVC_Handler>: /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800306c: b580 push {r7, lr} 800306e: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8003070: 46c0 nop @ (mov r8, r8) 8003072: 46bd mov sp, r7 8003074: bd80 pop {r7, pc} 08003076 <PendSV_Handler>: /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8003076: b580 push {r7, lr} 8003078: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800307a: 46c0 nop @ (mov r8, r8) 800307c: 46bd mov sp, r7 800307e: bd80 pop {r7, pc} 08003080 <SysTick_Handler>: /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8003080: b580 push {r7, lr} 8003082: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8003084: f000 f8ca bl 800321c <HAL_IncTick> /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8003088: 46c0 nop @ (mov r8, r8) 800308a: 46bd mov sp, r7 800308c: bd80 pop {r7, pc} 0800308e <EXTI4_15_IRQHandler>: /** * @brief This function handles EXTI line 4 to 15 interrupts. */ void EXTI4_15_IRQHandler(void) { 800308e: b580 push {r7, lr} 8003090: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI4_15_IRQn 0 */ /* USER CODE END EXTI4_15_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 8003092: 2380 movs r3, #128 @ 0x80 8003094: 005b lsls r3, r3, #1 8003096: 0018 movs r0, r3 8003098: f000 fbca bl 8003830 <HAL_GPIO_EXTI_IRQHandler> HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 800309c: 2380 movs r3, #128 @ 0x80 800309e: 009b lsls r3, r3, #2 80030a0: 0018 movs r0, r3 80030a2: f000 fbc5 bl 8003830 <HAL_GPIO_EXTI_IRQHandler> HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 80030a6: 2380 movs r3, #128 @ 0x80 80030a8: 00db lsls r3, r3, #3 80030aa: 0018 movs r0, r3 80030ac: f000 fbc0 bl 8003830 <HAL_GPIO_EXTI_IRQHandler> /* USER CODE BEGIN EXTI4_15_IRQn 1 */ /* USER CODE END EXTI4_15_IRQn 1 */ } 80030b0: 46c0 nop @ (mov r8, r8) 80030b2: 46bd mov sp, r7 80030b4: bd80 pop {r7, pc} ... 080030b8 <TIM17_IRQHandler>: /** * @brief This function handles TIM17 global interrupt. */ void TIM17_IRQHandler(void) { 80030b8: b580 push {r7, lr} 80030ba: af00 add r7, sp, #0 /* USER CODE BEGIN TIM17_IRQn 0 */ // __HAL_TIM_CLEAR_IT(&htim17, TIM_IT_UPDATE); // flag_ready_send = 1; /* USER CODE END TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim17); 80030bc: 4b03 ldr r3, [pc, #12] @ (80030cc <TIM17_IRQHandler+0x14>) 80030be: 0018 movs r0, r3 80030c0: f001 fb4e bl 8004760 <HAL_TIM_IRQHandler> /* USER CODE BEGIN TIM17_IRQn 1 */ /* USER CODE END TIM17_IRQn 1 */ } 80030c4: 46c0 nop @ (mov r8, r8) 80030c6: 46bd mov sp, r7 80030c8: bd80 pop {r7, pc} 80030ca: 46c0 nop @ (mov r8, r8) 80030cc: 200000a0 .word 0x200000a0 080030d0 <SPI1_IRQHandler>: /** * @brief This function handles SPI1 global interrupt. */ void SPI1_IRQHandler(void) { 80030d0: b580 push {r7, lr} 80030d2: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_IRQn 0 */ /* USER CODE END SPI1_IRQn 0 */ HAL_SPI_IRQHandler(&hspi1); 80030d4: 4b03 ldr r3, [pc, #12] @ (80030e4 <SPI1_IRQHandler+0x14>) 80030d6: 0018 movs r0, r3 80030d8: f001 f97a bl 80043d0 <HAL_SPI_IRQHandler> /* USER CODE BEGIN SPI1_IRQn 1 */ /* USER CODE END SPI1_IRQn 1 */ } 80030dc: 46c0 nop @ (mov r8, r8) 80030de: 46bd mov sp, r7 80030e0: bd80 pop {r7, pc} 80030e2: 46c0 nop @ (mov r8, r8) 80030e4: 2000003c .word 0x2000003c 080030e8 <SystemInit>: * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 80030e8: b580 push {r7, lr} 80030ea: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ #endif /* USER_VECT_TAB_ADDRESS */ } 80030ec: 46c0 nop @ (mov r8, r8) 80030ee: 46bd mov sp, r7 80030f0: bd80 pop {r7, pc} ... 080030f4 <Reset_Handler>: .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80030f4: 480d ldr r0, [pc, #52] @ (800312c <LoopForever+0x2>) mov sp, r0 /* set stack pointer */ 80030f6: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80030f8: f7ff fff6 bl 80030e8 <SystemInit> /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80030fc: 480c ldr r0, [pc, #48] @ (8003130 <LoopForever+0x6>) ldr r1, =_edata 80030fe: 490d ldr r1, [pc, #52] @ (8003134 <LoopForever+0xa>) ldr r2, =_sidata 8003100: 4a0d ldr r2, [pc, #52] @ (8003138 <LoopForever+0xe>) movs r3, #0 8003102: 2300 movs r3, #0 b LoopCopyDataInit 8003104: e002 b.n 800310c <LoopCopyDataInit> 08003106 <CopyDataInit>: CopyDataInit: ldr r4, [r2, r3] 8003106: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8003108: 50c4 str r4, [r0, r3] adds r3, r3, #4 800310a: 3304 adds r3, #4 0800310c <LoopCopyDataInit>: LoopCopyDataInit: adds r4, r0, r3 800310c: 18c4 adds r4, r0, r3 cmp r4, r1 800310e: 428c cmp r4, r1 bcc CopyDataInit 8003110: d3f9 bcc.n 8003106 <CopyDataInit> /* Zero fill the bss segment. */ ldr r2, =_sbss 8003112: 4a0a ldr r2, [pc, #40] @ (800313c <LoopForever+0x12>) ldr r4, =_ebss 8003114: 4c0a ldr r4, [pc, #40] @ (8003140 <LoopForever+0x16>) movs r3, #0 8003116: 2300 movs r3, #0 b LoopFillZerobss 8003118: e001 b.n 800311e <LoopFillZerobss> 0800311a <FillZerobss>: FillZerobss: str r3, [r2] 800311a: 6013 str r3, [r2, #0] adds r2, r2, #4 800311c: 3204 adds r2, #4 0800311e <LoopFillZerobss>: LoopFillZerobss: cmp r2, r4 800311e: 42a2 cmp r2, r4 bcc FillZerobss 8003120: d3fb bcc.n 800311a <FillZerobss> /* Call static constructors */ bl __libc_init_array 8003122: f001 fce9 bl 8004af8 <__libc_init_array> /* Call the application s entry point.*/ bl main 8003126: f7ff fa47 bl 80025b8 <main> 0800312a <LoopForever>: LoopForever: b LoopForever 800312a: e7fe b.n 800312a <LoopForever> ldr r0, =_estack 800312c: 20002000 .word 0x20002000 ldr r0, =_sdata 8003130: 20000000 .word 0x20000000 ldr r1, =_edata 8003134: 20000020 .word 0x20000020 ldr r2, =_sidata 8003138: 08005d50 .word 0x08005d50 ldr r2, =_sbss 800313c: 20000020 .word 0x20000020 ldr r4, =_ebss 8003140: 20000104 .word 0x20000104 08003144 <ADC1_IRQHandler>: * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8003144: e7fe b.n 8003144 <ADC1_IRQHandler> ... 08003148 <HAL_Init>: * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8003148: b580 push {r7, lr} 800314a: b082 sub sp, #8 800314c: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800314e: 1dfb adds r3, r7, #7 8003150: 2200 movs r2, #0 8003152: 701a strb r2, [r3, #0] #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8003154: 4b0b ldr r3, [pc, #44] @ (8003184 <HAL_Init+0x3c>) 8003156: 681a ldr r2, [r3, #0] 8003158: 4b0a ldr r3, [pc, #40] @ (8003184 <HAL_Init+0x3c>) 800315a: 2180 movs r1, #128 @ 0x80 800315c: 0049 lsls r1, r1, #1 800315e: 430a orrs r2, r1 8003160: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8003162: 2000 movs r0, #0 8003164: f000 f810 bl 8003188 <HAL_InitTick> 8003168: 1e03 subs r3, r0, #0 800316a: d003 beq.n 8003174 <HAL_Init+0x2c> { status = HAL_ERROR; 800316c: 1dfb adds r3, r7, #7 800316e: 2201 movs r2, #1 8003170: 701a strb r2, [r3, #0] 8003172: e001 b.n 8003178 <HAL_Init+0x30> } else { /* Init the low level hardware */ HAL_MspInit(); 8003174: f7ff fe96 bl 8002ea4 <HAL_MspInit> } /* Return function status */ return status; 8003178: 1dfb adds r3, r7, #7 800317a: 781b ldrb r3, [r3, #0] } 800317c: 0018 movs r0, r3 800317e: 46bd mov sp, r7 8003180: b002 add sp, #8 8003182: bd80 pop {r7, pc} 8003184: 40022000 .word 0x40022000 08003188 <HAL_InitTick>: * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8003188: b590 push {r4, r7, lr} 800318a: b085 sub sp, #20 800318c: af00 add r7, sp, #0 800318e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003190: 230f movs r3, #15 8003192: 18fb adds r3, r7, r3 8003194: 2200 movs r2, #0 8003196: 701a strb r2, [r3, #0] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 8003198: 4b1d ldr r3, [pc, #116] @ (8003210 <HAL_InitTick+0x88>) 800319a: 781b ldrb r3, [r3, #0] 800319c: 2b00 cmp r3, #0 800319e: d02b beq.n 80031f8 <HAL_InitTick+0x70> { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) 80031a0: 4b1c ldr r3, [pc, #112] @ (8003214 <HAL_InitTick+0x8c>) 80031a2: 681c ldr r4, [r3, #0] 80031a4: 4b1a ldr r3, [pc, #104] @ (8003210 <HAL_InitTick+0x88>) 80031a6: 781b ldrb r3, [r3, #0] 80031a8: 0019 movs r1, r3 80031aa: 23fa movs r3, #250 @ 0xfa 80031ac: 0098 lsls r0, r3, #2 80031ae: f7fc ffa9 bl 8000104 <__udivsi3> 80031b2: 0003 movs r3, r0 80031b4: 0019 movs r1, r3 80031b6: 0020 movs r0, r4 80031b8: f7fc ffa4 bl 8000104 <__udivsi3> 80031bc: 0003 movs r3, r0 80031be: 0018 movs r0, r3 80031c0: f000 f93d bl 800343e <HAL_SYSTICK_Config> 80031c4: 1e03 subs r3, r0, #0 80031c6: d112 bne.n 80031ee <HAL_InitTick+0x66> { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80031c8: 687b ldr r3, [r7, #4] 80031ca: 2b03 cmp r3, #3 80031cc: d80a bhi.n 80031e4 <HAL_InitTick+0x5c> { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80031ce: 6879 ldr r1, [r7, #4] 80031d0: 2301 movs r3, #1 80031d2: 425b negs r3, r3 80031d4: 2200 movs r2, #0 80031d6: 0018 movs r0, r3 80031d8: f000 f90c bl 80033f4 <HAL_NVIC_SetPriority> uwTickPrio = TickPriority; 80031dc: 4b0e ldr r3, [pc, #56] @ (8003218 <HAL_InitTick+0x90>) 80031de: 687a ldr r2, [r7, #4] 80031e0: 601a str r2, [r3, #0] 80031e2: e00d b.n 8003200 <HAL_InitTick+0x78> } else { status = HAL_ERROR; 80031e4: 230f movs r3, #15 80031e6: 18fb adds r3, r7, r3 80031e8: 2201 movs r2, #1 80031ea: 701a strb r2, [r3, #0] 80031ec: e008 b.n 8003200 <HAL_InitTick+0x78> } } else { status = HAL_ERROR; 80031ee: 230f movs r3, #15 80031f0: 18fb adds r3, r7, r3 80031f2: 2201 movs r2, #1 80031f4: 701a strb r2, [r3, #0] 80031f6: e003 b.n 8003200 <HAL_InitTick+0x78> } } else { status = HAL_ERROR; 80031f8: 230f movs r3, #15 80031fa: 18fb adds r3, r7, r3 80031fc: 2201 movs r2, #1 80031fe: 701a strb r2, [r3, #0] } /* Return function status */ return status; 8003200: 230f movs r3, #15 8003202: 18fb adds r3, r7, r3 8003204: 781b ldrb r3, [r3, #0] } 8003206: 0018 movs r0, r3 8003208: 46bd mov sp, r7 800320a: b005 add sp, #20 800320c: bd90 pop {r4, r7, pc} 800320e: 46c0 nop @ (mov r8, r8) 8003210: 2000001c .word 0x2000001c 8003214: 20000014 .word 0x20000014 8003218: 20000018 .word 0x20000018 0800321c <HAL_IncTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800321c: b580 push {r7, lr} 800321e: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8003220: 4b05 ldr r3, [pc, #20] @ (8003238 <HAL_IncTick+0x1c>) 8003222: 781b ldrb r3, [r3, #0] 8003224: 001a movs r2, r3 8003226: 4b05 ldr r3, [pc, #20] @ (800323c <HAL_IncTick+0x20>) 8003228: 681b ldr r3, [r3, #0] 800322a: 18d2 adds r2, r2, r3 800322c: 4b03 ldr r3, [pc, #12] @ (800323c <HAL_IncTick+0x20>) 800322e: 601a str r2, [r3, #0] } 8003230: 46c0 nop @ (mov r8, r8) 8003232: 46bd mov sp, r7 8003234: bd80 pop {r7, pc} 8003236: 46c0 nop @ (mov r8, r8) 8003238: 2000001c .word 0x2000001c 800323c: 20000100 .word 0x20000100 08003240 <HAL_GetTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8003240: b580 push {r7, lr} 8003242: af00 add r7, sp, #0 return uwTick; 8003244: 4b02 ldr r3, [pc, #8] @ (8003250 <HAL_GetTick+0x10>) 8003246: 681b ldr r3, [r3, #0] } 8003248: 0018 movs r0, r3 800324a: 46bd mov sp, r7 800324c: bd80 pop {r7, pc} 800324e: 46c0 nop @ (mov r8, r8) 8003250: 20000100 .word 0x20000100 08003254 <HAL_Delay>: * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8003254: b580 push {r7, lr} 8003256: b084 sub sp, #16 8003258: af00 add r7, sp, #0 800325a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800325c: f7ff fff0 bl 8003240 <HAL_GetTick> 8003260: 0003 movs r3, r0 8003262: 60bb str r3, [r7, #8] uint32_t wait = Delay; 8003264: 687b ldr r3, [r7, #4] 8003266: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8003268: 68fb ldr r3, [r7, #12] 800326a: 3301 adds r3, #1 800326c: d005 beq.n 800327a <HAL_Delay+0x26> { wait += (uint32_t)(uwTickFreq); 800326e: 4b0a ldr r3, [pc, #40] @ (8003298 <HAL_Delay+0x44>) 8003270: 781b ldrb r3, [r3, #0] 8003272: 001a movs r2, r3 8003274: 68fb ldr r3, [r7, #12] 8003276: 189b adds r3, r3, r2 8003278: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800327a: 46c0 nop @ (mov r8, r8) 800327c: f7ff ffe0 bl 8003240 <HAL_GetTick> 8003280: 0002 movs r2, r0 8003282: 68bb ldr r3, [r7, #8] 8003284: 1ad3 subs r3, r2, r3 8003286: 68fa ldr r2, [r7, #12] 8003288: 429a cmp r2, r3 800328a: d8f7 bhi.n 800327c <HAL_Delay+0x28> { } } 800328c: 46c0 nop @ (mov r8, r8) 800328e: 46c0 nop @ (mov r8, r8) 8003290: 46bd mov sp, r7 8003292: b004 add sp, #16 8003294: bd80 pop {r7, pc} 8003296: 46c0 nop @ (mov r8, r8) 8003298: 2000001c .word 0x2000001c 0800329c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800329c: b580 push {r7, lr} 800329e: b082 sub sp, #8 80032a0: af00 add r7, sp, #0 80032a2: 0002 movs r2, r0 80032a4: 1dfb adds r3, r7, #7 80032a6: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80032a8: 1dfb adds r3, r7, #7 80032aa: 781b ldrb r3, [r3, #0] 80032ac: 2b7f cmp r3, #127 @ 0x7f 80032ae: d809 bhi.n 80032c4 <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80032b0: 1dfb adds r3, r7, #7 80032b2: 781b ldrb r3, [r3, #0] 80032b4: 001a movs r2, r3 80032b6: 231f movs r3, #31 80032b8: 401a ands r2, r3 80032ba: 4b04 ldr r3, [pc, #16] @ (80032cc <__NVIC_EnableIRQ+0x30>) 80032bc: 2101 movs r1, #1 80032be: 4091 lsls r1, r2 80032c0: 000a movs r2, r1 80032c2: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } 80032c4: 46c0 nop @ (mov r8, r8) 80032c6: 46bd mov sp, r7 80032c8: b002 add sp, #8 80032ca: bd80 pop {r7, pc} 80032cc: e000e100 .word 0xe000e100 080032d0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80032d0: b590 push {r4, r7, lr} 80032d2: b083 sub sp, #12 80032d4: af00 add r7, sp, #0 80032d6: 0002 movs r2, r0 80032d8: 6039 str r1, [r7, #0] 80032da: 1dfb adds r3, r7, #7 80032dc: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80032de: 1dfb adds r3, r7, #7 80032e0: 781b ldrb r3, [r3, #0] 80032e2: 2b7f cmp r3, #127 @ 0x7f 80032e4: d828 bhi.n 8003338 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80032e6: 4a2f ldr r2, [pc, #188] @ (80033a4 <__NVIC_SetPriority+0xd4>) 80032e8: 1dfb adds r3, r7, #7 80032ea: 781b ldrb r3, [r3, #0] 80032ec: b25b sxtb r3, r3 80032ee: 089b lsrs r3, r3, #2 80032f0: 33c0 adds r3, #192 @ 0xc0 80032f2: 009b lsls r3, r3, #2 80032f4: 589b ldr r3, [r3, r2] 80032f6: 1dfa adds r2, r7, #7 80032f8: 7812 ldrb r2, [r2, #0] 80032fa: 0011 movs r1, r2 80032fc: 2203 movs r2, #3 80032fe: 400a ands r2, r1 8003300: 00d2 lsls r2, r2, #3 8003302: 21ff movs r1, #255 @ 0xff 8003304: 4091 lsls r1, r2 8003306: 000a movs r2, r1 8003308: 43d2 mvns r2, r2 800330a: 401a ands r2, r3 800330c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800330e: 683b ldr r3, [r7, #0] 8003310: 019b lsls r3, r3, #6 8003312: 22ff movs r2, #255 @ 0xff 8003314: 401a ands r2, r3 8003316: 1dfb adds r3, r7, #7 8003318: 781b ldrb r3, [r3, #0] 800331a: 0018 movs r0, r3 800331c: 2303 movs r3, #3 800331e: 4003 ands r3, r0 8003320: 00db lsls r3, r3, #3 8003322: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8003324: 481f ldr r0, [pc, #124] @ (80033a4 <__NVIC_SetPriority+0xd4>) 8003326: 1dfb adds r3, r7, #7 8003328: 781b ldrb r3, [r3, #0] 800332a: b25b sxtb r3, r3 800332c: 089b lsrs r3, r3, #2 800332e: 430a orrs r2, r1 8003330: 33c0 adds r3, #192 @ 0xc0 8003332: 009b lsls r3, r3, #2 8003334: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8003336: e031 b.n 800339c <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8003338: 4a1b ldr r2, [pc, #108] @ (80033a8 <__NVIC_SetPriority+0xd8>) 800333a: 1dfb adds r3, r7, #7 800333c: 781b ldrb r3, [r3, #0] 800333e: 0019 movs r1, r3 8003340: 230f movs r3, #15 8003342: 400b ands r3, r1 8003344: 3b08 subs r3, #8 8003346: 089b lsrs r3, r3, #2 8003348: 3306 adds r3, #6 800334a: 009b lsls r3, r3, #2 800334c: 18d3 adds r3, r2, r3 800334e: 3304 adds r3, #4 8003350: 681b ldr r3, [r3, #0] 8003352: 1dfa adds r2, r7, #7 8003354: 7812 ldrb r2, [r2, #0] 8003356: 0011 movs r1, r2 8003358: 2203 movs r2, #3 800335a: 400a ands r2, r1 800335c: 00d2 lsls r2, r2, #3 800335e: 21ff movs r1, #255 @ 0xff 8003360: 4091 lsls r1, r2 8003362: 000a movs r2, r1 8003364: 43d2 mvns r2, r2 8003366: 401a ands r2, r3 8003368: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800336a: 683b ldr r3, [r7, #0] 800336c: 019b lsls r3, r3, #6 800336e: 22ff movs r2, #255 @ 0xff 8003370: 401a ands r2, r3 8003372: 1dfb adds r3, r7, #7 8003374: 781b ldrb r3, [r3, #0] 8003376: 0018 movs r0, r3 8003378: 2303 movs r3, #3 800337a: 4003 ands r3, r0 800337c: 00db lsls r3, r3, #3 800337e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8003380: 4809 ldr r0, [pc, #36] @ (80033a8 <__NVIC_SetPriority+0xd8>) 8003382: 1dfb adds r3, r7, #7 8003384: 781b ldrb r3, [r3, #0] 8003386: 001c movs r4, r3 8003388: 230f movs r3, #15 800338a: 4023 ands r3, r4 800338c: 3b08 subs r3, #8 800338e: 089b lsrs r3, r3, #2 8003390: 430a orrs r2, r1 8003392: 3306 adds r3, #6 8003394: 009b lsls r3, r3, #2 8003396: 18c3 adds r3, r0, r3 8003398: 3304 adds r3, #4 800339a: 601a str r2, [r3, #0] } 800339c: 46c0 nop @ (mov r8, r8) 800339e: 46bd mov sp, r7 80033a0: b003 add sp, #12 80033a2: bd90 pop {r4, r7, pc} 80033a4: e000e100 .word 0xe000e100 80033a8: e000ed00 .word 0xe000ed00 080033ac <SysTick_Config>: \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80033ac: b580 push {r7, lr} 80033ae: b082 sub sp, #8 80033b0: af00 add r7, sp, #0 80033b2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80033b4: 687b ldr r3, [r7, #4] 80033b6: 1e5a subs r2, r3, #1 80033b8: 2380 movs r3, #128 @ 0x80 80033ba: 045b lsls r3, r3, #17 80033bc: 429a cmp r2, r3 80033be: d301 bcc.n 80033c4 <SysTick_Config+0x18> { return (1UL); /* Reload value impossible */ 80033c0: 2301 movs r3, #1 80033c2: e010 b.n 80033e6 <SysTick_Config+0x3a> } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80033c4: 4b0a ldr r3, [pc, #40] @ (80033f0 <SysTick_Config+0x44>) 80033c6: 687a ldr r2, [r7, #4] 80033c8: 3a01 subs r2, #1 80033ca: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80033cc: 2301 movs r3, #1 80033ce: 425b negs r3, r3 80033d0: 2103 movs r1, #3 80033d2: 0018 movs r0, r3 80033d4: f7ff ff7c bl 80032d0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80033d8: 4b05 ldr r3, [pc, #20] @ (80033f0 <SysTick_Config+0x44>) 80033da: 2200 movs r2, #0 80033dc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80033de: 4b04 ldr r3, [pc, #16] @ (80033f0 <SysTick_Config+0x44>) 80033e0: 2207 movs r2, #7 80033e2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80033e4: 2300 movs r3, #0 } 80033e6: 0018 movs r0, r3 80033e8: 46bd mov sp, r7 80033ea: b002 add sp, #8 80033ec: bd80 pop {r7, pc} 80033ee: 46c0 nop @ (mov r8, r8) 80033f0: e000e010 .word 0xe000e010 080033f4 <HAL_NVIC_SetPriority>: * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80033f4: b580 push {r7, lr} 80033f6: b084 sub sp, #16 80033f8: af00 add r7, sp, #0 80033fa: 60b9 str r1, [r7, #8] 80033fc: 607a str r2, [r7, #4] 80033fe: 210f movs r1, #15 8003400: 187b adds r3, r7, r1 8003402: 1c02 adds r2, r0, #0 8003404: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 8003406: 68ba ldr r2, [r7, #8] 8003408: 187b adds r3, r7, r1 800340a: 781b ldrb r3, [r3, #0] 800340c: b25b sxtb r3, r3 800340e: 0011 movs r1, r2 8003410: 0018 movs r0, r3 8003412: f7ff ff5d bl 80032d0 <__NVIC_SetPriority> } 8003416: 46c0 nop @ (mov r8, r8) 8003418: 46bd mov sp, r7 800341a: b004 add sp, #16 800341c: bd80 pop {r7, pc} 0800341e <HAL_NVIC_EnableIRQ>: * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800341e: b580 push {r7, lr} 8003420: b082 sub sp, #8 8003422: af00 add r7, sp, #0 8003424: 0002 movs r2, r0 8003426: 1dfb adds r3, r7, #7 8003428: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800342a: 1dfb adds r3, r7, #7 800342c: 781b ldrb r3, [r3, #0] 800342e: b25b sxtb r3, r3 8003430: 0018 movs r0, r3 8003432: f7ff ff33 bl 800329c <__NVIC_EnableIRQ> } 8003436: 46c0 nop @ (mov r8, r8) 8003438: 46bd mov sp, r7 800343a: b002 add sp, #8 800343c: bd80 pop {r7, pc} 0800343e <HAL_SYSTICK_Config>: * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800343e: b580 push {r7, lr} 8003440: b082 sub sp, #8 8003442: af00 add r7, sp, #0 8003444: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8003446: 687b ldr r3, [r7, #4] 8003448: 0018 movs r0, r3 800344a: f7ff ffaf bl 80033ac <SysTick_Config> 800344e: 0003 movs r3, r0 } 8003450: 0018 movs r0, r3 8003452: 46bd mov sp, r7 8003454: b002 add sp, #8 8003456: bd80 pop {r7, pc} 08003458 <HAL_DMA_Abort_IT>: * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003458: b580 push {r7, lr} 800345a: b084 sub sp, #16 800345c: af00 add r7, sp, #0 800345e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003460: 210f movs r1, #15 8003462: 187b adds r3, r7, r1 8003464: 2200 movs r2, #0 8003466: 701a strb r2, [r3, #0] if (hdma->State != HAL_DMA_STATE_BUSY) 8003468: 687b ldr r3, [r7, #4] 800346a: 2225 movs r2, #37 @ 0x25 800346c: 5c9b ldrb r3, [r3, r2] 800346e: b2db uxtb r3, r3 8003470: 2b02 cmp r3, #2 8003472: d006 beq.n 8003482 <HAL_DMA_Abort_IT+0x2a> { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003474: 687b ldr r3, [r7, #4] 8003476: 2204 movs r2, #4 8003478: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 800347a: 187b adds r3, r7, r1 800347c: 2201 movs r2, #1 800347e: 701a strb r2, [r3, #0] 8003480: e049 b.n 8003516 <HAL_DMA_Abort_IT+0xbe> } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003482: 687b ldr r3, [r7, #4] 8003484: 681b ldr r3, [r3, #0] 8003486: 681a ldr r2, [r3, #0] 8003488: 687b ldr r3, [r7, #4] 800348a: 681b ldr r3, [r3, #0] 800348c: 210e movs r1, #14 800348e: 438a bics r2, r1 8003490: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8003492: 687b ldr r3, [r7, #4] 8003494: 681b ldr r3, [r3, #0] 8003496: 681a ldr r2, [r3, #0] 8003498: 687b ldr r3, [r7, #4] 800349a: 681b ldr r3, [r3, #0] 800349c: 2101 movs r1, #1 800349e: 438a bics r2, r1 80034a0: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80034a2: 687b ldr r3, [r7, #4] 80034a4: 6c5b ldr r3, [r3, #68] @ 0x44 80034a6: 681a ldr r2, [r3, #0] 80034a8: 687b ldr r3, [r7, #4] 80034aa: 6c5b ldr r3, [r3, #68] @ 0x44 80034ac: 491d ldr r1, [pc, #116] @ (8003524 <HAL_DMA_Abort_IT+0xcc>) 80034ae: 400a ands r2, r1 80034b0: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); 80034b2: 4b1d ldr r3, [pc, #116] @ (8003528 <HAL_DMA_Abort_IT+0xd0>) 80034b4: 6859 ldr r1, [r3, #4] 80034b6: 687b ldr r3, [r7, #4] 80034b8: 6c1b ldr r3, [r3, #64] @ 0x40 80034ba: 221c movs r2, #28 80034bc: 4013 ands r3, r2 80034be: 2201 movs r2, #1 80034c0: 409a lsls r2, r3 80034c2: 4b19 ldr r3, [pc, #100] @ (8003528 <HAL_DMA_Abort_IT+0xd0>) 80034c4: 430a orrs r2, r1 80034c6: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80034c8: 687b ldr r3, [r7, #4] 80034ca: 6c9b ldr r3, [r3, #72] @ 0x48 80034cc: 687a ldr r2, [r7, #4] 80034ce: 6cd2 ldr r2, [r2, #76] @ 0x4c 80034d0: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 80034d2: 687b ldr r3, [r7, #4] 80034d4: 6d1b ldr r3, [r3, #80] @ 0x50 80034d6: 2b00 cmp r3, #0 80034d8: d00c beq.n 80034f4 <HAL_DMA_Abort_IT+0x9c> { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80034da: 687b ldr r3, [r7, #4] 80034dc: 6d1b ldr r3, [r3, #80] @ 0x50 80034de: 681a ldr r2, [r3, #0] 80034e0: 687b ldr r3, [r7, #4] 80034e2: 6d1b ldr r3, [r3, #80] @ 0x50 80034e4: 490f ldr r1, [pc, #60] @ (8003524 <HAL_DMA_Abort_IT+0xcc>) 80034e6: 400a ands r2, r1 80034e8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80034ea: 687b ldr r3, [r7, #4] 80034ec: 6d5b ldr r3, [r3, #84] @ 0x54 80034ee: 687a ldr r2, [r7, #4] 80034f0: 6d92 ldr r2, [r2, #88] @ 0x58 80034f2: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80034f4: 687b ldr r3, [r7, #4] 80034f6: 2225 movs r2, #37 @ 0x25 80034f8: 2101 movs r1, #1 80034fa: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80034fc: 687b ldr r3, [r7, #4] 80034fe: 2224 movs r2, #36 @ 0x24 8003500: 2100 movs r1, #0 8003502: 5499 strb r1, [r3, r2] /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 8003504: 687b ldr r3, [r7, #4] 8003506: 6b9b ldr r3, [r3, #56] @ 0x38 8003508: 2b00 cmp r3, #0 800350a: d004 beq.n 8003516 <HAL_DMA_Abort_IT+0xbe> { hdma->XferAbortCallback(hdma); 800350c: 687b ldr r3, [r7, #4] 800350e: 6b9b ldr r3, [r3, #56] @ 0x38 8003510: 687a ldr r2, [r7, #4] 8003512: 0010 movs r0, r2 8003514: 4798 blx r3 } } return status; 8003516: 230f movs r3, #15 8003518: 18fb adds r3, r7, r3 800351a: 781b ldrb r3, [r3, #0] } 800351c: 0018 movs r0, r3 800351e: 46bd mov sp, r7 8003520: b004 add sp, #16 8003522: bd80 pop {r7, pc} 8003524: fffffeff .word 0xfffffeff 8003528: 40020000 .word 0x40020000 0800352c <HAL_GPIO_Init>: * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800352c: b580 push {r7, lr} 800352e: b086 sub sp, #24 8003530: af00 add r7, sp, #0 8003532: 6078 str r0, [r7, #4] 8003534: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003536: 2300 movs r3, #0 8003538: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800353a: e147 b.n 80037cc <HAL_GPIO_Init+0x2a0> { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 800353c: 683b ldr r3, [r7, #0] 800353e: 681b ldr r3, [r3, #0] 8003540: 2101 movs r1, #1 8003542: 697a ldr r2, [r7, #20] 8003544: 4091 lsls r1, r2 8003546: 000a movs r2, r1 8003548: 4013 ands r3, r2 800354a: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 800354c: 68fb ldr r3, [r7, #12] 800354e: 2b00 cmp r3, #0 8003550: d100 bne.n 8003554 <HAL_GPIO_Init+0x28> 8003552: e138 b.n 80037c6 <HAL_GPIO_Init+0x29a> { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8003554: 683b ldr r3, [r7, #0] 8003556: 685b ldr r3, [r3, #4] 8003558: 2203 movs r2, #3 800355a: 4013 ands r3, r2 800355c: 2b01 cmp r3, #1 800355e: d005 beq.n 800356c <HAL_GPIO_Init+0x40> 8003560: 683b ldr r3, [r7, #0] 8003562: 685b ldr r3, [r3, #4] 8003564: 2203 movs r2, #3 8003566: 4013 ands r3, r2 8003568: 2b02 cmp r3, #2 800356a: d130 bne.n 80035ce <HAL_GPIO_Init+0xa2> { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800356c: 687b ldr r3, [r7, #4] 800356e: 689b ldr r3, [r3, #8] 8003570: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 8003572: 697b ldr r3, [r7, #20] 8003574: 005b lsls r3, r3, #1 8003576: 2203 movs r2, #3 8003578: 409a lsls r2, r3 800357a: 0013 movs r3, r2 800357c: 43da mvns r2, r3 800357e: 693b ldr r3, [r7, #16] 8003580: 4013 ands r3, r2 8003582: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8003584: 683b ldr r3, [r7, #0] 8003586: 68da ldr r2, [r3, #12] 8003588: 697b ldr r3, [r7, #20] 800358a: 005b lsls r3, r3, #1 800358c: 409a lsls r2, r3 800358e: 0013 movs r3, r2 8003590: 693a ldr r2, [r7, #16] 8003592: 4313 orrs r3, r2 8003594: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8003596: 687b ldr r3, [r7, #4] 8003598: 693a ldr r2, [r7, #16] 800359a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800359c: 687b ldr r3, [r7, #4] 800359e: 685b ldr r3, [r3, #4] 80035a0: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 80035a2: 2201 movs r2, #1 80035a4: 697b ldr r3, [r7, #20] 80035a6: 409a lsls r2, r3 80035a8: 0013 movs r3, r2 80035aa: 43da mvns r2, r3 80035ac: 693b ldr r3, [r7, #16] 80035ae: 4013 ands r3, r2 80035b0: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80035b2: 683b ldr r3, [r7, #0] 80035b4: 685b ldr r3, [r3, #4] 80035b6: 091b lsrs r3, r3, #4 80035b8: 2201 movs r2, #1 80035ba: 401a ands r2, r3 80035bc: 697b ldr r3, [r7, #20] 80035be: 409a lsls r2, r3 80035c0: 0013 movs r3, r2 80035c2: 693a ldr r2, [r7, #16] 80035c4: 4313 orrs r3, r2 80035c6: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80035c8: 687b ldr r3, [r7, #4] 80035ca: 693a ldr r2, [r7, #16] 80035cc: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80035ce: 683b ldr r3, [r7, #0] 80035d0: 685b ldr r3, [r3, #4] 80035d2: 2203 movs r2, #3 80035d4: 4013 ands r3, r2 80035d6: 2b03 cmp r3, #3 80035d8: d017 beq.n 800360a <HAL_GPIO_Init+0xde> { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80035da: 687b ldr r3, [r7, #4] 80035dc: 68db ldr r3, [r3, #12] 80035de: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); 80035e0: 697b ldr r3, [r7, #20] 80035e2: 005b lsls r3, r3, #1 80035e4: 2203 movs r2, #3 80035e6: 409a lsls r2, r3 80035e8: 0013 movs r3, r2 80035ea: 43da mvns r2, r3 80035ec: 693b ldr r3, [r7, #16] 80035ee: 4013 ands r3, r2 80035f0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80035f2: 683b ldr r3, [r7, #0] 80035f4: 689a ldr r2, [r3, #8] 80035f6: 697b ldr r3, [r7, #20] 80035f8: 005b lsls r3, r3, #1 80035fa: 409a lsls r2, r3 80035fc: 0013 movs r3, r2 80035fe: 693a ldr r2, [r7, #16] 8003600: 4313 orrs r3, r2 8003602: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8003604: 687b ldr r3, [r7, #4] 8003606: 693a ldr r2, [r7, #16] 8003608: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800360a: 683b ldr r3, [r7, #0] 800360c: 685b ldr r3, [r3, #4] 800360e: 2203 movs r2, #3 8003610: 4013 ands r3, r2 8003612: 2b02 cmp r3, #2 8003614: d123 bne.n 800365e <HAL_GPIO_Init+0x132> /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8003616: 697b ldr r3, [r7, #20] 8003618: 08da lsrs r2, r3, #3 800361a: 687b ldr r3, [r7, #4] 800361c: 3208 adds r2, #8 800361e: 0092 lsls r2, r2, #2 8003620: 58d3 ldr r3, [r2, r3] 8003622: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8003624: 697b ldr r3, [r7, #20] 8003626: 2207 movs r2, #7 8003628: 4013 ands r3, r2 800362a: 009b lsls r3, r3, #2 800362c: 220f movs r2, #15 800362e: 409a lsls r2, r3 8003630: 0013 movs r3, r2 8003632: 43da mvns r2, r3 8003634: 693b ldr r3, [r7, #16] 8003636: 4013 ands r3, r2 8003638: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800363a: 683b ldr r3, [r7, #0] 800363c: 691a ldr r2, [r3, #16] 800363e: 697b ldr r3, [r7, #20] 8003640: 2107 movs r1, #7 8003642: 400b ands r3, r1 8003644: 009b lsls r3, r3, #2 8003646: 409a lsls r2, r3 8003648: 0013 movs r3, r2 800364a: 693a ldr r2, [r7, #16] 800364c: 4313 orrs r3, r2 800364e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8003650: 697b ldr r3, [r7, #20] 8003652: 08da lsrs r2, r3, #3 8003654: 687b ldr r3, [r7, #4] 8003656: 3208 adds r2, #8 8003658: 0092 lsls r2, r2, #2 800365a: 6939 ldr r1, [r7, #16] 800365c: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800365e: 687b ldr r3, [r7, #4] 8003660: 681b ldr r3, [r3, #0] 8003662: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8003664: 697b ldr r3, [r7, #20] 8003666: 005b lsls r3, r3, #1 8003668: 2203 movs r2, #3 800366a: 409a lsls r2, r3 800366c: 0013 movs r3, r2 800366e: 43da mvns r2, r3 8003670: 693b ldr r3, [r7, #16] 8003672: 4013 ands r3, r2 8003674: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8003676: 683b ldr r3, [r7, #0] 8003678: 685b ldr r3, [r3, #4] 800367a: 2203 movs r2, #3 800367c: 401a ands r2, r3 800367e: 697b ldr r3, [r7, #20] 8003680: 005b lsls r3, r3, #1 8003682: 409a lsls r2, r3 8003684: 0013 movs r3, r2 8003686: 693a ldr r2, [r7, #16] 8003688: 4313 orrs r3, r2 800368a: 613b str r3, [r7, #16] GPIOx->MODER = temp; 800368c: 687b ldr r3, [r7, #4] 800368e: 693a ldr r2, [r7, #16] 8003690: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8003692: 683b ldr r3, [r7, #0] 8003694: 685a ldr r2, [r3, #4] 8003696: 23c0 movs r3, #192 @ 0xc0 8003698: 029b lsls r3, r3, #10 800369a: 4013 ands r3, r2 800369c: d100 bne.n 80036a0 <HAL_GPIO_Init+0x174> 800369e: e092 b.n 80037c6 <HAL_GPIO_Init+0x29a> { temp = EXTI->EXTICR[position >> 2u]; 80036a0: 4a50 ldr r2, [pc, #320] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 80036a2: 697b ldr r3, [r7, #20] 80036a4: 089b lsrs r3, r3, #2 80036a6: 3318 adds r3, #24 80036a8: 009b lsls r3, r3, #2 80036aa: 589b ldr r3, [r3, r2] 80036ac: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (8u * (position & 0x03u))); 80036ae: 697b ldr r3, [r7, #20] 80036b0: 2203 movs r2, #3 80036b2: 4013 ands r3, r2 80036b4: 00db lsls r3, r3, #3 80036b6: 220f movs r2, #15 80036b8: 409a lsls r2, r3 80036ba: 0013 movs r3, r2 80036bc: 43da mvns r2, r3 80036be: 693b ldr r3, [r7, #16] 80036c0: 4013 ands r3, r2 80036c2: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); 80036c4: 687a ldr r2, [r7, #4] 80036c6: 23a0 movs r3, #160 @ 0xa0 80036c8: 05db lsls r3, r3, #23 80036ca: 429a cmp r2, r3 80036cc: d013 beq.n 80036f6 <HAL_GPIO_Init+0x1ca> 80036ce: 687b ldr r3, [r7, #4] 80036d0: 4a45 ldr r2, [pc, #276] @ (80037e8 <HAL_GPIO_Init+0x2bc>) 80036d2: 4293 cmp r3, r2 80036d4: d00d beq.n 80036f2 <HAL_GPIO_Init+0x1c6> 80036d6: 687b ldr r3, [r7, #4] 80036d8: 4a44 ldr r2, [pc, #272] @ (80037ec <HAL_GPIO_Init+0x2c0>) 80036da: 4293 cmp r3, r2 80036dc: d007 beq.n 80036ee <HAL_GPIO_Init+0x1c2> 80036de: 687b ldr r3, [r7, #4] 80036e0: 4a43 ldr r2, [pc, #268] @ (80037f0 <HAL_GPIO_Init+0x2c4>) 80036e2: 4293 cmp r3, r2 80036e4: d101 bne.n 80036ea <HAL_GPIO_Init+0x1be> 80036e6: 2303 movs r3, #3 80036e8: e006 b.n 80036f8 <HAL_GPIO_Init+0x1cc> 80036ea: 2305 movs r3, #5 80036ec: e004 b.n 80036f8 <HAL_GPIO_Init+0x1cc> 80036ee: 2302 movs r3, #2 80036f0: e002 b.n 80036f8 <HAL_GPIO_Init+0x1cc> 80036f2: 2301 movs r3, #1 80036f4: e000 b.n 80036f8 <HAL_GPIO_Init+0x1cc> 80036f6: 2300 movs r3, #0 80036f8: 697a ldr r2, [r7, #20] 80036fa: 2103 movs r1, #3 80036fc: 400a ands r2, r1 80036fe: 00d2 lsls r2, r2, #3 8003700: 4093 lsls r3, r2 8003702: 693a ldr r2, [r7, #16] 8003704: 4313 orrs r3, r2 8003706: 613b str r3, [r7, #16] EXTI->EXTICR[position >> 2u] = temp; 8003708: 4936 ldr r1, [pc, #216] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 800370a: 697b ldr r3, [r7, #20] 800370c: 089b lsrs r3, r3, #2 800370e: 3318 adds r3, #24 8003710: 009b lsls r3, r3, #2 8003712: 693a ldr r2, [r7, #16] 8003714: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8003716: 4b33 ldr r3, [pc, #204] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 8003718: 681b ldr r3, [r3, #0] 800371a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800371c: 68fb ldr r3, [r7, #12] 800371e: 43da mvns r2, r3 8003720: 693b ldr r3, [r7, #16] 8003722: 4013 ands r3, r2 8003724: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8003726: 683b ldr r3, [r7, #0] 8003728: 685a ldr r2, [r3, #4] 800372a: 2380 movs r3, #128 @ 0x80 800372c: 035b lsls r3, r3, #13 800372e: 4013 ands r3, r2 8003730: d003 beq.n 800373a <HAL_GPIO_Init+0x20e> { temp |= iocurrent; 8003732: 693a ldr r2, [r7, #16] 8003734: 68fb ldr r3, [r7, #12] 8003736: 4313 orrs r3, r2 8003738: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 800373a: 4b2a ldr r3, [pc, #168] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 800373c: 693a ldr r2, [r7, #16] 800373e: 601a str r2, [r3, #0] temp = EXTI->FTSR1; 8003740: 4b28 ldr r3, [pc, #160] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 8003742: 685b ldr r3, [r3, #4] 8003744: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003746: 68fb ldr r3, [r7, #12] 8003748: 43da mvns r2, r3 800374a: 693b ldr r3, [r7, #16] 800374c: 4013 ands r3, r2 800374e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8003750: 683b ldr r3, [r7, #0] 8003752: 685a ldr r2, [r3, #4] 8003754: 2380 movs r3, #128 @ 0x80 8003756: 039b lsls r3, r3, #14 8003758: 4013 ands r3, r2 800375a: d003 beq.n 8003764 <HAL_GPIO_Init+0x238> { temp |= iocurrent; 800375c: 693a ldr r2, [r7, #16] 800375e: 68fb ldr r3, [r7, #12] 8003760: 4313 orrs r3, r2 8003762: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8003764: 4b1f ldr r3, [pc, #124] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 8003766: 693a ldr r2, [r7, #16] 8003768: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 800376a: 4a1e ldr r2, [pc, #120] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 800376c: 2384 movs r3, #132 @ 0x84 800376e: 58d3 ldr r3, [r2, r3] 8003770: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003772: 68fb ldr r3, [r7, #12] 8003774: 43da mvns r2, r3 8003776: 693b ldr r3, [r7, #16] 8003778: 4013 ands r3, r2 800377a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 800377c: 683b ldr r3, [r7, #0] 800377e: 685a ldr r2, [r3, #4] 8003780: 2380 movs r3, #128 @ 0x80 8003782: 029b lsls r3, r3, #10 8003784: 4013 ands r3, r2 8003786: d003 beq.n 8003790 <HAL_GPIO_Init+0x264> { temp |= iocurrent; 8003788: 693a ldr r2, [r7, #16] 800378a: 68fb ldr r3, [r7, #12] 800378c: 4313 orrs r3, r2 800378e: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8003790: 4914 ldr r1, [pc, #80] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 8003792: 2284 movs r2, #132 @ 0x84 8003794: 693b ldr r3, [r7, #16] 8003796: 508b str r3, [r1, r2] temp = EXTI->IMR1; 8003798: 4a12 ldr r2, [pc, #72] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 800379a: 2380 movs r3, #128 @ 0x80 800379c: 58d3 ldr r3, [r2, r3] 800379e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80037a0: 68fb ldr r3, [r7, #12] 80037a2: 43da mvns r2, r3 80037a4: 693b ldr r3, [r7, #16] 80037a6: 4013 ands r3, r2 80037a8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 80037aa: 683b ldr r3, [r7, #0] 80037ac: 685a ldr r2, [r3, #4] 80037ae: 2380 movs r3, #128 @ 0x80 80037b0: 025b lsls r3, r3, #9 80037b2: 4013 ands r3, r2 80037b4: d003 beq.n 80037be <HAL_GPIO_Init+0x292> { temp |= iocurrent; 80037b6: 693a ldr r2, [r7, #16] 80037b8: 68fb ldr r3, [r7, #12] 80037ba: 4313 orrs r3, r2 80037bc: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 80037be: 4909 ldr r1, [pc, #36] @ (80037e4 <HAL_GPIO_Init+0x2b8>) 80037c0: 2280 movs r2, #128 @ 0x80 80037c2: 693b ldr r3, [r7, #16] 80037c4: 508b str r3, [r1, r2] } } position++; 80037c6: 697b ldr r3, [r7, #20] 80037c8: 3301 adds r3, #1 80037ca: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80037cc: 683b ldr r3, [r7, #0] 80037ce: 681a ldr r2, [r3, #0] 80037d0: 697b ldr r3, [r7, #20] 80037d2: 40da lsrs r2, r3 80037d4: 1e13 subs r3, r2, #0 80037d6: d000 beq.n 80037da <HAL_GPIO_Init+0x2ae> 80037d8: e6b0 b.n 800353c <HAL_GPIO_Init+0x10> } } 80037da: 46c0 nop @ (mov r8, r8) 80037dc: 46c0 nop @ (mov r8, r8) 80037de: 46bd mov sp, r7 80037e0: b006 add sp, #24 80037e2: bd80 pop {r7, pc} 80037e4: 40021800 .word 0x40021800 80037e8: 50000400 .word 0x50000400 80037ec: 50000800 .word 0x50000800 80037f0: 50000c00 .word 0x50000c00 080037f4 <HAL_GPIO_WritePin>: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80037f4: b580 push {r7, lr} 80037f6: b082 sub sp, #8 80037f8: af00 add r7, sp, #0 80037fa: 6078 str r0, [r7, #4] 80037fc: 0008 movs r0, r1 80037fe: 0011 movs r1, r2 8003800: 1cbb adds r3, r7, #2 8003802: 1c02 adds r2, r0, #0 8003804: 801a strh r2, [r3, #0] 8003806: 1c7b adds r3, r7, #1 8003808: 1c0a adds r2, r1, #0 800380a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800380c: 1c7b adds r3, r7, #1 800380e: 781b ldrb r3, [r3, #0] 8003810: 2b00 cmp r3, #0 8003812: d004 beq.n 800381e <HAL_GPIO_WritePin+0x2a> { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8003814: 1cbb adds r3, r7, #2 8003816: 881a ldrh r2, [r3, #0] 8003818: 687b ldr r3, [r7, #4] 800381a: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 800381c: e003 b.n 8003826 <HAL_GPIO_WritePin+0x32> GPIOx->BRR = (uint32_t)GPIO_Pin; 800381e: 1cbb adds r3, r7, #2 8003820: 881a ldrh r2, [r3, #0] 8003822: 687b ldr r3, [r7, #4] 8003824: 629a str r2, [r3, #40] @ 0x28 } 8003826: 46c0 nop @ (mov r8, r8) 8003828: 46bd mov sp, r7 800382a: b002 add sp, #8 800382c: bd80 pop {r7, pc} ... 08003830 <HAL_GPIO_EXTI_IRQHandler>: * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8003830: b580 push {r7, lr} 8003832: b082 sub sp, #8 8003834: af00 add r7, sp, #0 8003836: 0002 movs r2, r0 8003838: 1dbb adds r3, r7, #6 800383a: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) 800383c: 4b10 ldr r3, [pc, #64] @ (8003880 <HAL_GPIO_EXTI_IRQHandler+0x50>) 800383e: 68db ldr r3, [r3, #12] 8003840: 1dba adds r2, r7, #6 8003842: 8812 ldrh r2, [r2, #0] 8003844: 4013 ands r3, r2 8003846: d008 beq.n 800385a <HAL_GPIO_EXTI_IRQHandler+0x2a> { __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); 8003848: 4b0d ldr r3, [pc, #52] @ (8003880 <HAL_GPIO_EXTI_IRQHandler+0x50>) 800384a: 1dba adds r2, r7, #6 800384c: 8812 ldrh r2, [r2, #0] 800384e: 60da str r2, [r3, #12] HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); 8003850: 1dbb adds r3, r7, #6 8003852: 881b ldrh r3, [r3, #0] 8003854: 0018 movs r0, r3 8003856: f000 f815 bl 8003884 <HAL_GPIO_EXTI_Rising_Callback> } if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) 800385a: 4b09 ldr r3, [pc, #36] @ (8003880 <HAL_GPIO_EXTI_IRQHandler+0x50>) 800385c: 691b ldr r3, [r3, #16] 800385e: 1dba adds r2, r7, #6 8003860: 8812 ldrh r2, [r2, #0] 8003862: 4013 ands r3, r2 8003864: d008 beq.n 8003878 <HAL_GPIO_EXTI_IRQHandler+0x48> { __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); 8003866: 4b06 ldr r3, [pc, #24] @ (8003880 <HAL_GPIO_EXTI_IRQHandler+0x50>) 8003868: 1dba adds r2, r7, #6 800386a: 8812 ldrh r2, [r2, #0] 800386c: 611a str r2, [r3, #16] HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); 800386e: 1dbb adds r3, r7, #6 8003870: 881b ldrh r3, [r3, #0] 8003872: 0018 movs r0, r3 8003874: f7ff fad0 bl 8002e18 <HAL_GPIO_EXTI_Falling_Callback> } } 8003878: 46c0 nop @ (mov r8, r8) 800387a: 46bd mov sp, r7 800387c: b002 add sp, #8 800387e: bd80 pop {r7, pc} 8003880: 40021800 .word 0x40021800 08003884 <HAL_GPIO_EXTI_Rising_Callback>: * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) { 8003884: b580 push {r7, lr} 8003886: b082 sub sp, #8 8003888: af00 add r7, sp, #0 800388a: 0002 movs r2, r0 800388c: 1dbb adds r3, r7, #6 800388e: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file */ } 8003890: 46c0 nop @ (mov r8, r8) 8003892: 46bd mov sp, r7 8003894: b002 add sp, #8 8003896: bd80 pop {r7, pc} 08003898 <HAL_PWREx_ControlVoltageScaling>: * cleared before returning the status. If the flag is not cleared within * 6 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8003898: b580 push {r7, lr} 800389a: b084 sub sp, #16 800389c: af00 add r7, sp, #0 800389e: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* Modify voltage scaling range */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 80038a0: 4b19 ldr r3, [pc, #100] @ (8003908 <HAL_PWREx_ControlVoltageScaling+0x70>) 80038a2: 681b ldr r3, [r3, #0] 80038a4: 4a19 ldr r2, [pc, #100] @ (800390c <HAL_PWREx_ControlVoltageScaling+0x74>) 80038a6: 4013 ands r3, r2 80038a8: 0019 movs r1, r3 80038aa: 4b17 ldr r3, [pc, #92] @ (8003908 <HAL_PWREx_ControlVoltageScaling+0x70>) 80038ac: 687a ldr r2, [r7, #4] 80038ae: 430a orrs r2, r1 80038b0: 601a str r2, [r3, #0] /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 80038b2: 687a ldr r2, [r7, #4] 80038b4: 2380 movs r3, #128 @ 0x80 80038b6: 009b lsls r3, r3, #2 80038b8: 429a cmp r2, r3 80038ba: d11f bne.n 80038fc <HAL_PWREx_ControlVoltageScaling+0x64> { /* Set timeout value */ wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; 80038bc: 4b14 ldr r3, [pc, #80] @ (8003910 <HAL_PWREx_ControlVoltageScaling+0x78>) 80038be: 681a ldr r2, [r3, #0] 80038c0: 0013 movs r3, r2 80038c2: 005b lsls r3, r3, #1 80038c4: 189b adds r3, r3, r2 80038c6: 005b lsls r3, r3, #1 80038c8: 4912 ldr r1, [pc, #72] @ (8003914 <HAL_PWREx_ControlVoltageScaling+0x7c>) 80038ca: 0018 movs r0, r3 80038cc: f7fc fc1a bl 8000104 <__udivsi3> 80038d0: 0003 movs r3, r0 80038d2: 3301 adds r3, #1 80038d4: 60fb str r3, [r7, #12] /* Wait until VOSF is reset */ while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80038d6: e008 b.n 80038ea <HAL_PWREx_ControlVoltageScaling+0x52> { if (wait_loop_index != 0U) 80038d8: 68fb ldr r3, [r7, #12] 80038da: 2b00 cmp r3, #0 80038dc: d003 beq.n 80038e6 <HAL_PWREx_ControlVoltageScaling+0x4e> { wait_loop_index--; 80038de: 68fb ldr r3, [r7, #12] 80038e0: 3b01 subs r3, #1 80038e2: 60fb str r3, [r7, #12] 80038e4: e001 b.n 80038ea <HAL_PWREx_ControlVoltageScaling+0x52> } else { return HAL_TIMEOUT; 80038e6: 2303 movs r3, #3 80038e8: e009 b.n 80038fe <HAL_PWREx_ControlVoltageScaling+0x66> while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80038ea: 4b07 ldr r3, [pc, #28] @ (8003908 <HAL_PWREx_ControlVoltageScaling+0x70>) 80038ec: 695a ldr r2, [r3, #20] 80038ee: 2380 movs r3, #128 @ 0x80 80038f0: 00db lsls r3, r3, #3 80038f2: 401a ands r2, r3 80038f4: 2380 movs r3, #128 @ 0x80 80038f6: 00db lsls r3, r3, #3 80038f8: 429a cmp r2, r3 80038fa: d0ed beq.n 80038d8 <HAL_PWREx_ControlVoltageScaling+0x40> } } } return HAL_OK; 80038fc: 2300 movs r3, #0 } 80038fe: 0018 movs r0, r3 8003900: 46bd mov sp, r7 8003902: b004 add sp, #16 8003904: bd80 pop {r7, pc} 8003906: 46c0 nop @ (mov r8, r8) 8003908: 40007000 .word 0x40007000 800390c: fffff9ff .word 0xfffff9ff 8003910: 20000014 .word 0x20000014 8003914: 000f4240 .word 0x000f4240 08003918 <HAL_RCC_OscConfig>: * supported by this function. User should request a transition to LSE Off * first and then to LSE On or LSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003918: b580 push {r7, lr} 800391a: b088 sub sp, #32 800391c: af00 add r7, sp, #0 800391e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003920: 687b ldr r3, [r7, #4] 8003922: 2b00 cmp r3, #0 8003924: d101 bne.n 800392a <HAL_RCC_OscConfig+0x12> { return HAL_ERROR; 8003926: 2301 movs r3, #1 8003928: e2fe b.n 8003f28 <HAL_RCC_OscConfig+0x610> /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800392a: 687b ldr r3, [r7, #4] 800392c: 681b ldr r3, [r3, #0] 800392e: 2201 movs r2, #1 8003930: 4013 ands r3, r2 8003932: d100 bne.n 8003936 <HAL_RCC_OscConfig+0x1e> 8003934: e07c b.n 8003a30 <HAL_RCC_OscConfig+0x118> { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003936: 4bc3 ldr r3, [pc, #780] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003938: 689b ldr r3, [r3, #8] 800393a: 2238 movs r2, #56 @ 0x38 800393c: 4013 ands r3, r2 800393e: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003940: 4bc0 ldr r3, [pc, #768] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003942: 68db ldr r3, [r3, #12] 8003944: 2203 movs r2, #3 8003946: 4013 ands r3, r2 8003948: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) 800394a: 69bb ldr r3, [r7, #24] 800394c: 2b10 cmp r3, #16 800394e: d102 bne.n 8003956 <HAL_RCC_OscConfig+0x3e> 8003950: 697b ldr r3, [r7, #20] 8003952: 2b03 cmp r3, #3 8003954: d002 beq.n 800395c <HAL_RCC_OscConfig+0x44> || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) 8003956: 69bb ldr r3, [r7, #24] 8003958: 2b08 cmp r3, #8 800395a: d10b bne.n 8003974 <HAL_RCC_OscConfig+0x5c> { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800395c: 4bb9 ldr r3, [pc, #740] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 800395e: 681a ldr r2, [r3, #0] 8003960: 2380 movs r3, #128 @ 0x80 8003962: 029b lsls r3, r3, #10 8003964: 4013 ands r3, r2 8003966: d062 beq.n 8003a2e <HAL_RCC_OscConfig+0x116> 8003968: 687b ldr r3, [r7, #4] 800396a: 685b ldr r3, [r3, #4] 800396c: 2b00 cmp r3, #0 800396e: d15e bne.n 8003a2e <HAL_RCC_OscConfig+0x116> { return HAL_ERROR; 8003970: 2301 movs r3, #1 8003972: e2d9 b.n 8003f28 <HAL_RCC_OscConfig+0x610> } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003974: 687b ldr r3, [r7, #4] 8003976: 685a ldr r2, [r3, #4] 8003978: 2380 movs r3, #128 @ 0x80 800397a: 025b lsls r3, r3, #9 800397c: 429a cmp r2, r3 800397e: d107 bne.n 8003990 <HAL_RCC_OscConfig+0x78> 8003980: 4bb0 ldr r3, [pc, #704] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003982: 681a ldr r2, [r3, #0] 8003984: 4baf ldr r3, [pc, #700] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003986: 2180 movs r1, #128 @ 0x80 8003988: 0249 lsls r1, r1, #9 800398a: 430a orrs r2, r1 800398c: 601a str r2, [r3, #0] 800398e: e020 b.n 80039d2 <HAL_RCC_OscConfig+0xba> 8003990: 687b ldr r3, [r7, #4] 8003992: 685a ldr r2, [r3, #4] 8003994: 23a0 movs r3, #160 @ 0xa0 8003996: 02db lsls r3, r3, #11 8003998: 429a cmp r2, r3 800399a: d10e bne.n 80039ba <HAL_RCC_OscConfig+0xa2> 800399c: 4ba9 ldr r3, [pc, #676] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 800399e: 681a ldr r2, [r3, #0] 80039a0: 4ba8 ldr r3, [pc, #672] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039a2: 2180 movs r1, #128 @ 0x80 80039a4: 02c9 lsls r1, r1, #11 80039a6: 430a orrs r2, r1 80039a8: 601a str r2, [r3, #0] 80039aa: 4ba6 ldr r3, [pc, #664] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039ac: 681a ldr r2, [r3, #0] 80039ae: 4ba5 ldr r3, [pc, #660] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039b0: 2180 movs r1, #128 @ 0x80 80039b2: 0249 lsls r1, r1, #9 80039b4: 430a orrs r2, r1 80039b6: 601a str r2, [r3, #0] 80039b8: e00b b.n 80039d2 <HAL_RCC_OscConfig+0xba> 80039ba: 4ba2 ldr r3, [pc, #648] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039bc: 681a ldr r2, [r3, #0] 80039be: 4ba1 ldr r3, [pc, #644] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039c0: 49a1 ldr r1, [pc, #644] @ (8003c48 <HAL_RCC_OscConfig+0x330>) 80039c2: 400a ands r2, r1 80039c4: 601a str r2, [r3, #0] 80039c6: 4b9f ldr r3, [pc, #636] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039c8: 681a ldr r2, [r3, #0] 80039ca: 4b9e ldr r3, [pc, #632] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039cc: 499f ldr r1, [pc, #636] @ (8003c4c <HAL_RCC_OscConfig+0x334>) 80039ce: 400a ands r2, r1 80039d0: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80039d2: 687b ldr r3, [r7, #4] 80039d4: 685b ldr r3, [r3, #4] 80039d6: 2b00 cmp r3, #0 80039d8: d014 beq.n 8003a04 <HAL_RCC_OscConfig+0xec> { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039da: f7ff fc31 bl 8003240 <HAL_GetTick> 80039de: 0003 movs r3, r0 80039e0: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80039e2: e008 b.n 80039f6 <HAL_RCC_OscConfig+0xde> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80039e4: f7ff fc2c bl 8003240 <HAL_GetTick> 80039e8: 0002 movs r2, r0 80039ea: 693b ldr r3, [r7, #16] 80039ec: 1ad3 subs r3, r2, r3 80039ee: 2b64 cmp r3, #100 @ 0x64 80039f0: d901 bls.n 80039f6 <HAL_RCC_OscConfig+0xde> { return HAL_TIMEOUT; 80039f2: 2303 movs r3, #3 80039f4: e298 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80039f6: 4b93 ldr r3, [pc, #588] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 80039f8: 681a ldr r2, [r3, #0] 80039fa: 2380 movs r3, #128 @ 0x80 80039fc: 029b lsls r3, r3, #10 80039fe: 4013 ands r3, r2 8003a00: d0f0 beq.n 80039e4 <HAL_RCC_OscConfig+0xcc> 8003a02: e015 b.n 8003a30 <HAL_RCC_OscConfig+0x118> } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003a04: f7ff fc1c bl 8003240 <HAL_GetTick> 8003a08: 0003 movs r3, r0 8003a0a: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003a0c: e008 b.n 8003a20 <HAL_RCC_OscConfig+0x108> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003a0e: f7ff fc17 bl 8003240 <HAL_GetTick> 8003a12: 0002 movs r2, r0 8003a14: 693b ldr r3, [r7, #16] 8003a16: 1ad3 subs r3, r2, r3 8003a18: 2b64 cmp r3, #100 @ 0x64 8003a1a: d901 bls.n 8003a20 <HAL_RCC_OscConfig+0x108> { return HAL_TIMEOUT; 8003a1c: 2303 movs r3, #3 8003a1e: e283 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003a20: 4b88 ldr r3, [pc, #544] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a22: 681a ldr r2, [r3, #0] 8003a24: 2380 movs r3, #128 @ 0x80 8003a26: 029b lsls r3, r3, #10 8003a28: 4013 ands r3, r2 8003a2a: d1f0 bne.n 8003a0e <HAL_RCC_OscConfig+0xf6> 8003a2c: e000 b.n 8003a30 <HAL_RCC_OscConfig+0x118> if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003a2e: 46c0 nop @ (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003a30: 687b ldr r3, [r7, #4] 8003a32: 681b ldr r3, [r3, #0] 8003a34: 2202 movs r2, #2 8003a36: 4013 ands r3, r2 8003a38: d100 bne.n 8003a3c <HAL_RCC_OscConfig+0x124> 8003a3a: e099 b.n 8003b70 <HAL_RCC_OscConfig+0x258> assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003a3c: 4b81 ldr r3, [pc, #516] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a3e: 689b ldr r3, [r3, #8] 8003a40: 2238 movs r2, #56 @ 0x38 8003a42: 4013 ands r3, r2 8003a44: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003a46: 4b7f ldr r3, [pc, #508] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a48: 68db ldr r3, [r3, #12] 8003a4a: 2203 movs r2, #3 8003a4c: 4013 ands r3, r2 8003a4e: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) 8003a50: 69bb ldr r3, [r7, #24] 8003a52: 2b10 cmp r3, #16 8003a54: d102 bne.n 8003a5c <HAL_RCC_OscConfig+0x144> 8003a56: 697b ldr r3, [r7, #20] 8003a58: 2b02 cmp r3, #2 8003a5a: d002 beq.n 8003a62 <HAL_RCC_OscConfig+0x14a> || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) 8003a5c: 69bb ldr r3, [r7, #24] 8003a5e: 2b00 cmp r3, #0 8003a60: d135 bne.n 8003ace <HAL_RCC_OscConfig+0x1b6> { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003a62: 4b78 ldr r3, [pc, #480] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a64: 681a ldr r2, [r3, #0] 8003a66: 2380 movs r3, #128 @ 0x80 8003a68: 00db lsls r3, r3, #3 8003a6a: 4013 ands r3, r2 8003a6c: d005 beq.n 8003a7a <HAL_RCC_OscConfig+0x162> 8003a6e: 687b ldr r3, [r7, #4] 8003a70: 68db ldr r3, [r3, #12] 8003a72: 2b00 cmp r3, #0 8003a74: d101 bne.n 8003a7a <HAL_RCC_OscConfig+0x162> { return HAL_ERROR; 8003a76: 2301 movs r3, #1 8003a78: e256 b.n 8003f28 <HAL_RCC_OscConfig+0x610> } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003a7a: 4b72 ldr r3, [pc, #456] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a7c: 685b ldr r3, [r3, #4] 8003a7e: 4a74 ldr r2, [pc, #464] @ (8003c50 <HAL_RCC_OscConfig+0x338>) 8003a80: 4013 ands r3, r2 8003a82: 0019 movs r1, r3 8003a84: 687b ldr r3, [r7, #4] 8003a86: 695b ldr r3, [r3, #20] 8003a88: 021a lsls r2, r3, #8 8003a8a: 4b6e ldr r3, [pc, #440] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a8c: 430a orrs r2, r1 8003a8e: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 8003a90: 69bb ldr r3, [r7, #24] 8003a92: 2b00 cmp r3, #0 8003a94: d112 bne.n 8003abc <HAL_RCC_OscConfig+0x1a4> { /* Adjust the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003a96: 4b6b ldr r3, [pc, #428] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003a98: 681b ldr r3, [r3, #0] 8003a9a: 4a6e ldr r2, [pc, #440] @ (8003c54 <HAL_RCC_OscConfig+0x33c>) 8003a9c: 4013 ands r3, r2 8003a9e: 0019 movs r1, r3 8003aa0: 687b ldr r3, [r7, #4] 8003aa2: 691a ldr r2, [r3, #16] 8003aa4: 4b67 ldr r3, [pc, #412] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003aa6: 430a orrs r2, r1 8003aa8: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 8003aaa: 4b66 ldr r3, [pc, #408] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003aac: 681b ldr r3, [r3, #0] 8003aae: 0adb lsrs r3, r3, #11 8003ab0: 2207 movs r2, #7 8003ab2: 4013 ands r3, r2 8003ab4: 4a68 ldr r2, [pc, #416] @ (8003c58 <HAL_RCC_OscConfig+0x340>) 8003ab6: 40da lsrs r2, r3 8003ab8: 4b68 ldr r3, [pc, #416] @ (8003c5c <HAL_RCC_OscConfig+0x344>) 8003aba: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8003abc: 4b68 ldr r3, [pc, #416] @ (8003c60 <HAL_RCC_OscConfig+0x348>) 8003abe: 681b ldr r3, [r3, #0] 8003ac0: 0018 movs r0, r3 8003ac2: f7ff fb61 bl 8003188 <HAL_InitTick> 8003ac6: 1e03 subs r3, r0, #0 8003ac8: d051 beq.n 8003b6e <HAL_RCC_OscConfig+0x256> { return HAL_ERROR; 8003aca: 2301 movs r3, #1 8003acc: e22c b.n 8003f28 <HAL_RCC_OscConfig+0x610> } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003ace: 687b ldr r3, [r7, #4] 8003ad0: 68db ldr r3, [r3, #12] 8003ad2: 2b00 cmp r3, #0 8003ad4: d030 beq.n 8003b38 <HAL_RCC_OscConfig+0x220> { /* Configure the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003ad6: 4b5b ldr r3, [pc, #364] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003ad8: 681b ldr r3, [r3, #0] 8003ada: 4a5e ldr r2, [pc, #376] @ (8003c54 <HAL_RCC_OscConfig+0x33c>) 8003adc: 4013 ands r3, r2 8003ade: 0019 movs r1, r3 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 691a ldr r2, [r3, #16] 8003ae4: 4b57 ldr r3, [pc, #348] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003ae6: 430a orrs r2, r1 8003ae8: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_ENABLE(); 8003aea: 4b56 ldr r3, [pc, #344] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003aec: 681a ldr r2, [r3, #0] 8003aee: 4b55 ldr r3, [pc, #340] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003af0: 2180 movs r1, #128 @ 0x80 8003af2: 0049 lsls r1, r1, #1 8003af4: 430a orrs r2, r1 8003af6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003af8: f7ff fba2 bl 8003240 <HAL_GetTick> 8003afc: 0003 movs r3, r0 8003afe: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003b00: e008 b.n 8003b14 <HAL_RCC_OscConfig+0x1fc> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003b02: f7ff fb9d bl 8003240 <HAL_GetTick> 8003b06: 0002 movs r2, r0 8003b08: 693b ldr r3, [r7, #16] 8003b0a: 1ad3 subs r3, r2, r3 8003b0c: 2b02 cmp r3, #2 8003b0e: d901 bls.n 8003b14 <HAL_RCC_OscConfig+0x1fc> { return HAL_TIMEOUT; 8003b10: 2303 movs r3, #3 8003b12: e209 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003b14: 4b4b ldr r3, [pc, #300] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b16: 681a ldr r2, [r3, #0] 8003b18: 2380 movs r3, #128 @ 0x80 8003b1a: 00db lsls r3, r3, #3 8003b1c: 4013 ands r3, r2 8003b1e: d0f0 beq.n 8003b02 <HAL_RCC_OscConfig+0x1ea> } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003b20: 4b48 ldr r3, [pc, #288] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b22: 685b ldr r3, [r3, #4] 8003b24: 4a4a ldr r2, [pc, #296] @ (8003c50 <HAL_RCC_OscConfig+0x338>) 8003b26: 4013 ands r3, r2 8003b28: 0019 movs r1, r3 8003b2a: 687b ldr r3, [r7, #4] 8003b2c: 695b ldr r3, [r3, #20] 8003b2e: 021a lsls r2, r3, #8 8003b30: 4b44 ldr r3, [pc, #272] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b32: 430a orrs r2, r1 8003b34: 605a str r2, [r3, #4] 8003b36: e01b b.n 8003b70 <HAL_RCC_OscConfig+0x258> } else { /* Disable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_DISABLE(); 8003b38: 4b42 ldr r3, [pc, #264] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b3a: 681a ldr r2, [r3, #0] 8003b3c: 4b41 ldr r3, [pc, #260] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b3e: 4949 ldr r1, [pc, #292] @ (8003c64 <HAL_RCC_OscConfig+0x34c>) 8003b40: 400a ands r2, r1 8003b42: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003b44: f7ff fb7c bl 8003240 <HAL_GetTick> 8003b48: 0003 movs r3, r0 8003b4a: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8003b4c: e008 b.n 8003b60 <HAL_RCC_OscConfig+0x248> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003b4e: f7ff fb77 bl 8003240 <HAL_GetTick> 8003b52: 0002 movs r2, r0 8003b54: 693b ldr r3, [r7, #16] 8003b56: 1ad3 subs r3, r2, r3 8003b58: 2b02 cmp r3, #2 8003b5a: d901 bls.n 8003b60 <HAL_RCC_OscConfig+0x248> { return HAL_TIMEOUT; 8003b5c: 2303 movs r3, #3 8003b5e: e1e3 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8003b60: 4b38 ldr r3, [pc, #224] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b62: 681a ldr r2, [r3, #0] 8003b64: 2380 movs r3, #128 @ 0x80 8003b66: 00db lsls r3, r3, #3 8003b68: 4013 ands r3, r2 8003b6a: d1f0 bne.n 8003b4e <HAL_RCC_OscConfig+0x236> 8003b6c: e000 b.n 8003b70 <HAL_RCC_OscConfig+0x258> if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003b6e: 46c0 nop @ (mov r8, r8) } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003b70: 687b ldr r3, [r7, #4] 8003b72: 681b ldr r3, [r3, #0] 8003b74: 2208 movs r2, #8 8003b76: 4013 ands r3, r2 8003b78: d047 beq.n 8003c0a <HAL_RCC_OscConfig+0x2f2> { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8003b7a: 4b32 ldr r3, [pc, #200] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b7c: 689b ldr r3, [r3, #8] 8003b7e: 2238 movs r2, #56 @ 0x38 8003b80: 4013 ands r3, r2 8003b82: 2b18 cmp r3, #24 8003b84: d10a bne.n 8003b9c <HAL_RCC_OscConfig+0x284> { /* When LSI is used as system clock it will not be disabled */ if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) 8003b86: 4b2f ldr r3, [pc, #188] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003b88: 6e1b ldr r3, [r3, #96] @ 0x60 8003b8a: 2202 movs r2, #2 8003b8c: 4013 ands r3, r2 8003b8e: d03c beq.n 8003c0a <HAL_RCC_OscConfig+0x2f2> 8003b90: 687b ldr r3, [r7, #4] 8003b92: 699b ldr r3, [r3, #24] 8003b94: 2b00 cmp r3, #0 8003b96: d138 bne.n 8003c0a <HAL_RCC_OscConfig+0x2f2> { return HAL_ERROR; 8003b98: 2301 movs r3, #1 8003b9a: e1c5 b.n 8003f28 <HAL_RCC_OscConfig+0x610> } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8003b9c: 687b ldr r3, [r7, #4] 8003b9e: 699b ldr r3, [r3, #24] 8003ba0: 2b00 cmp r3, #0 8003ba2: d019 beq.n 8003bd8 <HAL_RCC_OscConfig+0x2c0> { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003ba4: 4b27 ldr r3, [pc, #156] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003ba6: 6e1a ldr r2, [r3, #96] @ 0x60 8003ba8: 4b26 ldr r3, [pc, #152] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003baa: 2101 movs r1, #1 8003bac: 430a orrs r2, r1 8003bae: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003bb0: f7ff fb46 bl 8003240 <HAL_GetTick> 8003bb4: 0003 movs r3, r0 8003bb6: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003bb8: e008 b.n 8003bcc <HAL_RCC_OscConfig+0x2b4> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003bba: f7ff fb41 bl 8003240 <HAL_GetTick> 8003bbe: 0002 movs r2, r0 8003bc0: 693b ldr r3, [r7, #16] 8003bc2: 1ad3 subs r3, r2, r3 8003bc4: 2b02 cmp r3, #2 8003bc6: d901 bls.n 8003bcc <HAL_RCC_OscConfig+0x2b4> { return HAL_TIMEOUT; 8003bc8: 2303 movs r3, #3 8003bca: e1ad b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003bcc: 4b1d ldr r3, [pc, #116] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003bce: 6e1b ldr r3, [r3, #96] @ 0x60 8003bd0: 2202 movs r2, #2 8003bd2: 4013 ands r3, r2 8003bd4: d0f1 beq.n 8003bba <HAL_RCC_OscConfig+0x2a2> 8003bd6: e018 b.n 8003c0a <HAL_RCC_OscConfig+0x2f2> } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003bd8: 4b1a ldr r3, [pc, #104] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003bda: 6e1a ldr r2, [r3, #96] @ 0x60 8003bdc: 4b19 ldr r3, [pc, #100] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003bde: 2101 movs r1, #1 8003be0: 438a bics r2, r1 8003be2: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003be4: f7ff fb2c bl 8003240 <HAL_GetTick> 8003be8: 0003 movs r3, r0 8003bea: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003bec: e008 b.n 8003c00 <HAL_RCC_OscConfig+0x2e8> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003bee: f7ff fb27 bl 8003240 <HAL_GetTick> 8003bf2: 0002 movs r2, r0 8003bf4: 693b ldr r3, [r7, #16] 8003bf6: 1ad3 subs r3, r2, r3 8003bf8: 2b02 cmp r3, #2 8003bfa: d901 bls.n 8003c00 <HAL_RCC_OscConfig+0x2e8> { return HAL_TIMEOUT; 8003bfc: 2303 movs r3, #3 8003bfe: e193 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003c00: 4b10 ldr r3, [pc, #64] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003c02: 6e1b ldr r3, [r3, #96] @ 0x60 8003c04: 2202 movs r2, #2 8003c06: 4013 ands r3, r2 8003c08: d1f1 bne.n 8003bee <HAL_RCC_OscConfig+0x2d6> } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003c0a: 687b ldr r3, [r7, #4] 8003c0c: 681b ldr r3, [r3, #0] 8003c0e: 2204 movs r2, #4 8003c10: 4013 ands r3, r2 8003c12: d100 bne.n 8003c16 <HAL_RCC_OscConfig+0x2fe> 8003c14: e0c6 b.n 8003da4 <HAL_RCC_OscConfig+0x48c> { FlagStatus pwrclkchanged = RESET; 8003c16: 231f movs r3, #31 8003c18: 18fb adds r3, r7, r3 8003c1a: 2200 movs r2, #0 8003c1c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8003c1e: 4b09 ldr r3, [pc, #36] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003c20: 689b ldr r3, [r3, #8] 8003c22: 2238 movs r2, #56 @ 0x38 8003c24: 4013 ands r3, r2 8003c26: 2b20 cmp r3, #32 8003c28: d11e bne.n 8003c68 <HAL_RCC_OscConfig+0x350> { if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) 8003c2a: 4b06 ldr r3, [pc, #24] @ (8003c44 <HAL_RCC_OscConfig+0x32c>) 8003c2c: 6ddb ldr r3, [r3, #92] @ 0x5c 8003c2e: 2202 movs r2, #2 8003c30: 4013 ands r3, r2 8003c32: d100 bne.n 8003c36 <HAL_RCC_OscConfig+0x31e> 8003c34: e0b6 b.n 8003da4 <HAL_RCC_OscConfig+0x48c> 8003c36: 687b ldr r3, [r7, #4] 8003c38: 689b ldr r3, [r3, #8] 8003c3a: 2b00 cmp r3, #0 8003c3c: d000 beq.n 8003c40 <HAL_RCC_OscConfig+0x328> 8003c3e: e0b1 b.n 8003da4 <HAL_RCC_OscConfig+0x48c> { return HAL_ERROR; 8003c40: 2301 movs r3, #1 8003c42: e171 b.n 8003f28 <HAL_RCC_OscConfig+0x610> 8003c44: 40021000 .word 0x40021000 8003c48: fffeffff .word 0xfffeffff 8003c4c: fffbffff .word 0xfffbffff 8003c50: ffff80ff .word 0xffff80ff 8003c54: ffffc7ff .word 0xffffc7ff 8003c58: 00f42400 .word 0x00f42400 8003c5c: 20000014 .word 0x20000014 8003c60: 20000018 .word 0x20000018 8003c64: fffffeff .word 0xfffffeff } else { /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8003c68: 4bb1 ldr r3, [pc, #708] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003c6a: 6bda ldr r2, [r3, #60] @ 0x3c 8003c6c: 2380 movs r3, #128 @ 0x80 8003c6e: 055b lsls r3, r3, #21 8003c70: 4013 ands r3, r2 8003c72: d101 bne.n 8003c78 <HAL_RCC_OscConfig+0x360> 8003c74: 2301 movs r3, #1 8003c76: e000 b.n 8003c7a <HAL_RCC_OscConfig+0x362> 8003c78: 2300 movs r3, #0 8003c7a: 2b00 cmp r3, #0 8003c7c: d011 beq.n 8003ca2 <HAL_RCC_OscConfig+0x38a> { __HAL_RCC_PWR_CLK_ENABLE(); 8003c7e: 4bac ldr r3, [pc, #688] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003c80: 6bda ldr r2, [r3, #60] @ 0x3c 8003c82: 4bab ldr r3, [pc, #684] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003c84: 2180 movs r1, #128 @ 0x80 8003c86: 0549 lsls r1, r1, #21 8003c88: 430a orrs r2, r1 8003c8a: 63da str r2, [r3, #60] @ 0x3c 8003c8c: 4ba8 ldr r3, [pc, #672] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003c8e: 6bda ldr r2, [r3, #60] @ 0x3c 8003c90: 2380 movs r3, #128 @ 0x80 8003c92: 055b lsls r3, r3, #21 8003c94: 4013 ands r3, r2 8003c96: 60fb str r3, [r7, #12] 8003c98: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8003c9a: 231f movs r3, #31 8003c9c: 18fb adds r3, r7, r3 8003c9e: 2201 movs r2, #1 8003ca0: 701a strb r2, [r3, #0] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003ca2: 4ba4 ldr r3, [pc, #656] @ (8003f34 <HAL_RCC_OscConfig+0x61c>) 8003ca4: 681a ldr r2, [r3, #0] 8003ca6: 2380 movs r3, #128 @ 0x80 8003ca8: 005b lsls r3, r3, #1 8003caa: 4013 ands r3, r2 8003cac: d11a bne.n 8003ce4 <HAL_RCC_OscConfig+0x3cc> { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003cae: 4ba1 ldr r3, [pc, #644] @ (8003f34 <HAL_RCC_OscConfig+0x61c>) 8003cb0: 681a ldr r2, [r3, #0] 8003cb2: 4ba0 ldr r3, [pc, #640] @ (8003f34 <HAL_RCC_OscConfig+0x61c>) 8003cb4: 2180 movs r1, #128 @ 0x80 8003cb6: 0049 lsls r1, r1, #1 8003cb8: 430a orrs r2, r1 8003cba: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003cbc: f7ff fac0 bl 8003240 <HAL_GetTick> 8003cc0: 0003 movs r3, r0 8003cc2: 613b str r3, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003cc4: e008 b.n 8003cd8 <HAL_RCC_OscConfig+0x3c0> { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003cc6: f7ff fabb bl 8003240 <HAL_GetTick> 8003cca: 0002 movs r2, r0 8003ccc: 693b ldr r3, [r7, #16] 8003cce: 1ad3 subs r3, r2, r3 8003cd0: 2b02 cmp r3, #2 8003cd2: d901 bls.n 8003cd8 <HAL_RCC_OscConfig+0x3c0> { return HAL_TIMEOUT; 8003cd4: 2303 movs r3, #3 8003cd6: e127 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003cd8: 4b96 ldr r3, [pc, #600] @ (8003f34 <HAL_RCC_OscConfig+0x61c>) 8003cda: 681a ldr r2, [r3, #0] 8003cdc: 2380 movs r3, #128 @ 0x80 8003cde: 005b lsls r3, r3, #1 8003ce0: 4013 ands r3, r2 8003ce2: d0f0 beq.n 8003cc6 <HAL_RCC_OscConfig+0x3ae> } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003ce4: 687b ldr r3, [r7, #4] 8003ce6: 689b ldr r3, [r3, #8] 8003ce8: 2b01 cmp r3, #1 8003cea: d106 bne.n 8003cfa <HAL_RCC_OscConfig+0x3e2> 8003cec: 4b90 ldr r3, [pc, #576] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003cee: 6dda ldr r2, [r3, #92] @ 0x5c 8003cf0: 4b8f ldr r3, [pc, #572] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003cf2: 2101 movs r1, #1 8003cf4: 430a orrs r2, r1 8003cf6: 65da str r2, [r3, #92] @ 0x5c 8003cf8: e01c b.n 8003d34 <HAL_RCC_OscConfig+0x41c> 8003cfa: 687b ldr r3, [r7, #4] 8003cfc: 689b ldr r3, [r3, #8] 8003cfe: 2b05 cmp r3, #5 8003d00: d10c bne.n 8003d1c <HAL_RCC_OscConfig+0x404> 8003d02: 4b8b ldr r3, [pc, #556] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d04: 6dda ldr r2, [r3, #92] @ 0x5c 8003d06: 4b8a ldr r3, [pc, #552] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d08: 2104 movs r1, #4 8003d0a: 430a orrs r2, r1 8003d0c: 65da str r2, [r3, #92] @ 0x5c 8003d0e: 4b88 ldr r3, [pc, #544] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d10: 6dda ldr r2, [r3, #92] @ 0x5c 8003d12: 4b87 ldr r3, [pc, #540] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d14: 2101 movs r1, #1 8003d16: 430a orrs r2, r1 8003d18: 65da str r2, [r3, #92] @ 0x5c 8003d1a: e00b b.n 8003d34 <HAL_RCC_OscConfig+0x41c> 8003d1c: 4b84 ldr r3, [pc, #528] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d1e: 6dda ldr r2, [r3, #92] @ 0x5c 8003d20: 4b83 ldr r3, [pc, #524] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d22: 2101 movs r1, #1 8003d24: 438a bics r2, r1 8003d26: 65da str r2, [r3, #92] @ 0x5c 8003d28: 4b81 ldr r3, [pc, #516] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d2a: 6dda ldr r2, [r3, #92] @ 0x5c 8003d2c: 4b80 ldr r3, [pc, #512] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d2e: 2104 movs r1, #4 8003d30: 438a bics r2, r1 8003d32: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003d34: 687b ldr r3, [r7, #4] 8003d36: 689b ldr r3, [r3, #8] 8003d38: 2b00 cmp r3, #0 8003d3a: d014 beq.n 8003d66 <HAL_RCC_OscConfig+0x44e> { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003d3c: f7ff fa80 bl 8003240 <HAL_GetTick> 8003d40: 0003 movs r3, r0 8003d42: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003d44: e009 b.n 8003d5a <HAL_RCC_OscConfig+0x442> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003d46: f7ff fa7b bl 8003240 <HAL_GetTick> 8003d4a: 0002 movs r2, r0 8003d4c: 693b ldr r3, [r7, #16] 8003d4e: 1ad3 subs r3, r2, r3 8003d50: 4a79 ldr r2, [pc, #484] @ (8003f38 <HAL_RCC_OscConfig+0x620>) 8003d52: 4293 cmp r3, r2 8003d54: d901 bls.n 8003d5a <HAL_RCC_OscConfig+0x442> { return HAL_TIMEOUT; 8003d56: 2303 movs r3, #3 8003d58: e0e6 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003d5a: 4b75 ldr r3, [pc, #468] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d5c: 6ddb ldr r3, [r3, #92] @ 0x5c 8003d5e: 2202 movs r2, #2 8003d60: 4013 ands r3, r2 8003d62: d0f0 beq.n 8003d46 <HAL_RCC_OscConfig+0x42e> 8003d64: e013 b.n 8003d8e <HAL_RCC_OscConfig+0x476> } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003d66: f7ff fa6b bl 8003240 <HAL_GetTick> 8003d6a: 0003 movs r3, r0 8003d6c: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003d6e: e009 b.n 8003d84 <HAL_RCC_OscConfig+0x46c> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003d70: f7ff fa66 bl 8003240 <HAL_GetTick> 8003d74: 0002 movs r2, r0 8003d76: 693b ldr r3, [r7, #16] 8003d78: 1ad3 subs r3, r2, r3 8003d7a: 4a6f ldr r2, [pc, #444] @ (8003f38 <HAL_RCC_OscConfig+0x620>) 8003d7c: 4293 cmp r3, r2 8003d7e: d901 bls.n 8003d84 <HAL_RCC_OscConfig+0x46c> { return HAL_TIMEOUT; 8003d80: 2303 movs r3, #3 8003d82: e0d1 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003d84: 4b6a ldr r3, [pc, #424] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d86: 6ddb ldr r3, [r3, #92] @ 0x5c 8003d88: 2202 movs r2, #2 8003d8a: 4013 ands r3, r2 8003d8c: d1f0 bne.n 8003d70 <HAL_RCC_OscConfig+0x458> } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8003d8e: 231f movs r3, #31 8003d90: 18fb adds r3, r7, r3 8003d92: 781b ldrb r3, [r3, #0] 8003d94: 2b01 cmp r3, #1 8003d96: d105 bne.n 8003da4 <HAL_RCC_OscConfig+0x48c> { __HAL_RCC_PWR_CLK_DISABLE(); 8003d98: 4b65 ldr r3, [pc, #404] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d9a: 6bda ldr r2, [r3, #60] @ 0x3c 8003d9c: 4b64 ldr r3, [pc, #400] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003d9e: 4967 ldr r1, [pc, #412] @ (8003f3c <HAL_RCC_OscConfig+0x624>) 8003da0: 400a ands r2, r1 8003da2: 63da str r2, [r3, #60] @ 0x3c #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8003da4: 687b ldr r3, [r7, #4] 8003da6: 69db ldr r3, [r3, #28] 8003da8: 2b00 cmp r3, #0 8003daa: d100 bne.n 8003dae <HAL_RCC_OscConfig+0x496> 8003dac: e0bb b.n 8003f26 <HAL_RCC_OscConfig+0x60e> { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003dae: 4b60 ldr r3, [pc, #384] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003db0: 689b ldr r3, [r3, #8] 8003db2: 2238 movs r2, #56 @ 0x38 8003db4: 4013 ands r3, r2 8003db6: 2b10 cmp r3, #16 8003db8: d100 bne.n 8003dbc <HAL_RCC_OscConfig+0x4a4> 8003dba: e07b b.n 8003eb4 <HAL_RCC_OscConfig+0x59c> { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8003dbc: 687b ldr r3, [r7, #4] 8003dbe: 69db ldr r3, [r3, #28] 8003dc0: 2b02 cmp r3, #2 8003dc2: d156 bne.n 8003e72 <HAL_RCC_OscConfig+0x55a> assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); #endif /* RCC_PLLQ_SUPPORT */ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003dc4: 4b5a ldr r3, [pc, #360] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003dc6: 681a ldr r2, [r3, #0] 8003dc8: 4b59 ldr r3, [pc, #356] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003dca: 495d ldr r1, [pc, #372] @ (8003f40 <HAL_RCC_OscConfig+0x628>) 8003dcc: 400a ands r2, r1 8003dce: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003dd0: f7ff fa36 bl 8003240 <HAL_GetTick> 8003dd4: 0003 movs r3, r0 8003dd6: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003dd8: e008 b.n 8003dec <HAL_RCC_OscConfig+0x4d4> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003dda: f7ff fa31 bl 8003240 <HAL_GetTick> 8003dde: 0002 movs r2, r0 8003de0: 693b ldr r3, [r7, #16] 8003de2: 1ad3 subs r3, r2, r3 8003de4: 2b02 cmp r3, #2 8003de6: d901 bls.n 8003dec <HAL_RCC_OscConfig+0x4d4> { return HAL_TIMEOUT; 8003de8: 2303 movs r3, #3 8003dea: e09d b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003dec: 4b50 ldr r3, [pc, #320] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003dee: 681a ldr r2, [r3, #0] 8003df0: 2380 movs r3, #128 @ 0x80 8003df2: 049b lsls r3, r3, #18 8003df4: 4013 ands r3, r2 8003df6: d1f0 bne.n 8003dda <HAL_RCC_OscConfig+0x4c2> } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined(RCC_PLLQ_SUPPORT) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003df8: 4b4d ldr r3, [pc, #308] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003dfa: 68db ldr r3, [r3, #12] 8003dfc: 4a51 ldr r2, [pc, #324] @ (8003f44 <HAL_RCC_OscConfig+0x62c>) 8003dfe: 4013 ands r3, r2 8003e00: 0019 movs r1, r3 8003e02: 687b ldr r3, [r7, #4] 8003e04: 6a1a ldr r2, [r3, #32] 8003e06: 687b ldr r3, [r7, #4] 8003e08: 6a5b ldr r3, [r3, #36] @ 0x24 8003e0a: 431a orrs r2, r3 8003e0c: 687b ldr r3, [r7, #4] 8003e0e: 6a9b ldr r3, [r3, #40] @ 0x28 8003e10: 021b lsls r3, r3, #8 8003e12: 431a orrs r2, r3 8003e14: 687b ldr r3, [r7, #4] 8003e16: 6adb ldr r3, [r3, #44] @ 0x2c 8003e18: 431a orrs r2, r3 8003e1a: 687b ldr r3, [r7, #4] 8003e1c: 6b1b ldr r3, [r3, #48] @ 0x30 8003e1e: 431a orrs r2, r3 8003e20: 687b ldr r3, [r7, #4] 8003e22: 6b5b ldr r3, [r3, #52] @ 0x34 8003e24: 431a orrs r2, r3 8003e26: 4b42 ldr r3, [pc, #264] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e28: 430a orrs r2, r1 8003e2a: 60da str r2, [r3, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLR); #endif /* RCC_PLLQ_SUPPORT */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003e2c: 4b40 ldr r3, [pc, #256] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e2e: 681a ldr r2, [r3, #0] 8003e30: 4b3f ldr r3, [pc, #252] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e32: 2180 movs r1, #128 @ 0x80 8003e34: 0449 lsls r1, r1, #17 8003e36: 430a orrs r2, r1 8003e38: 601a str r2, [r3, #0] /* Enable PLLR Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); 8003e3a: 4b3d ldr r3, [pc, #244] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e3c: 68da ldr r2, [r3, #12] 8003e3e: 4b3c ldr r3, [pc, #240] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e40: 2180 movs r1, #128 @ 0x80 8003e42: 0549 lsls r1, r1, #21 8003e44: 430a orrs r2, r1 8003e46: 60da str r2, [r3, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e48: f7ff f9fa bl 8003240 <HAL_GetTick> 8003e4c: 0003 movs r3, r0 8003e4e: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003e50: e008 b.n 8003e64 <HAL_RCC_OscConfig+0x54c> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003e52: f7ff f9f5 bl 8003240 <HAL_GetTick> 8003e56: 0002 movs r2, r0 8003e58: 693b ldr r3, [r7, #16] 8003e5a: 1ad3 subs r3, r2, r3 8003e5c: 2b02 cmp r3, #2 8003e5e: d901 bls.n 8003e64 <HAL_RCC_OscConfig+0x54c> { return HAL_TIMEOUT; 8003e60: 2303 movs r3, #3 8003e62: e061 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003e64: 4b32 ldr r3, [pc, #200] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e66: 681a ldr r2, [r3, #0] 8003e68: 2380 movs r3, #128 @ 0x80 8003e6a: 049b lsls r3, r3, #18 8003e6c: 4013 ands r3, r2 8003e6e: d0f0 beq.n 8003e52 <HAL_RCC_OscConfig+0x53a> 8003e70: e059 b.n 8003f26 <HAL_RCC_OscConfig+0x60e> } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003e72: 4b2f ldr r3, [pc, #188] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e74: 681a ldr r2, [r3, #0] 8003e76: 4b2e ldr r3, [pc, #184] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e78: 4931 ldr r1, [pc, #196] @ (8003f40 <HAL_RCC_OscConfig+0x628>) 8003e7a: 400a ands r2, r1 8003e7c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e7e: f7ff f9df bl 8003240 <HAL_GetTick> 8003e82: 0003 movs r3, r0 8003e84: 613b str r3, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003e86: e008 b.n 8003e9a <HAL_RCC_OscConfig+0x582> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003e88: f7ff f9da bl 8003240 <HAL_GetTick> 8003e8c: 0002 movs r2, r0 8003e8e: 693b ldr r3, [r7, #16] 8003e90: 1ad3 subs r3, r2, r3 8003e92: 2b02 cmp r3, #2 8003e94: d901 bls.n 8003e9a <HAL_RCC_OscConfig+0x582> { return HAL_TIMEOUT; 8003e96: 2303 movs r3, #3 8003e98: e046 b.n 8003f28 <HAL_RCC_OscConfig+0x610> while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003e9a: 4b25 ldr r3, [pc, #148] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003e9c: 681a ldr r2, [r3, #0] 8003e9e: 2380 movs r3, #128 @ 0x80 8003ea0: 049b lsls r3, r3, #18 8003ea2: 4013 ands r3, r2 8003ea4: d1f0 bne.n 8003e88 <HAL_RCC_OscConfig+0x570> } } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLQ_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); 8003ea6: 4b22 ldr r3, [pc, #136] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003ea8: 68da ldr r2, [r3, #12] 8003eaa: 4b21 ldr r3, [pc, #132] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003eac: 4926 ldr r1, [pc, #152] @ (8003f48 <HAL_RCC_OscConfig+0x630>) 8003eae: 400a ands r2, r1 8003eb0: 60da str r2, [r3, #12] 8003eb2: e038 b.n 8003f26 <HAL_RCC_OscConfig+0x60e> } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003eb4: 687b ldr r3, [r7, #4] 8003eb6: 69db ldr r3, [r3, #28] 8003eb8: 2b01 cmp r3, #1 8003eba: d101 bne.n 8003ec0 <HAL_RCC_OscConfig+0x5a8> { return HAL_ERROR; 8003ebc: 2301 movs r3, #1 8003ebe: e033 b.n 8003f28 <HAL_RCC_OscConfig+0x610> } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 8003ec0: 4b1b ldr r3, [pc, #108] @ (8003f30 <HAL_RCC_OscConfig+0x618>) 8003ec2: 68db ldr r3, [r3, #12] 8003ec4: 617b str r3, [r7, #20] if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003ec6: 697b ldr r3, [r7, #20] 8003ec8: 2203 movs r2, #3 8003eca: 401a ands r2, r3 8003ecc: 687b ldr r3, [r7, #4] 8003ece: 6a1b ldr r3, [r3, #32] 8003ed0: 429a cmp r2, r3 8003ed2: d126 bne.n 8003f22 <HAL_RCC_OscConfig+0x60a> (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003ed4: 697b ldr r3, [r7, #20] 8003ed6: 2270 movs r2, #112 @ 0x70 8003ed8: 401a ands r2, r3 8003eda: 687b ldr r3, [r7, #4] 8003edc: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003ede: 429a cmp r2, r3 8003ee0: d11f bne.n 8003f22 <HAL_RCC_OscConfig+0x60a> (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003ee2: 697a ldr r2, [r7, #20] 8003ee4: 23fe movs r3, #254 @ 0xfe 8003ee6: 01db lsls r3, r3, #7 8003ee8: 401a ands r2, r3 8003eea: 687b ldr r3, [r7, #4] 8003eec: 6a9b ldr r3, [r3, #40] @ 0x28 8003eee: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003ef0: 429a cmp r2, r3 8003ef2: d116 bne.n 8003f22 <HAL_RCC_OscConfig+0x60a> (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003ef4: 697a ldr r2, [r7, #20] 8003ef6: 23f8 movs r3, #248 @ 0xf8 8003ef8: 039b lsls r3, r3, #14 8003efa: 401a ands r2, r3 8003efc: 687b ldr r3, [r7, #4] 8003efe: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003f00: 429a cmp r2, r3 8003f02: d10e bne.n 8003f22 <HAL_RCC_OscConfig+0x60a> #if defined (RCC_PLLQ_SUPPORT) (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 8003f04: 697a ldr r2, [r7, #20] 8003f06: 23e0 movs r3, #224 @ 0xe0 8003f08: 051b lsls r3, r3, #20 8003f0a: 401a ands r2, r3 8003f0c: 687b ldr r3, [r7, #4] 8003f0e: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003f10: 429a cmp r2, r3 8003f12: d106 bne.n 8003f22 <HAL_RCC_OscConfig+0x60a> #endif /* RCC_PLLQ_SUPPORT */ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 8003f14: 697b ldr r3, [r7, #20] 8003f16: 0f5b lsrs r3, r3, #29 8003f18: 075a lsls r2, r3, #29 8003f1a: 687b ldr r3, [r7, #4] 8003f1c: 6b5b ldr r3, [r3, #52] @ 0x34 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 8003f1e: 429a cmp r2, r3 8003f20: d001 beq.n 8003f26 <HAL_RCC_OscConfig+0x60e> { return HAL_ERROR; 8003f22: 2301 movs r3, #1 8003f24: e000 b.n 8003f28 <HAL_RCC_OscConfig+0x610> } } } } return HAL_OK; 8003f26: 2300 movs r3, #0 } 8003f28: 0018 movs r0, r3 8003f2a: 46bd mov sp, r7 8003f2c: b008 add sp, #32 8003f2e: bd80 pop {r7, pc} 8003f30: 40021000 .word 0x40021000 8003f34: 40007000 .word 0x40007000 8003f38: 00001388 .word 0x00001388 8003f3c: efffffff .word 0xefffffff 8003f40: feffffff .word 0xfeffffff 8003f44: 11c1808c .word 0x11c1808c 8003f48: eefefffc .word 0xeefefffc 08003f4c <HAL_RCC_ClockConfig>: * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003f4c: b580 push {r7, lr} 8003f4e: b084 sub sp, #16 8003f50: af00 add r7, sp, #0 8003f52: 6078 str r0, [r7, #4] 8003f54: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003f56: 687b ldr r3, [r7, #4] 8003f58: 2b00 cmp r3, #0 8003f5a: d101 bne.n 8003f60 <HAL_RCC_ClockConfig+0x14> { return HAL_ERROR; 8003f5c: 2301 movs r3, #1 8003f5e: e0e9 b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003f60: 4b76 ldr r3, [pc, #472] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 8003f62: 681b ldr r3, [r3, #0] 8003f64: 2207 movs r2, #7 8003f66: 4013 ands r3, r2 8003f68: 683a ldr r2, [r7, #0] 8003f6a: 429a cmp r2, r3 8003f6c: d91e bls.n 8003fac <HAL_RCC_ClockConfig+0x60> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003f6e: 4b73 ldr r3, [pc, #460] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 8003f70: 681b ldr r3, [r3, #0] 8003f72: 2207 movs r2, #7 8003f74: 4393 bics r3, r2 8003f76: 0019 movs r1, r3 8003f78: 4b70 ldr r3, [pc, #448] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 8003f7a: 683a ldr r2, [r7, #0] 8003f7c: 430a orrs r2, r1 8003f7e: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8003f80: f7ff f95e bl 8003240 <HAL_GetTick> 8003f84: 0003 movs r3, r0 8003f86: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003f88: e009 b.n 8003f9e <HAL_RCC_ClockConfig+0x52> { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003f8a: f7ff f959 bl 8003240 <HAL_GetTick> 8003f8e: 0002 movs r2, r0 8003f90: 68fb ldr r3, [r7, #12] 8003f92: 1ad3 subs r3, r2, r3 8003f94: 4a6a ldr r2, [pc, #424] @ (8004140 <HAL_RCC_ClockConfig+0x1f4>) 8003f96: 4293 cmp r3, r2 8003f98: d901 bls.n 8003f9e <HAL_RCC_ClockConfig+0x52> { return HAL_TIMEOUT; 8003f9a: 2303 movs r3, #3 8003f9c: e0ca b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003f9e: 4b67 ldr r3, [pc, #412] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 8003fa0: 681b ldr r3, [r3, #0] 8003fa2: 2207 movs r2, #7 8003fa4: 4013 ands r3, r2 8003fa6: 683a ldr r2, [r7, #0] 8003fa8: 429a cmp r2, r3 8003faa: d1ee bne.n 8003f8a <HAL_RCC_ClockConfig+0x3e> } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003fac: 687b ldr r3, [r7, #4] 8003fae: 681b ldr r3, [r3, #0] 8003fb0: 2202 movs r2, #2 8003fb2: 4013 ands r3, r2 8003fb4: d015 beq.n 8003fe2 <HAL_RCC_ClockConfig+0x96> { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003fb6: 687b ldr r3, [r7, #4] 8003fb8: 681b ldr r3, [r3, #0] 8003fba: 2204 movs r2, #4 8003fbc: 4013 ands r3, r2 8003fbe: d006 beq.n 8003fce <HAL_RCC_ClockConfig+0x82> { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8003fc0: 4b60 ldr r3, [pc, #384] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8003fc2: 689a ldr r2, [r3, #8] 8003fc4: 4b5f ldr r3, [pc, #380] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8003fc6: 21e0 movs r1, #224 @ 0xe0 8003fc8: 01c9 lsls r1, r1, #7 8003fca: 430a orrs r2, r1 8003fcc: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003fce: 4b5d ldr r3, [pc, #372] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8003fd0: 689b ldr r3, [r3, #8] 8003fd2: 4a5d ldr r2, [pc, #372] @ (8004148 <HAL_RCC_ClockConfig+0x1fc>) 8003fd4: 4013 ands r3, r2 8003fd6: 0019 movs r1, r3 8003fd8: 687b ldr r3, [r7, #4] 8003fda: 689a ldr r2, [r3, #8] 8003fdc: 4b59 ldr r3, [pc, #356] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8003fde: 430a orrs r2, r1 8003fe0: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003fe2: 687b ldr r3, [r7, #4] 8003fe4: 681b ldr r3, [r3, #0] 8003fe6: 2201 movs r2, #1 8003fe8: 4013 ands r3, r2 8003fea: d057 beq.n 800409c <HAL_RCC_ClockConfig+0x150> { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003fec: 687b ldr r3, [r7, #4] 8003fee: 685b ldr r3, [r3, #4] 8003ff0: 2b01 cmp r3, #1 8003ff2: d107 bne.n 8004004 <HAL_RCC_ClockConfig+0xb8> { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003ff4: 4b53 ldr r3, [pc, #332] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8003ff6: 681a ldr r2, [r3, #0] 8003ff8: 2380 movs r3, #128 @ 0x80 8003ffa: 029b lsls r3, r3, #10 8003ffc: 4013 ands r3, r2 8003ffe: d12b bne.n 8004058 <HAL_RCC_ClockConfig+0x10c> { return HAL_ERROR; 8004000: 2301 movs r3, #1 8004002: e097 b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8004004: 687b ldr r3, [r7, #4] 8004006: 685b ldr r3, [r3, #4] 8004008: 2b02 cmp r3, #2 800400a: d107 bne.n 800401c <HAL_RCC_ClockConfig+0xd0> { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800400c: 4b4d ldr r3, [pc, #308] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800400e: 681a ldr r2, [r3, #0] 8004010: 2380 movs r3, #128 @ 0x80 8004012: 049b lsls r3, r3, #18 8004014: 4013 ands r3, r2 8004016: d11f bne.n 8004058 <HAL_RCC_ClockConfig+0x10c> { return HAL_ERROR; 8004018: 2301 movs r3, #1 800401a: e08b b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 800401c: 687b ldr r3, [r7, #4] 800401e: 685b ldr r3, [r3, #4] 8004020: 2b00 cmp r3, #0 8004022: d107 bne.n 8004034 <HAL_RCC_ClockConfig+0xe8> { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8004024: 4b47 ldr r3, [pc, #284] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8004026: 681a ldr r2, [r3, #0] 8004028: 2380 movs r3, #128 @ 0x80 800402a: 00db lsls r3, r3, #3 800402c: 4013 ands r3, r2 800402e: d113 bne.n 8004058 <HAL_RCC_ClockConfig+0x10c> { return HAL_ERROR; 8004030: 2301 movs r3, #1 8004032: e07f b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> } } /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8004034: 687b ldr r3, [r7, #4] 8004036: 685b ldr r3, [r3, #4] 8004038: 2b03 cmp r3, #3 800403a: d106 bne.n 800404a <HAL_RCC_ClockConfig+0xfe> { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 800403c: 4b41 ldr r3, [pc, #260] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800403e: 6e1b ldr r3, [r3, #96] @ 0x60 8004040: 2202 movs r2, #2 8004042: 4013 ands r3, r2 8004044: d108 bne.n 8004058 <HAL_RCC_ClockConfig+0x10c> { return HAL_ERROR; 8004046: 2301 movs r3, #1 8004048: e074 b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800404a: 4b3e ldr r3, [pc, #248] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800404c: 6ddb ldr r3, [r3, #92] @ 0x5c 800404e: 2202 movs r2, #2 8004050: 4013 ands r3, r2 8004052: d101 bne.n 8004058 <HAL_RCC_ClockConfig+0x10c> { return HAL_ERROR; 8004054: 2301 movs r3, #1 8004056: e06d b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8004058: 4b3a ldr r3, [pc, #232] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800405a: 689b ldr r3, [r3, #8] 800405c: 2207 movs r2, #7 800405e: 4393 bics r3, r2 8004060: 0019 movs r1, r3 8004062: 687b ldr r3, [r7, #4] 8004064: 685a ldr r2, [r3, #4] 8004066: 4b37 ldr r3, [pc, #220] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8004068: 430a orrs r2, r1 800406a: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800406c: f7ff f8e8 bl 8003240 <HAL_GetTick> 8004070: 0003 movs r3, r0 8004072: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004074: e009 b.n 800408a <HAL_RCC_ClockConfig+0x13e> { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004076: f7ff f8e3 bl 8003240 <HAL_GetTick> 800407a: 0002 movs r2, r0 800407c: 68fb ldr r3, [r7, #12] 800407e: 1ad3 subs r3, r2, r3 8004080: 4a2f ldr r2, [pc, #188] @ (8004140 <HAL_RCC_ClockConfig+0x1f4>) 8004082: 4293 cmp r3, r2 8004084: d901 bls.n 800408a <HAL_RCC_ClockConfig+0x13e> { return HAL_TIMEOUT; 8004086: 2303 movs r3, #3 8004088: e054 b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800408a: 4b2e ldr r3, [pc, #184] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800408c: 689b ldr r3, [r3, #8] 800408e: 2238 movs r2, #56 @ 0x38 8004090: 401a ands r2, r3 8004092: 687b ldr r3, [r7, #4] 8004094: 685b ldr r3, [r3, #4] 8004096: 00db lsls r3, r3, #3 8004098: 429a cmp r2, r3 800409a: d1ec bne.n 8004076 <HAL_RCC_ClockConfig+0x12a> } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800409c: 4b27 ldr r3, [pc, #156] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 800409e: 681b ldr r3, [r3, #0] 80040a0: 2207 movs r2, #7 80040a2: 4013 ands r3, r2 80040a4: 683a ldr r2, [r7, #0] 80040a6: 429a cmp r2, r3 80040a8: d21e bcs.n 80040e8 <HAL_RCC_ClockConfig+0x19c> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80040aa: 4b24 ldr r3, [pc, #144] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 80040ac: 681b ldr r3, [r3, #0] 80040ae: 2207 movs r2, #7 80040b0: 4393 bics r3, r2 80040b2: 0019 movs r1, r3 80040b4: 4b21 ldr r3, [pc, #132] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 80040b6: 683a ldr r2, [r7, #0] 80040b8: 430a orrs r2, r1 80040ba: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 80040bc: f7ff f8c0 bl 8003240 <HAL_GetTick> 80040c0: 0003 movs r3, r0 80040c2: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80040c4: e009 b.n 80040da <HAL_RCC_ClockConfig+0x18e> { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80040c6: f7ff f8bb bl 8003240 <HAL_GetTick> 80040ca: 0002 movs r2, r0 80040cc: 68fb ldr r3, [r7, #12] 80040ce: 1ad3 subs r3, r2, r3 80040d0: 4a1b ldr r2, [pc, #108] @ (8004140 <HAL_RCC_ClockConfig+0x1f4>) 80040d2: 4293 cmp r3, r2 80040d4: d901 bls.n 80040da <HAL_RCC_ClockConfig+0x18e> { return HAL_TIMEOUT; 80040d6: 2303 movs r3, #3 80040d8: e02c b.n 8004134 <HAL_RCC_ClockConfig+0x1e8> while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80040da: 4b18 ldr r3, [pc, #96] @ (800413c <HAL_RCC_ClockConfig+0x1f0>) 80040dc: 681b ldr r3, [r3, #0] 80040de: 2207 movs r2, #7 80040e0: 4013 ands r3, r2 80040e2: 683a ldr r2, [r7, #0] 80040e4: 429a cmp r2, r3 80040e6: d1ee bne.n 80040c6 <HAL_RCC_ClockConfig+0x17a> } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80040e8: 687b ldr r3, [r7, #4] 80040ea: 681b ldr r3, [r3, #0] 80040ec: 2204 movs r2, #4 80040ee: 4013 ands r3, r2 80040f0: d009 beq.n 8004106 <HAL_RCC_ClockConfig+0x1ba> { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 80040f2: 4b14 ldr r3, [pc, #80] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 80040f4: 689b ldr r3, [r3, #8] 80040f6: 4a15 ldr r2, [pc, #84] @ (800414c <HAL_RCC_ClockConfig+0x200>) 80040f8: 4013 ands r3, r2 80040fa: 0019 movs r1, r3 80040fc: 687b ldr r3, [r7, #4] 80040fe: 68da ldr r2, [r3, #12] 8004100: 4b10 ldr r3, [pc, #64] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 8004102: 430a orrs r2, r1 8004104: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8004106: f000 f829 bl 800415c <HAL_RCC_GetSysClockFreq> 800410a: 0001 movs r1, r0 800410c: 4b0d ldr r3, [pc, #52] @ (8004144 <HAL_RCC_ClockConfig+0x1f8>) 800410e: 689b ldr r3, [r3, #8] 8004110: 0a1b lsrs r3, r3, #8 8004112: 220f movs r2, #15 8004114: 401a ands r2, r3 8004116: 4b0e ldr r3, [pc, #56] @ (8004150 <HAL_RCC_ClockConfig+0x204>) 8004118: 0092 lsls r2, r2, #2 800411a: 58d3 ldr r3, [r2, r3] 800411c: 221f movs r2, #31 800411e: 4013 ands r3, r2 8004120: 000a movs r2, r1 8004122: 40da lsrs r2, r3 8004124: 4b0b ldr r3, [pc, #44] @ (8004154 <HAL_RCC_ClockConfig+0x208>) 8004126: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8004128: 4b0b ldr r3, [pc, #44] @ (8004158 <HAL_RCC_ClockConfig+0x20c>) 800412a: 681b ldr r3, [r3, #0] 800412c: 0018 movs r0, r3 800412e: f7ff f82b bl 8003188 <HAL_InitTick> 8004132: 0003 movs r3, r0 } 8004134: 0018 movs r0, r3 8004136: 46bd mov sp, r7 8004138: b004 add sp, #16 800413a: bd80 pop {r7, pc} 800413c: 40022000 .word 0x40022000 8004140: 00001388 .word 0x00001388 8004144: 40021000 .word 0x40021000 8004148: fffff0ff .word 0xfffff0ff 800414c: ffff8fff .word 0xffff8fff 8004150: 08005b30 .word 0x08005b30 8004154: 20000014 .word 0x20000014 8004158: 20000018 .word 0x20000018 0800415c <HAL_RCC_GetSysClockFreq>: * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800415c: b580 push {r7, lr} 800415e: b086 sub sp, #24 8004160: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm, hsidiv; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8004162: 4b3c ldr r3, [pc, #240] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 8004164: 689b ldr r3, [r3, #8] 8004166: 2238 movs r2, #56 @ 0x38 8004168: 4013 ands r3, r2 800416a: d10f bne.n 800418c <HAL_RCC_GetSysClockFreq+0x30> { /* HSISYS can be derived for HSI16 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 800416c: 4b39 ldr r3, [pc, #228] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 800416e: 681b ldr r3, [r3, #0] 8004170: 0adb lsrs r3, r3, #11 8004172: 2207 movs r2, #7 8004174: 4013 ands r3, r2 8004176: 2201 movs r2, #1 8004178: 409a lsls r2, r3 800417a: 0013 movs r3, r2 800417c: 603b str r3, [r7, #0] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 800417e: 6839 ldr r1, [r7, #0] 8004180: 4835 ldr r0, [pc, #212] @ (8004258 <HAL_RCC_GetSysClockFreq+0xfc>) 8004182: f7fb ffbf bl 8000104 <__udivsi3> 8004186: 0003 movs r3, r0 8004188: 613b str r3, [r7, #16] 800418a: e05d b.n 8004248 <HAL_RCC_GetSysClockFreq+0xec> } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800418c: 4b31 ldr r3, [pc, #196] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 800418e: 689b ldr r3, [r3, #8] 8004190: 2238 movs r2, #56 @ 0x38 8004192: 4013 ands r3, r2 8004194: 2b08 cmp r3, #8 8004196: d102 bne.n 800419e <HAL_RCC_GetSysClockFreq+0x42> { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8004198: 4b30 ldr r3, [pc, #192] @ (800425c <HAL_RCC_GetSysClockFreq+0x100>) 800419a: 613b str r3, [r7, #16] 800419c: e054 b.n 8004248 <HAL_RCC_GetSysClockFreq+0xec> } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800419e: 4b2d ldr r3, [pc, #180] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 80041a0: 689b ldr r3, [r3, #8] 80041a2: 2238 movs r2, #56 @ 0x38 80041a4: 4013 ands r3, r2 80041a6: 2b10 cmp r3, #16 80041a8: d138 bne.n 800421c <HAL_RCC_GetSysClockFreq+0xc0> /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 80041aa: 4b2a ldr r3, [pc, #168] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 80041ac: 68db ldr r3, [r3, #12] 80041ae: 2203 movs r2, #3 80041b0: 4013 ands r3, r2 80041b2: 60fb str r3, [r7, #12] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80041b4: 4b27 ldr r3, [pc, #156] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 80041b6: 68db ldr r3, [r3, #12] 80041b8: 091b lsrs r3, r3, #4 80041ba: 2207 movs r2, #7 80041bc: 4013 ands r3, r2 80041be: 3301 adds r3, #1 80041c0: 60bb str r3, [r7, #8] switch (pllsource) 80041c2: 68fb ldr r3, [r7, #12] 80041c4: 2b03 cmp r3, #3 80041c6: d10d bne.n 80041e4 <HAL_RCC_GetSysClockFreq+0x88> { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80041c8: 68b9 ldr r1, [r7, #8] 80041ca: 4824 ldr r0, [pc, #144] @ (800425c <HAL_RCC_GetSysClockFreq+0x100>) 80041cc: f7fb ff9a bl 8000104 <__udivsi3> 80041d0: 0003 movs r3, r0 80041d2: 0019 movs r1, r3 80041d4: 4b1f ldr r3, [pc, #124] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 80041d6: 68db ldr r3, [r3, #12] 80041d8: 0a1b lsrs r3, r3, #8 80041da: 227f movs r2, #127 @ 0x7f 80041dc: 4013 ands r3, r2 80041de: 434b muls r3, r1 80041e0: 617b str r3, [r7, #20] break; 80041e2: e00d b.n 8004200 <HAL_RCC_GetSysClockFreq+0xa4> case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ default: /* HSI16 used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; 80041e4: 68b9 ldr r1, [r7, #8] 80041e6: 481c ldr r0, [pc, #112] @ (8004258 <HAL_RCC_GetSysClockFreq+0xfc>) 80041e8: f7fb ff8c bl 8000104 <__udivsi3> 80041ec: 0003 movs r3, r0 80041ee: 0019 movs r1, r3 80041f0: 4b18 ldr r3, [pc, #96] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 80041f2: 68db ldr r3, [r3, #12] 80041f4: 0a1b lsrs r3, r3, #8 80041f6: 227f movs r2, #127 @ 0x7f 80041f8: 4013 ands r3, r2 80041fa: 434b muls r3, r1 80041fc: 617b str r3, [r7, #20] break; 80041fe: 46c0 nop @ (mov r8, r8) } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); 8004200: 4b14 ldr r3, [pc, #80] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 8004202: 68db ldr r3, [r3, #12] 8004204: 0f5b lsrs r3, r3, #29 8004206: 2207 movs r2, #7 8004208: 4013 ands r3, r2 800420a: 3301 adds r3, #1 800420c: 607b str r3, [r7, #4] sysclockfreq = pllvco / pllr; 800420e: 6879 ldr r1, [r7, #4] 8004210: 6978 ldr r0, [r7, #20] 8004212: f7fb ff77 bl 8000104 <__udivsi3> 8004216: 0003 movs r3, r0 8004218: 613b str r3, [r7, #16] 800421a: e015 b.n 8004248 <HAL_RCC_GetSysClockFreq+0xec> } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 800421c: 4b0d ldr r3, [pc, #52] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 800421e: 689b ldr r3, [r3, #8] 8004220: 2238 movs r2, #56 @ 0x38 8004222: 4013 ands r3, r2 8004224: 2b20 cmp r3, #32 8004226: d103 bne.n 8004230 <HAL_RCC_GetSysClockFreq+0xd4> { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 8004228: 2380 movs r3, #128 @ 0x80 800422a: 021b lsls r3, r3, #8 800422c: 613b str r3, [r7, #16] 800422e: e00b b.n 8004248 <HAL_RCC_GetSysClockFreq+0xec> } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8004230: 4b08 ldr r3, [pc, #32] @ (8004254 <HAL_RCC_GetSysClockFreq+0xf8>) 8004232: 689b ldr r3, [r3, #8] 8004234: 2238 movs r2, #56 @ 0x38 8004236: 4013 ands r3, r2 8004238: 2b18 cmp r3, #24 800423a: d103 bne.n 8004244 <HAL_RCC_GetSysClockFreq+0xe8> { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 800423c: 23fa movs r3, #250 @ 0xfa 800423e: 01db lsls r3, r3, #7 8004240: 613b str r3, [r7, #16] 8004242: e001 b.n 8004248 <HAL_RCC_GetSysClockFreq+0xec> } else { sysclockfreq = 0U; 8004244: 2300 movs r3, #0 8004246: 613b str r3, [r7, #16] } return sysclockfreq; 8004248: 693b ldr r3, [r7, #16] } 800424a: 0018 movs r0, r3 800424c: 46bd mov sp, r7 800424e: b006 add sp, #24 8004250: bd80 pop {r7, pc} 8004252: 46c0 nop @ (mov r8, r8) 8004254: 40021000 .word 0x40021000 8004258: 00f42400 .word 0x00f42400 800425c: 007a1200 .word 0x007a1200 08004260 <HAL_SPI_Init>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8004260: b580 push {r7, lr} 8004262: b084 sub sp, #16 8004264: af00 add r7, sp, #0 8004266: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 8004268: 687b ldr r3, [r7, #4] 800426a: 2b00 cmp r3, #0 800426c: d101 bne.n 8004272 <HAL_SPI_Init+0x12> { return HAL_ERROR; 800426e: 2301 movs r3, #1 8004270: e0a8 b.n 80043c4 <HAL_SPI_Init+0x164> assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 8004272: 687b ldr r3, [r7, #4] 8004274: 6a5b ldr r3, [r3, #36] @ 0x24 8004276: 2b00 cmp r3, #0 8004278: d109 bne.n 800428e <HAL_SPI_Init+0x2e> { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 800427a: 687b ldr r3, [r7, #4] 800427c: 685a ldr r2, [r3, #4] 800427e: 2382 movs r3, #130 @ 0x82 8004280: 005b lsls r3, r3, #1 8004282: 429a cmp r2, r3 8004284: d009 beq.n 800429a <HAL_SPI_Init+0x3a> assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8004286: 687b ldr r3, [r7, #4] 8004288: 2200 movs r2, #0 800428a: 61da str r2, [r3, #28] 800428c: e005 b.n 800429a <HAL_SPI_Init+0x3a> else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 800428e: 687b ldr r3, [r7, #4] 8004290: 2200 movs r2, #0 8004292: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 8004294: 687b ldr r3, [r7, #4] 8004296: 2200 movs r2, #0 8004298: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800429a: 687b ldr r3, [r7, #4] 800429c: 2200 movs r2, #0 800429e: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 80042a0: 687b ldr r3, [r7, #4] 80042a2: 225d movs r2, #93 @ 0x5d 80042a4: 5c9b ldrb r3, [r3, r2] 80042a6: b2db uxtb r3, r3 80042a8: 2b00 cmp r3, #0 80042aa: d107 bne.n 80042bc <HAL_SPI_Init+0x5c> { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 80042ac: 687b ldr r3, [r7, #4] 80042ae: 225c movs r2, #92 @ 0x5c 80042b0: 2100 movs r1, #0 80042b2: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 80042b4: 687b ldr r3, [r7, #4] 80042b6: 0018 movs r0, r3 80042b8: f7fe fe18 bl 8002eec <HAL_SPI_MspInit> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 80042bc: 687b ldr r3, [r7, #4] 80042be: 225d movs r2, #93 @ 0x5d 80042c0: 2102 movs r1, #2 80042c2: 5499 strb r1, [r3, r2] /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80042c4: 687b ldr r3, [r7, #4] 80042c6: 681b ldr r3, [r3, #0] 80042c8: 681a ldr r2, [r3, #0] 80042ca: 687b ldr r3, [r7, #4] 80042cc: 681b ldr r3, [r3, #0] 80042ce: 2140 movs r1, #64 @ 0x40 80042d0: 438a bics r2, r1 80042d2: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 80042d4: 687b ldr r3, [r7, #4] 80042d6: 68da ldr r2, [r3, #12] 80042d8: 23e0 movs r3, #224 @ 0xe0 80042da: 00db lsls r3, r3, #3 80042dc: 429a cmp r2, r3 80042de: d902 bls.n 80042e6 <HAL_SPI_Init+0x86> { frxth = SPI_RXFIFO_THRESHOLD_HF; 80042e0: 2300 movs r3, #0 80042e2: 60fb str r3, [r7, #12] 80042e4: e002 b.n 80042ec <HAL_SPI_Init+0x8c> } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 80042e6: 2380 movs r3, #128 @ 0x80 80042e8: 015b lsls r3, r3, #5 80042ea: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 80042ec: 687b ldr r3, [r7, #4] 80042ee: 68da ldr r2, [r3, #12] 80042f0: 23f0 movs r3, #240 @ 0xf0 80042f2: 011b lsls r3, r3, #4 80042f4: 429a cmp r2, r3 80042f6: d008 beq.n 800430a <HAL_SPI_Init+0xaa> 80042f8: 687b ldr r3, [r7, #4] 80042fa: 68da ldr r2, [r3, #12] 80042fc: 23e0 movs r3, #224 @ 0xe0 80042fe: 00db lsls r3, r3, #3 8004300: 429a cmp r2, r3 8004302: d002 beq.n 800430a <HAL_SPI_Init+0xaa> { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004304: 687b ldr r3, [r7, #4] 8004306: 2200 movs r2, #0 8004308: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 800430a: 687b ldr r3, [r7, #4] 800430c: 685a ldr r2, [r3, #4] 800430e: 2382 movs r3, #130 @ 0x82 8004310: 005b lsls r3, r3, #1 8004312: 401a ands r2, r3 8004314: 687b ldr r3, [r7, #4] 8004316: 6899 ldr r1, [r3, #8] 8004318: 2384 movs r3, #132 @ 0x84 800431a: 021b lsls r3, r3, #8 800431c: 400b ands r3, r1 800431e: 431a orrs r2, r3 8004320: 687b ldr r3, [r7, #4] 8004322: 691b ldr r3, [r3, #16] 8004324: 2102 movs r1, #2 8004326: 400b ands r3, r1 8004328: 431a orrs r2, r3 800432a: 687b ldr r3, [r7, #4] 800432c: 695b ldr r3, [r3, #20] 800432e: 2101 movs r1, #1 8004330: 400b ands r3, r1 8004332: 431a orrs r2, r3 8004334: 687b ldr r3, [r7, #4] 8004336: 6999 ldr r1, [r3, #24] 8004338: 2380 movs r3, #128 @ 0x80 800433a: 009b lsls r3, r3, #2 800433c: 400b ands r3, r1 800433e: 431a orrs r2, r3 8004340: 687b ldr r3, [r7, #4] 8004342: 69db ldr r3, [r3, #28] 8004344: 2138 movs r1, #56 @ 0x38 8004346: 400b ands r3, r1 8004348: 431a orrs r2, r3 800434a: 687b ldr r3, [r7, #4] 800434c: 6a1b ldr r3, [r3, #32] 800434e: 2180 movs r1, #128 @ 0x80 8004350: 400b ands r3, r1 8004352: 431a orrs r2, r3 8004354: 0011 movs r1, r2 8004356: 687b ldr r3, [r7, #4] 8004358: 6a9a ldr r2, [r3, #40] @ 0x28 800435a: 2380 movs r3, #128 @ 0x80 800435c: 019b lsls r3, r3, #6 800435e: 401a ands r2, r3 8004360: 687b ldr r3, [r7, #4] 8004362: 681b ldr r3, [r3, #0] 8004364: 430a orrs r2, r1 8004366: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 8004368: 687b ldr r3, [r7, #4] 800436a: 699b ldr r3, [r3, #24] 800436c: 0c1b lsrs r3, r3, #16 800436e: 2204 movs r2, #4 8004370: 401a ands r2, r3 8004372: 687b ldr r3, [r7, #4] 8004374: 6a5b ldr r3, [r3, #36] @ 0x24 8004376: 2110 movs r1, #16 8004378: 400b ands r3, r1 800437a: 431a orrs r2, r3 800437c: 687b ldr r3, [r7, #4] 800437e: 6b5b ldr r3, [r3, #52] @ 0x34 8004380: 2108 movs r1, #8 8004382: 400b ands r3, r1 8004384: 431a orrs r2, r3 8004386: 687b ldr r3, [r7, #4] 8004388: 68d9 ldr r1, [r3, #12] 800438a: 23f0 movs r3, #240 @ 0xf0 800438c: 011b lsls r3, r3, #4 800438e: 400b ands r3, r1 8004390: 431a orrs r2, r3 8004392: 0011 movs r1, r2 8004394: 68fa ldr r2, [r7, #12] 8004396: 2380 movs r3, #128 @ 0x80 8004398: 015b lsls r3, r3, #5 800439a: 401a ands r2, r3 800439c: 687b ldr r3, [r7, #4] 800439e: 681b ldr r3, [r3, #0] 80043a0: 430a orrs r2, r1 80043a2: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 80043a4: 687b ldr r3, [r7, #4] 80043a6: 681b ldr r3, [r3, #0] 80043a8: 69da ldr r2, [r3, #28] 80043aa: 687b ldr r3, [r7, #4] 80043ac: 681b ldr r3, [r3, #0] 80043ae: 4907 ldr r1, [pc, #28] @ (80043cc <HAL_SPI_Init+0x16c>) 80043b0: 400a ands r2, r1 80043b2: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80043b4: 687b ldr r3, [r7, #4] 80043b6: 2200 movs r2, #0 80043b8: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 80043ba: 687b ldr r3, [r7, #4] 80043bc: 225d movs r2, #93 @ 0x5d 80043be: 2101 movs r1, #1 80043c0: 5499 strb r1, [r3, r2] return HAL_OK; 80043c2: 2300 movs r3, #0 } 80043c4: 0018 movs r0, r3 80043c6: 46bd mov sp, r7 80043c8: b004 add sp, #16 80043ca: bd80 pop {r7, pc} 80043cc: fffff7ff .word 0xfffff7ff 080043d0 <HAL_SPI_IRQHandler>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { 80043d0: b580 push {r7, lr} 80043d2: b088 sub sp, #32 80043d4: af00 add r7, sp, #0 80043d6: 6078 str r0, [r7, #4] uint32_t itsource = hspi->Instance->CR2; 80043d8: 687b ldr r3, [r7, #4] 80043da: 681b ldr r3, [r3, #0] 80043dc: 685b ldr r3, [r3, #4] 80043de: 61fb str r3, [r7, #28] uint32_t itflag = hspi->Instance->SR; 80043e0: 687b ldr r3, [r7, #4] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 689b ldr r3, [r3, #8] 80043e6: 61bb str r3, [r7, #24] /* SPI in mode Receiver ----------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 80043e8: 69bb ldr r3, [r7, #24] 80043ea: 099b lsrs r3, r3, #6 80043ec: 001a movs r2, r3 80043ee: 2301 movs r3, #1 80043f0: 4013 ands r3, r2 80043f2: d10f bne.n 8004414 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 80043f4: 69bb ldr r3, [r7, #24] 80043f6: 2201 movs r2, #1 80043f8: 4013 ands r3, r2 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 80043fa: d00b beq.n 8004414 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 80043fc: 69fb ldr r3, [r7, #28] 80043fe: 099b lsrs r3, r3, #6 8004400: 001a movs r2, r3 8004402: 2301 movs r3, #1 8004404: 4013 ands r3, r2 8004406: d005 beq.n 8004414 <HAL_SPI_IRQHandler+0x44> { hspi->RxISR(hspi); 8004408: 687b ldr r3, [r7, #4] 800440a: 6cdb ldr r3, [r3, #76] @ 0x4c 800440c: 687a ldr r2, [r7, #4] 800440e: 0010 movs r0, r2 8004410: 4798 blx r3 return; 8004412: e0d5 b.n 80045c0 <HAL_SPI_IRQHandler+0x1f0> } /* SPI in mode Transmitter -------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) 8004414: 69bb ldr r3, [r7, #24] 8004416: 085b lsrs r3, r3, #1 8004418: 001a movs r2, r3 800441a: 2301 movs r3, #1 800441c: 4013 ands r3, r2 800441e: d00b beq.n 8004438 <HAL_SPI_IRQHandler+0x68> 8004420: 69fb ldr r3, [r7, #28] 8004422: 09db lsrs r3, r3, #7 8004424: 001a movs r2, r3 8004426: 2301 movs r3, #1 8004428: 4013 ands r3, r2 800442a: d005 beq.n 8004438 <HAL_SPI_IRQHandler+0x68> { hspi->TxISR(hspi); 800442c: 687b ldr r3, [r7, #4] 800442e: 6d1b ldr r3, [r3, #80] @ 0x50 8004430: 687a ldr r2, [r7, #4] 8004432: 0010 movs r0, r2 8004434: 4798 blx r3 return; 8004436: e0c3 b.n 80045c0 <HAL_SPI_IRQHandler+0x1f0> } /* SPI in Error Treatment --------------------------------------------------*/ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) 8004438: 69bb ldr r3, [r7, #24] 800443a: 095b lsrs r3, r3, #5 800443c: 001a movs r2, r3 800443e: 2301 movs r3, #1 8004440: 4013 ands r3, r2 8004442: d10c bne.n 800445e <HAL_SPI_IRQHandler+0x8e> 8004444: 69bb ldr r3, [r7, #24] 8004446: 099b lsrs r3, r3, #6 8004448: 001a movs r2, r3 800444a: 2301 movs r3, #1 800444c: 4013 ands r3, r2 800444e: d106 bne.n 800445e <HAL_SPI_IRQHandler+0x8e> || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) 8004450: 69bb ldr r3, [r7, #24] 8004452: 0a1b lsrs r3, r3, #8 8004454: 001a movs r2, r3 8004456: 2301 movs r3, #1 8004458: 4013 ands r3, r2 800445a: d100 bne.n 800445e <HAL_SPI_IRQHandler+0x8e> 800445c: e0b0 b.n 80045c0 <HAL_SPI_IRQHandler+0x1f0> 800445e: 69fb ldr r3, [r7, #28] 8004460: 095b lsrs r3, r3, #5 8004462: 001a movs r2, r3 8004464: 2301 movs r3, #1 8004466: 4013 ands r3, r2 8004468: d100 bne.n 800446c <HAL_SPI_IRQHandler+0x9c> 800446a: e0a9 b.n 80045c0 <HAL_SPI_IRQHandler+0x1f0> { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) 800446c: 69bb ldr r3, [r7, #24] 800446e: 099b lsrs r3, r3, #6 8004470: 001a movs r2, r3 8004472: 2301 movs r3, #1 8004474: 4013 ands r3, r2 8004476: d023 beq.n 80044c0 <HAL_SPI_IRQHandler+0xf0> { if (hspi->State != HAL_SPI_STATE_BUSY_TX) 8004478: 687b ldr r3, [r7, #4] 800447a: 225d movs r2, #93 @ 0x5d 800447c: 5c9b ldrb r3, [r3, r2] 800447e: b2db uxtb r3, r3 8004480: 2b03 cmp r3, #3 8004482: d011 beq.n 80044a8 <HAL_SPI_IRQHandler+0xd8> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); 8004484: 687b ldr r3, [r7, #4] 8004486: 6e1b ldr r3, [r3, #96] @ 0x60 8004488: 2204 movs r2, #4 800448a: 431a orrs r2, r3 800448c: 687b ldr r3, [r7, #4] 800448e: 661a str r2, [r3, #96] @ 0x60 __HAL_SPI_CLEAR_OVRFLAG(hspi); 8004490: 2300 movs r3, #0 8004492: 617b str r3, [r7, #20] 8004494: 687b ldr r3, [r7, #4] 8004496: 681b ldr r3, [r3, #0] 8004498: 68db ldr r3, [r3, #12] 800449a: 617b str r3, [r7, #20] 800449c: 687b ldr r3, [r7, #4] 800449e: 681b ldr r3, [r3, #0] 80044a0: 689b ldr r3, [r3, #8] 80044a2: 617b str r3, [r7, #20] 80044a4: 697b ldr r3, [r7, #20] 80044a6: e00b b.n 80044c0 <HAL_SPI_IRQHandler+0xf0> } else { __HAL_SPI_CLEAR_OVRFLAG(hspi); 80044a8: 2300 movs r3, #0 80044aa: 613b str r3, [r7, #16] 80044ac: 687b ldr r3, [r7, #4] 80044ae: 681b ldr r3, [r3, #0] 80044b0: 68db ldr r3, [r3, #12] 80044b2: 613b str r3, [r7, #16] 80044b4: 687b ldr r3, [r7, #4] 80044b6: 681b ldr r3, [r3, #0] 80044b8: 689b ldr r3, [r3, #8] 80044ba: 613b str r3, [r7, #16] 80044bc: 693b ldr r3, [r7, #16] return; 80044be: e07f b.n 80045c0 <HAL_SPI_IRQHandler+0x1f0> } } /* SPI Mode Fault error interrupt occurred -------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) 80044c0: 69bb ldr r3, [r7, #24] 80044c2: 095b lsrs r3, r3, #5 80044c4: 001a movs r2, r3 80044c6: 2301 movs r3, #1 80044c8: 4013 ands r3, r2 80044ca: d014 beq.n 80044f6 <HAL_SPI_IRQHandler+0x126> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); 80044cc: 687b ldr r3, [r7, #4] 80044ce: 6e1b ldr r3, [r3, #96] @ 0x60 80044d0: 2201 movs r2, #1 80044d2: 431a orrs r2, r3 80044d4: 687b ldr r3, [r7, #4] 80044d6: 661a str r2, [r3, #96] @ 0x60 __HAL_SPI_CLEAR_MODFFLAG(hspi); 80044d8: 2300 movs r3, #0 80044da: 60fb str r3, [r7, #12] 80044dc: 687b ldr r3, [r7, #4] 80044de: 681b ldr r3, [r3, #0] 80044e0: 689b ldr r3, [r3, #8] 80044e2: 60fb str r3, [r7, #12] 80044e4: 687b ldr r3, [r7, #4] 80044e6: 681b ldr r3, [r3, #0] 80044e8: 681a ldr r2, [r3, #0] 80044ea: 687b ldr r3, [r7, #4] 80044ec: 681b ldr r3, [r3, #0] 80044ee: 2140 movs r1, #64 @ 0x40 80044f0: 438a bics r2, r1 80044f2: 601a str r2, [r3, #0] 80044f4: 68fb ldr r3, [r7, #12] } /* SPI Frame error interrupt occurred ------------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) 80044f6: 69bb ldr r3, [r7, #24] 80044f8: 0a1b lsrs r3, r3, #8 80044fa: 001a movs r2, r3 80044fc: 2301 movs r3, #1 80044fe: 4013 ands r3, r2 8004500: d00c beq.n 800451c <HAL_SPI_IRQHandler+0x14c> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); 8004502: 687b ldr r3, [r7, #4] 8004504: 6e1b ldr r3, [r3, #96] @ 0x60 8004506: 2208 movs r2, #8 8004508: 431a orrs r2, r3 800450a: 687b ldr r3, [r7, #4] 800450c: 661a str r2, [r3, #96] @ 0x60 __HAL_SPI_CLEAR_FREFLAG(hspi); 800450e: 2300 movs r3, #0 8004510: 60bb str r3, [r7, #8] 8004512: 687b ldr r3, [r7, #4] 8004514: 681b ldr r3, [r3, #0] 8004516: 689b ldr r3, [r3, #8] 8004518: 60bb str r3, [r7, #8] 800451a: 68bb ldr r3, [r7, #8] } if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800451c: 687b ldr r3, [r7, #4] 800451e: 6e1b ldr r3, [r3, #96] @ 0x60 8004520: 2b00 cmp r3, #0 8004522: d04c beq.n 80045be <HAL_SPI_IRQHandler+0x1ee> { /* Disable all interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); 8004524: 687b ldr r3, [r7, #4] 8004526: 681b ldr r3, [r3, #0] 8004528: 685a ldr r2, [r3, #4] 800452a: 687b ldr r3, [r7, #4] 800452c: 681b ldr r3, [r3, #0] 800452e: 21e0 movs r1, #224 @ 0xe0 8004530: 438a bics r2, r1 8004532: 605a str r2, [r3, #4] hspi->State = HAL_SPI_STATE_READY; 8004534: 687b ldr r3, [r7, #4] 8004536: 225d movs r2, #93 @ 0x5d 8004538: 2101 movs r1, #1 800453a: 5499 strb r1, [r3, r2] /* Disable the SPI DMA requests if enabled */ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) 800453c: 69fb ldr r3, [r7, #28] 800453e: 2202 movs r2, #2 8004540: 4013 ands r3, r2 8004542: d103 bne.n 800454c <HAL_SPI_IRQHandler+0x17c> 8004544: 69fb ldr r3, [r7, #28] 8004546: 2201 movs r2, #1 8004548: 4013 ands r3, r2 800454a: d032 beq.n 80045b2 <HAL_SPI_IRQHandler+0x1e2> { CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); 800454c: 687b ldr r3, [r7, #4] 800454e: 681b ldr r3, [r3, #0] 8004550: 685a ldr r2, [r3, #4] 8004552: 687b ldr r3, [r7, #4] 8004554: 681b ldr r3, [r3, #0] 8004556: 2103 movs r1, #3 8004558: 438a bics r2, r1 800455a: 605a str r2, [r3, #4] /* Abort the SPI DMA Rx channel */ if (hspi->hdmarx != NULL) 800455c: 687b ldr r3, [r7, #4] 800455e: 6d9b ldr r3, [r3, #88] @ 0x58 8004560: 2b00 cmp r3, #0 8004562: d010 beq.n 8004586 <HAL_SPI_IRQHandler+0x1b6> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; 8004564: 687b ldr r3, [r7, #4] 8004566: 6d9b ldr r3, [r3, #88] @ 0x58 8004568: 4a17 ldr r2, [pc, #92] @ (80045c8 <HAL_SPI_IRQHandler+0x1f8>) 800456a: 639a str r2, [r3, #56] @ 0x38 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) 800456c: 687b ldr r3, [r7, #4] 800456e: 6d9b ldr r3, [r3, #88] @ 0x58 8004570: 0018 movs r0, r3 8004572: f7fe ff71 bl 8003458 <HAL_DMA_Abort_IT> 8004576: 1e03 subs r3, r0, #0 8004578: d005 beq.n 8004586 <HAL_SPI_IRQHandler+0x1b6> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800457a: 687b ldr r3, [r7, #4] 800457c: 6e1b ldr r3, [r3, #96] @ 0x60 800457e: 2240 movs r2, #64 @ 0x40 8004580: 431a orrs r2, r3 8004582: 687b ldr r3, [r7, #4] 8004584: 661a str r2, [r3, #96] @ 0x60 } } /* Abort the SPI DMA Tx channel */ if (hspi->hdmatx != NULL) 8004586: 687b ldr r3, [r7, #4] 8004588: 6d5b ldr r3, [r3, #84] @ 0x54 800458a: 2b00 cmp r3, #0 800458c: d016 beq.n 80045bc <HAL_SPI_IRQHandler+0x1ec> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; 800458e: 687b ldr r3, [r7, #4] 8004590: 6d5b ldr r3, [r3, #84] @ 0x54 8004592: 4a0d ldr r2, [pc, #52] @ (80045c8 <HAL_SPI_IRQHandler+0x1f8>) 8004594: 639a str r2, [r3, #56] @ 0x38 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) 8004596: 687b ldr r3, [r7, #4] 8004598: 6d5b ldr r3, [r3, #84] @ 0x54 800459a: 0018 movs r0, r3 800459c: f7fe ff5c bl 8003458 <HAL_DMA_Abort_IT> 80045a0: 1e03 subs r3, r0, #0 80045a2: d00b beq.n 80045bc <HAL_SPI_IRQHandler+0x1ec> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 80045a4: 687b ldr r3, [r7, #4] 80045a6: 6e1b ldr r3, [r3, #96] @ 0x60 80045a8: 2240 movs r2, #64 @ 0x40 80045aa: 431a orrs r2, r3 80045ac: 687b ldr r3, [r7, #4] 80045ae: 661a str r2, [r3, #96] @ 0x60 if (hspi->hdmatx != NULL) 80045b0: e004 b.n 80045bc <HAL_SPI_IRQHandler+0x1ec> { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 80045b2: 687b ldr r3, [r7, #4] 80045b4: 0018 movs r0, r3 80045b6: f000 f809 bl 80045cc <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } return; 80045ba: e000 b.n 80045be <HAL_SPI_IRQHandler+0x1ee> if (hspi->hdmatx != NULL) 80045bc: 46c0 nop @ (mov r8, r8) return; 80045be: 46c0 nop @ (mov r8, r8) } } 80045c0: 46bd mov sp, r7 80045c2: b008 add sp, #32 80045c4: bd80 pop {r7, pc} 80045c6: 46c0 nop @ (mov r8, r8) 80045c8: 080045dd .word 0x080045dd 080045cc <HAL_SPI_ErrorCallback>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { 80045cc: b580 push {r7, lr} 80045ce: b082 sub sp, #8 80045d0: af00 add r7, sp, #0 80045d2: 6078 str r0, [r7, #4] the HAL_SPI_ErrorCallback should be implemented in the user file */ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes and user can use HAL_SPI_GetError() API to check the latest error occurred */ } 80045d4: 46c0 nop @ (mov r8, r8) 80045d6: 46bd mov sp, r7 80045d8: b002 add sp, #8 80045da: bd80 pop {r7, pc} 080045dc <SPI_DMAAbortOnError>: * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80045dc: b580 push {r7, lr} 80045de: b084 sub sp, #16 80045e0: af00 add r7, sp, #0 80045e2: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ 80045e4: 687b ldr r3, [r7, #4] 80045e6: 6a9b ldr r3, [r3, #40] @ 0x28 80045e8: 60fb str r3, [r7, #12] hspi->RxXferCount = 0U; 80045ea: 68fb ldr r3, [r7, #12] 80045ec: 2246 movs r2, #70 @ 0x46 80045ee: 2100 movs r1, #0 80045f0: 5299 strh r1, [r3, r2] hspi->TxXferCount = 0U; 80045f2: 68fb ldr r3, [r7, #12] 80045f4: 2200 movs r2, #0 80045f6: 87da strh r2, [r3, #62] @ 0x3e /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 80045f8: 68fb ldr r3, [r7, #12] 80045fa: 0018 movs r0, r3 80045fc: f7ff ffe6 bl 80045cc <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 8004600: 46c0 nop @ (mov r8, r8) 8004602: 46bd mov sp, r7 8004604: b004 add sp, #16 8004606: bd80 pop {r7, pc} 08004608 <HAL_TIM_Base_Init>: * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8004608: b580 push {r7, lr} 800460a: b082 sub sp, #8 800460c: af00 add r7, sp, #0 800460e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004610: 687b ldr r3, [r7, #4] 8004612: 2b00 cmp r3, #0 8004614: d101 bne.n 800461a <HAL_TIM_Base_Init+0x12> { return HAL_ERROR; 8004616: 2301 movs r3, #1 8004618: e04a b.n 80046b0 <HAL_TIM_Base_Init+0xa8> assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800461a: 687b ldr r3, [r7, #4] 800461c: 223d movs r2, #61 @ 0x3d 800461e: 5c9b ldrb r3, [r3, r2] 8004620: b2db uxtb r3, r3 8004622: 2b00 cmp r3, #0 8004624: d107 bne.n 8004636 <HAL_TIM_Base_Init+0x2e> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8004626: 687b ldr r3, [r7, #4] 8004628: 223c movs r2, #60 @ 0x3c 800462a: 2100 movs r1, #0 800462c: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800462e: 687b ldr r3, [r7, #4] 8004630: 0018 movs r0, r3 8004632: f7fe fceb bl 800300c <HAL_TIM_Base_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004636: 687b ldr r3, [r7, #4] 8004638: 223d movs r2, #61 @ 0x3d 800463a: 2102 movs r1, #2 800463c: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800463e: 687b ldr r3, [r7, #4] 8004640: 681a ldr r2, [r3, #0] 8004642: 687b ldr r3, [r7, #4] 8004644: 3304 adds r3, #4 8004646: 0019 movs r1, r3 8004648: 0010 movs r0, r2 800464a: f000 f9b1 bl 80049b0 <TIM_Base_SetConfig> /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800464e: 687b ldr r3, [r7, #4] 8004650: 2248 movs r2, #72 @ 0x48 8004652: 2101 movs r1, #1 8004654: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004656: 687b ldr r3, [r7, #4] 8004658: 223e movs r2, #62 @ 0x3e 800465a: 2101 movs r1, #1 800465c: 5499 strb r1, [r3, r2] 800465e: 687b ldr r3, [r7, #4] 8004660: 223f movs r2, #63 @ 0x3f 8004662: 2101 movs r1, #1 8004664: 5499 strb r1, [r3, r2] 8004666: 687b ldr r3, [r7, #4] 8004668: 2240 movs r2, #64 @ 0x40 800466a: 2101 movs r1, #1 800466c: 5499 strb r1, [r3, r2] 800466e: 687b ldr r3, [r7, #4] 8004670: 2241 movs r2, #65 @ 0x41 8004672: 2101 movs r1, #1 8004674: 5499 strb r1, [r3, r2] 8004676: 687b ldr r3, [r7, #4] 8004678: 2242 movs r2, #66 @ 0x42 800467a: 2101 movs r1, #1 800467c: 5499 strb r1, [r3, r2] 800467e: 687b ldr r3, [r7, #4] 8004680: 2243 movs r2, #67 @ 0x43 8004682: 2101 movs r1, #1 8004684: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004686: 687b ldr r3, [r7, #4] 8004688: 2244 movs r2, #68 @ 0x44 800468a: 2101 movs r1, #1 800468c: 5499 strb r1, [r3, r2] 800468e: 687b ldr r3, [r7, #4] 8004690: 2245 movs r2, #69 @ 0x45 8004692: 2101 movs r1, #1 8004694: 5499 strb r1, [r3, r2] 8004696: 687b ldr r3, [r7, #4] 8004698: 2246 movs r2, #70 @ 0x46 800469a: 2101 movs r1, #1 800469c: 5499 strb r1, [r3, r2] 800469e: 687b ldr r3, [r7, #4] 80046a0: 2247 movs r2, #71 @ 0x47 80046a2: 2101 movs r1, #1 80046a4: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80046a6: 687b ldr r3, [r7, #4] 80046a8: 223d movs r2, #61 @ 0x3d 80046aa: 2101 movs r1, #1 80046ac: 5499 strb r1, [r3, r2] return HAL_OK; 80046ae: 2300 movs r3, #0 } 80046b0: 0018 movs r0, r3 80046b2: 46bd mov sp, r7 80046b4: b002 add sp, #8 80046b6: bd80 pop {r7, pc} 080046b8 <HAL_TIM_Base_Start_IT>: * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 80046b8: b580 push {r7, lr} 80046ba: b084 sub sp, #16 80046bc: af00 add r7, sp, #0 80046be: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 80046c0: 687b ldr r3, [r7, #4] 80046c2: 223d movs r2, #61 @ 0x3d 80046c4: 5c9b ldrb r3, [r3, r2] 80046c6: b2db uxtb r3, r3 80046c8: 2b01 cmp r3, #1 80046ca: d001 beq.n 80046d0 <HAL_TIM_Base_Start_IT+0x18> { return HAL_ERROR; 80046cc: 2301 movs r3, #1 80046ce: e03d b.n 800474c <HAL_TIM_Base_Start_IT+0x94> } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80046d0: 687b ldr r3, [r7, #4] 80046d2: 223d movs r2, #61 @ 0x3d 80046d4: 2102 movs r1, #2 80046d6: 5499 strb r1, [r3, r2] /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 80046d8: 687b ldr r3, [r7, #4] 80046da: 681b ldr r3, [r3, #0] 80046dc: 68da ldr r2, [r3, #12] 80046de: 687b ldr r3, [r7, #4] 80046e0: 681b ldr r3, [r3, #0] 80046e2: 2101 movs r1, #1 80046e4: 430a orrs r2, r1 80046e6: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80046e8: 687b ldr r3, [r7, #4] 80046ea: 681b ldr r3, [r3, #0] 80046ec: 4a19 ldr r2, [pc, #100] @ (8004754 <HAL_TIM_Base_Start_IT+0x9c>) 80046ee: 4293 cmp r3, r2 80046f0: d00a beq.n 8004708 <HAL_TIM_Base_Start_IT+0x50> 80046f2: 687b ldr r3, [r7, #4] 80046f4: 681a ldr r2, [r3, #0] 80046f6: 2380 movs r3, #128 @ 0x80 80046f8: 05db lsls r3, r3, #23 80046fa: 429a cmp r2, r3 80046fc: d004 beq.n 8004708 <HAL_TIM_Base_Start_IT+0x50> 80046fe: 687b ldr r3, [r7, #4] 8004700: 681b ldr r3, [r3, #0] 8004702: 4a15 ldr r2, [pc, #84] @ (8004758 <HAL_TIM_Base_Start_IT+0xa0>) 8004704: 4293 cmp r3, r2 8004706: d116 bne.n 8004736 <HAL_TIM_Base_Start_IT+0x7e> { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8004708: 687b ldr r3, [r7, #4] 800470a: 681b ldr r3, [r3, #0] 800470c: 689b ldr r3, [r3, #8] 800470e: 4a13 ldr r2, [pc, #76] @ (800475c <HAL_TIM_Base_Start_IT+0xa4>) 8004710: 4013 ands r3, r2 8004712: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004714: 68fb ldr r3, [r7, #12] 8004716: 2b06 cmp r3, #6 8004718: d016 beq.n 8004748 <HAL_TIM_Base_Start_IT+0x90> 800471a: 68fa ldr r2, [r7, #12] 800471c: 2380 movs r3, #128 @ 0x80 800471e: 025b lsls r3, r3, #9 8004720: 429a cmp r2, r3 8004722: d011 beq.n 8004748 <HAL_TIM_Base_Start_IT+0x90> { __HAL_TIM_ENABLE(htim); 8004724: 687b ldr r3, [r7, #4] 8004726: 681b ldr r3, [r3, #0] 8004728: 681a ldr r2, [r3, #0] 800472a: 687b ldr r3, [r7, #4] 800472c: 681b ldr r3, [r3, #0] 800472e: 2101 movs r1, #1 8004730: 430a orrs r2, r1 8004732: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004734: e008 b.n 8004748 <HAL_TIM_Base_Start_IT+0x90> } } else { __HAL_TIM_ENABLE(htim); 8004736: 687b ldr r3, [r7, #4] 8004738: 681b ldr r3, [r3, #0] 800473a: 681a ldr r2, [r3, #0] 800473c: 687b ldr r3, [r7, #4] 800473e: 681b ldr r3, [r3, #0] 8004740: 2101 movs r1, #1 8004742: 430a orrs r2, r1 8004744: 601a str r2, [r3, #0] 8004746: e000 b.n 800474a <HAL_TIM_Base_Start_IT+0x92> if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004748: 46c0 nop @ (mov r8, r8) } /* Return function status */ return HAL_OK; 800474a: 2300 movs r3, #0 } 800474c: 0018 movs r0, r3 800474e: 46bd mov sp, r7 8004750: b004 add sp, #16 8004752: bd80 pop {r7, pc} 8004754: 40012c00 .word 0x40012c00 8004758: 40000400 .word 0x40000400 800475c: 00010007 .word 0x00010007 08004760 <HAL_TIM_IRQHandler>: * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8004760: b580 push {r7, lr} 8004762: b084 sub sp, #16 8004764: af00 add r7, sp, #0 8004766: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8004768: 687b ldr r3, [r7, #4] 800476a: 681b ldr r3, [r3, #0] 800476c: 68db ldr r3, [r3, #12] 800476e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8004770: 687b ldr r3, [r7, #4] 8004772: 681b ldr r3, [r3, #0] 8004774: 691b ldr r3, [r3, #16] 8004776: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8004778: 68bb ldr r3, [r7, #8] 800477a: 2202 movs r2, #2 800477c: 4013 ands r3, r2 800477e: d021 beq.n 80047c4 <HAL_TIM_IRQHandler+0x64> { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8004780: 68fb ldr r3, [r7, #12] 8004782: 2202 movs r2, #2 8004784: 4013 ands r3, r2 8004786: d01d beq.n 80047c4 <HAL_TIM_IRQHandler+0x64> { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8004788: 687b ldr r3, [r7, #4] 800478a: 681b ldr r3, [r3, #0] 800478c: 2203 movs r2, #3 800478e: 4252 negs r2, r2 8004790: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8004792: 687b ldr r3, [r7, #4] 8004794: 2201 movs r2, #1 8004796: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8004798: 687b ldr r3, [r7, #4] 800479a: 681b ldr r3, [r3, #0] 800479c: 699b ldr r3, [r3, #24] 800479e: 2203 movs r2, #3 80047a0: 4013 ands r3, r2 80047a2: d004 beq.n 80047ae <HAL_TIM_IRQHandler+0x4e> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80047a4: 687b ldr r3, [r7, #4] 80047a6: 0018 movs r0, r3 80047a8: f000 f8ea bl 8004980 <HAL_TIM_IC_CaptureCallback> 80047ac: e007 b.n 80047be <HAL_TIM_IRQHandler+0x5e> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80047ae: 687b ldr r3, [r7, #4] 80047b0: 0018 movs r0, r3 80047b2: f000 f8dd bl 8004970 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 80047b6: 687b ldr r3, [r7, #4] 80047b8: 0018 movs r0, r3 80047ba: f000 f8e9 bl 8004990 <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80047be: 687b ldr r3, [r7, #4] 80047c0: 2200 movs r2, #0 80047c2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80047c4: 68bb ldr r3, [r7, #8] 80047c6: 2204 movs r2, #4 80047c8: 4013 ands r3, r2 80047ca: d022 beq.n 8004812 <HAL_TIM_IRQHandler+0xb2> { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80047cc: 68fb ldr r3, [r7, #12] 80047ce: 2204 movs r2, #4 80047d0: 4013 ands r3, r2 80047d2: d01e beq.n 8004812 <HAL_TIM_IRQHandler+0xb2> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80047d4: 687b ldr r3, [r7, #4] 80047d6: 681b ldr r3, [r3, #0] 80047d8: 2205 movs r2, #5 80047da: 4252 negs r2, r2 80047dc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80047de: 687b ldr r3, [r7, #4] 80047e0: 2202 movs r2, #2 80047e2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80047e4: 687b ldr r3, [r7, #4] 80047e6: 681b ldr r3, [r3, #0] 80047e8: 699a ldr r2, [r3, #24] 80047ea: 23c0 movs r3, #192 @ 0xc0 80047ec: 009b lsls r3, r3, #2 80047ee: 4013 ands r3, r2 80047f0: d004 beq.n 80047fc <HAL_TIM_IRQHandler+0x9c> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80047f2: 687b ldr r3, [r7, #4] 80047f4: 0018 movs r0, r3 80047f6: f000 f8c3 bl 8004980 <HAL_TIM_IC_CaptureCallback> 80047fa: e007 b.n 800480c <HAL_TIM_IRQHandler+0xac> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80047fc: 687b ldr r3, [r7, #4] 80047fe: 0018 movs r0, r3 8004800: f000 f8b6 bl 8004970 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8004804: 687b ldr r3, [r7, #4] 8004806: 0018 movs r0, r3 8004808: f000 f8c2 bl 8004990 <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800480c: 687b ldr r3, [r7, #4] 800480e: 2200 movs r2, #0 8004810: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8004812: 68bb ldr r3, [r7, #8] 8004814: 2208 movs r2, #8 8004816: 4013 ands r3, r2 8004818: d021 beq.n 800485e <HAL_TIM_IRQHandler+0xfe> { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800481a: 68fb ldr r3, [r7, #12] 800481c: 2208 movs r2, #8 800481e: 4013 ands r3, r2 8004820: d01d beq.n 800485e <HAL_TIM_IRQHandler+0xfe> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8004822: 687b ldr r3, [r7, #4] 8004824: 681b ldr r3, [r3, #0] 8004826: 2209 movs r2, #9 8004828: 4252 negs r2, r2 800482a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800482c: 687b ldr r3, [r7, #4] 800482e: 2204 movs r2, #4 8004830: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8004832: 687b ldr r3, [r7, #4] 8004834: 681b ldr r3, [r3, #0] 8004836: 69db ldr r3, [r3, #28] 8004838: 2203 movs r2, #3 800483a: 4013 ands r3, r2 800483c: d004 beq.n 8004848 <HAL_TIM_IRQHandler+0xe8> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800483e: 687b ldr r3, [r7, #4] 8004840: 0018 movs r0, r3 8004842: f000 f89d bl 8004980 <HAL_TIM_IC_CaptureCallback> 8004846: e007 b.n 8004858 <HAL_TIM_IRQHandler+0xf8> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004848: 687b ldr r3, [r7, #4] 800484a: 0018 movs r0, r3 800484c: f000 f890 bl 8004970 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8004850: 687b ldr r3, [r7, #4] 8004852: 0018 movs r0, r3 8004854: f000 f89c bl 8004990 <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004858: 687b ldr r3, [r7, #4] 800485a: 2200 movs r2, #0 800485c: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800485e: 68bb ldr r3, [r7, #8] 8004860: 2210 movs r2, #16 8004862: 4013 ands r3, r2 8004864: d022 beq.n 80048ac <HAL_TIM_IRQHandler+0x14c> { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8004866: 68fb ldr r3, [r7, #12] 8004868: 2210 movs r2, #16 800486a: 4013 ands r3, r2 800486c: d01e beq.n 80048ac <HAL_TIM_IRQHandler+0x14c> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800486e: 687b ldr r3, [r7, #4] 8004870: 681b ldr r3, [r3, #0] 8004872: 2211 movs r2, #17 8004874: 4252 negs r2, r2 8004876: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8004878: 687b ldr r3, [r7, #4] 800487a: 2208 movs r2, #8 800487c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800487e: 687b ldr r3, [r7, #4] 8004880: 681b ldr r3, [r3, #0] 8004882: 69da ldr r2, [r3, #28] 8004884: 23c0 movs r3, #192 @ 0xc0 8004886: 009b lsls r3, r3, #2 8004888: 4013 ands r3, r2 800488a: d004 beq.n 8004896 <HAL_TIM_IRQHandler+0x136> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800488c: 687b ldr r3, [r7, #4] 800488e: 0018 movs r0, r3 8004890: f000 f876 bl 8004980 <HAL_TIM_IC_CaptureCallback> 8004894: e007 b.n 80048a6 <HAL_TIM_IRQHandler+0x146> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004896: 687b ldr r3, [r7, #4] 8004898: 0018 movs r0, r3 800489a: f000 f869 bl 8004970 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 800489e: 687b ldr r3, [r7, #4] 80048a0: 0018 movs r0, r3 80048a2: f000 f875 bl 8004990 <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80048a6: 687b ldr r3, [r7, #4] 80048a8: 2200 movs r2, #0 80048aa: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80048ac: 68bb ldr r3, [r7, #8] 80048ae: 2201 movs r2, #1 80048b0: 4013 ands r3, r2 80048b2: d00c beq.n 80048ce <HAL_TIM_IRQHandler+0x16e> { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80048b4: 68fb ldr r3, [r7, #12] 80048b6: 2201 movs r2, #1 80048b8: 4013 ands r3, r2 80048ba: d008 beq.n 80048ce <HAL_TIM_IRQHandler+0x16e> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80048bc: 687b ldr r3, [r7, #4] 80048be: 681b ldr r3, [r3, #0] 80048c0: 2202 movs r2, #2 80048c2: 4252 negs r2, r2 80048c4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80048c6: 687b ldr r3, [r7, #4] 80048c8: 0018 movs r0, r3 80048ca: f7fe fad1 bl 8002e70 <HAL_TIM_PeriodElapsedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 80048ce: 68bb ldr r3, [r7, #8] 80048d0: 2280 movs r2, #128 @ 0x80 80048d2: 4013 ands r3, r2 80048d4: d104 bne.n 80048e0 <HAL_TIM_IRQHandler+0x180> ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 80048d6: 68ba ldr r2, [r7, #8] 80048d8: 2380 movs r3, #128 @ 0x80 80048da: 019b lsls r3, r3, #6 80048dc: 4013 ands r3, r2 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 80048de: d00b beq.n 80048f8 <HAL_TIM_IRQHandler+0x198> { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80048e0: 68fb ldr r3, [r7, #12] 80048e2: 2280 movs r2, #128 @ 0x80 80048e4: 4013 ands r3, r2 80048e6: d007 beq.n 80048f8 <HAL_TIM_IRQHandler+0x198> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 80048e8: 687b ldr r3, [r7, #4] 80048ea: 681b ldr r3, [r3, #0] 80048ec: 4a1e ldr r2, [pc, #120] @ (8004968 <HAL_TIM_IRQHandler+0x208>) 80048ee: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80048f0: 687b ldr r3, [r7, #4] 80048f2: 0018 movs r0, r3 80048f4: f000 f8e8 bl 8004ac8 <HAL_TIMEx_BreakCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 80048f8: 68ba ldr r2, [r7, #8] 80048fa: 2380 movs r3, #128 @ 0x80 80048fc: 005b lsls r3, r3, #1 80048fe: 4013 ands r3, r2 8004900: d00b beq.n 800491a <HAL_TIM_IRQHandler+0x1ba> { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8004902: 68fb ldr r3, [r7, #12] 8004904: 2280 movs r2, #128 @ 0x80 8004906: 4013 ands r3, r2 8004908: d007 beq.n 800491a <HAL_TIM_IRQHandler+0x1ba> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800490a: 687b ldr r3, [r7, #4] 800490c: 681b ldr r3, [r3, #0] 800490e: 4a17 ldr r2, [pc, #92] @ (800496c <HAL_TIM_IRQHandler+0x20c>) 8004910: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8004912: 687b ldr r3, [r7, #4] 8004914: 0018 movs r0, r3 8004916: f000 f8df bl 8004ad8 <HAL_TIMEx_Break2Callback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800491a: 68bb ldr r3, [r7, #8] 800491c: 2240 movs r2, #64 @ 0x40 800491e: 4013 ands r3, r2 8004920: d00c beq.n 800493c <HAL_TIM_IRQHandler+0x1dc> { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8004922: 68fb ldr r3, [r7, #12] 8004924: 2240 movs r2, #64 @ 0x40 8004926: 4013 ands r3, r2 8004928: d008 beq.n 800493c <HAL_TIM_IRQHandler+0x1dc> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800492a: 687b ldr r3, [r7, #4] 800492c: 681b ldr r3, [r3, #0] 800492e: 2241 movs r2, #65 @ 0x41 8004930: 4252 negs r2, r2 8004932: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8004934: 687b ldr r3, [r7, #4] 8004936: 0018 movs r0, r3 8004938: f000 f832 bl 80049a0 <HAL_TIM_TriggerCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800493c: 68bb ldr r3, [r7, #8] 800493e: 2220 movs r2, #32 8004940: 4013 ands r3, r2 8004942: d00c beq.n 800495e <HAL_TIM_IRQHandler+0x1fe> { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8004944: 68fb ldr r3, [r7, #12] 8004946: 2220 movs r2, #32 8004948: 4013 ands r3, r2 800494a: d008 beq.n 800495e <HAL_TIM_IRQHandler+0x1fe> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800494c: 687b ldr r3, [r7, #4] 800494e: 681b ldr r3, [r3, #0] 8004950: 2221 movs r2, #33 @ 0x21 8004952: 4252 negs r2, r2 8004954: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8004956: 687b ldr r3, [r7, #4] 8004958: 0018 movs r0, r3 800495a: f000 f8ad bl 8004ab8 <HAL_TIMEx_CommutCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800495e: 46c0 nop @ (mov r8, r8) 8004960: 46bd mov sp, r7 8004962: b004 add sp, #16 8004964: bd80 pop {r7, pc} 8004966: 46c0 nop @ (mov r8, r8) 8004968: ffffdf7f .word 0xffffdf7f 800496c: fffffeff .word 0xfffffeff 08004970 <HAL_TIM_OC_DelayElapsedCallback>: * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8004970: b580 push {r7, lr} 8004972: b082 sub sp, #8 8004974: af00 add r7, sp, #0 8004976: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8004978: 46c0 nop @ (mov r8, r8) 800497a: 46bd mov sp, r7 800497c: b002 add sp, #8 800497e: bd80 pop {r7, pc} 08004980 <HAL_TIM_IC_CaptureCallback>: * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8004980: b580 push {r7, lr} 8004982: b082 sub sp, #8 8004984: af00 add r7, sp, #0 8004986: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8004988: 46c0 nop @ (mov r8, r8) 800498a: 46bd mov sp, r7 800498c: b002 add sp, #8 800498e: bd80 pop {r7, pc} 08004990 <HAL_TIM_PWM_PulseFinishedCallback>: * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8004990: b580 push {r7, lr} 8004992: b082 sub sp, #8 8004994: af00 add r7, sp, #0 8004996: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8004998: 46c0 nop @ (mov r8, r8) 800499a: 46bd mov sp, r7 800499c: b002 add sp, #8 800499e: bd80 pop {r7, pc} 080049a0 <HAL_TIM_TriggerCallback>: * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80049a0: b580 push {r7, lr} 80049a2: b082 sub sp, #8 80049a4: af00 add r7, sp, #0 80049a6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80049a8: 46c0 nop @ (mov r8, r8) 80049aa: 46bd mov sp, r7 80049ac: b002 add sp, #8 80049ae: bd80 pop {r7, pc} 080049b0 <TIM_Base_SetConfig>: * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80049b0: b580 push {r7, lr} 80049b2: b084 sub sp, #16 80049b4: af00 add r7, sp, #0 80049b6: 6078 str r0, [r7, #4] 80049b8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80049ba: 687b ldr r3, [r7, #4] 80049bc: 681b ldr r3, [r3, #0] 80049be: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80049c0: 687b ldr r3, [r7, #4] 80049c2: 4a37 ldr r2, [pc, #220] @ (8004aa0 <TIM_Base_SetConfig+0xf0>) 80049c4: 4293 cmp r3, r2 80049c6: d008 beq.n 80049da <TIM_Base_SetConfig+0x2a> 80049c8: 687a ldr r2, [r7, #4] 80049ca: 2380 movs r3, #128 @ 0x80 80049cc: 05db lsls r3, r3, #23 80049ce: 429a cmp r2, r3 80049d0: d003 beq.n 80049da <TIM_Base_SetConfig+0x2a> 80049d2: 687b ldr r3, [r7, #4] 80049d4: 4a33 ldr r2, [pc, #204] @ (8004aa4 <TIM_Base_SetConfig+0xf4>) 80049d6: 4293 cmp r3, r2 80049d8: d108 bne.n 80049ec <TIM_Base_SetConfig+0x3c> { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80049da: 68fb ldr r3, [r7, #12] 80049dc: 2270 movs r2, #112 @ 0x70 80049de: 4393 bics r3, r2 80049e0: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80049e2: 683b ldr r3, [r7, #0] 80049e4: 685b ldr r3, [r3, #4] 80049e6: 68fa ldr r2, [r7, #12] 80049e8: 4313 orrs r3, r2 80049ea: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80049ec: 687b ldr r3, [r7, #4] 80049ee: 4a2c ldr r2, [pc, #176] @ (8004aa0 <TIM_Base_SetConfig+0xf0>) 80049f0: 4293 cmp r3, r2 80049f2: d014 beq.n 8004a1e <TIM_Base_SetConfig+0x6e> 80049f4: 687a ldr r2, [r7, #4] 80049f6: 2380 movs r3, #128 @ 0x80 80049f8: 05db lsls r3, r3, #23 80049fa: 429a cmp r2, r3 80049fc: d00f beq.n 8004a1e <TIM_Base_SetConfig+0x6e> 80049fe: 687b ldr r3, [r7, #4] 8004a00: 4a28 ldr r2, [pc, #160] @ (8004aa4 <TIM_Base_SetConfig+0xf4>) 8004a02: 4293 cmp r3, r2 8004a04: d00b beq.n 8004a1e <TIM_Base_SetConfig+0x6e> 8004a06: 687b ldr r3, [r7, #4] 8004a08: 4a27 ldr r2, [pc, #156] @ (8004aa8 <TIM_Base_SetConfig+0xf8>) 8004a0a: 4293 cmp r3, r2 8004a0c: d007 beq.n 8004a1e <TIM_Base_SetConfig+0x6e> 8004a0e: 687b ldr r3, [r7, #4] 8004a10: 4a26 ldr r2, [pc, #152] @ (8004aac <TIM_Base_SetConfig+0xfc>) 8004a12: 4293 cmp r3, r2 8004a14: d003 beq.n 8004a1e <TIM_Base_SetConfig+0x6e> 8004a16: 687b ldr r3, [r7, #4] 8004a18: 4a25 ldr r2, [pc, #148] @ (8004ab0 <TIM_Base_SetConfig+0x100>) 8004a1a: 4293 cmp r3, r2 8004a1c: d108 bne.n 8004a30 <TIM_Base_SetConfig+0x80> { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8004a1e: 68fb ldr r3, [r7, #12] 8004a20: 4a24 ldr r2, [pc, #144] @ (8004ab4 <TIM_Base_SetConfig+0x104>) 8004a22: 4013 ands r3, r2 8004a24: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a26: 683b ldr r3, [r7, #0] 8004a28: 68db ldr r3, [r3, #12] 8004a2a: 68fa ldr r2, [r7, #12] 8004a2c: 4313 orrs r3, r2 8004a2e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004a30: 68fb ldr r3, [r7, #12] 8004a32: 2280 movs r2, #128 @ 0x80 8004a34: 4393 bics r3, r2 8004a36: 001a movs r2, r3 8004a38: 683b ldr r3, [r7, #0] 8004a3a: 695b ldr r3, [r3, #20] 8004a3c: 4313 orrs r3, r2 8004a3e: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8004a40: 687b ldr r3, [r7, #4] 8004a42: 68fa ldr r2, [r7, #12] 8004a44: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8004a46: 683b ldr r3, [r7, #0] 8004a48: 689a ldr r2, [r3, #8] 8004a4a: 687b ldr r3, [r7, #4] 8004a4c: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004a4e: 683b ldr r3, [r7, #0] 8004a50: 681a ldr r2, [r3, #0] 8004a52: 687b ldr r3, [r7, #4] 8004a54: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004a56: 687b ldr r3, [r7, #4] 8004a58: 4a11 ldr r2, [pc, #68] @ (8004aa0 <TIM_Base_SetConfig+0xf0>) 8004a5a: 4293 cmp r3, r2 8004a5c: d007 beq.n 8004a6e <TIM_Base_SetConfig+0xbe> 8004a5e: 687b ldr r3, [r7, #4] 8004a60: 4a12 ldr r2, [pc, #72] @ (8004aac <TIM_Base_SetConfig+0xfc>) 8004a62: 4293 cmp r3, r2 8004a64: d003 beq.n 8004a6e <TIM_Base_SetConfig+0xbe> 8004a66: 687b ldr r3, [r7, #4] 8004a68: 4a11 ldr r2, [pc, #68] @ (8004ab0 <TIM_Base_SetConfig+0x100>) 8004a6a: 4293 cmp r3, r2 8004a6c: d103 bne.n 8004a76 <TIM_Base_SetConfig+0xc6> { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8004a6e: 683b ldr r3, [r7, #0] 8004a70: 691a ldr r2, [r3, #16] 8004a72: 687b ldr r3, [r7, #4] 8004a74: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8004a76: 687b ldr r3, [r7, #4] 8004a78: 2201 movs r2, #1 8004a7a: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8004a7c: 687b ldr r3, [r7, #4] 8004a7e: 691b ldr r3, [r3, #16] 8004a80: 2201 movs r2, #1 8004a82: 4013 ands r3, r2 8004a84: 2b01 cmp r3, #1 8004a86: d106 bne.n 8004a96 <TIM_Base_SetConfig+0xe6> { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8004a88: 687b ldr r3, [r7, #4] 8004a8a: 691b ldr r3, [r3, #16] 8004a8c: 2201 movs r2, #1 8004a8e: 4393 bics r3, r2 8004a90: 001a movs r2, r3 8004a92: 687b ldr r3, [r7, #4] 8004a94: 611a str r2, [r3, #16] } } 8004a96: 46c0 nop @ (mov r8, r8) 8004a98: 46bd mov sp, r7 8004a9a: b004 add sp, #16 8004a9c: bd80 pop {r7, pc} 8004a9e: 46c0 nop @ (mov r8, r8) 8004aa0: 40012c00 .word 0x40012c00 8004aa4: 40000400 .word 0x40000400 8004aa8: 40002000 .word 0x40002000 8004aac: 40014400 .word 0x40014400 8004ab0: 40014800 .word 0x40014800 8004ab4: fffffcff .word 0xfffffcff 08004ab8 <HAL_TIMEx_CommutCallback>: * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8004ab8: b580 push {r7, lr} 8004aba: b082 sub sp, #8 8004abc: af00 add r7, sp, #0 8004abe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8004ac0: 46c0 nop @ (mov r8, r8) 8004ac2: 46bd mov sp, r7 8004ac4: b002 add sp, #8 8004ac6: bd80 pop {r7, pc} 08004ac8 <HAL_TIMEx_BreakCallback>: * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8004ac8: b580 push {r7, lr} 8004aca: b082 sub sp, #8 8004acc: af00 add r7, sp, #0 8004ace: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8004ad0: 46c0 nop @ (mov r8, r8) 8004ad2: 46bd mov sp, r7 8004ad4: b002 add sp, #8 8004ad6: bd80 pop {r7, pc} 08004ad8 <HAL_TIMEx_Break2Callback>: * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8004ad8: b580 push {r7, lr} 8004ada: b082 sub sp, #8 8004adc: af00 add r7, sp, #0 8004ade: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8004ae0: 46c0 nop @ (mov r8, r8) 8004ae2: 46bd mov sp, r7 8004ae4: b002 add sp, #8 8004ae6: bd80 pop {r7, pc} 08004ae8 <memset>: 8004ae8: 0003 movs r3, r0 8004aea: 1882 adds r2, r0, r2 8004aec: 4293 cmp r3, r2 8004aee: d100 bne.n 8004af2 <memset+0xa> 8004af0: 4770 bx lr 8004af2: 7019 strb r1, [r3, #0] 8004af4: 3301 adds r3, #1 8004af6: e7f9 b.n 8004aec <memset+0x4> 08004af8 <__libc_init_array>: 8004af8: b570 push {r4, r5, r6, lr} 8004afa: 2600 movs r6, #0 8004afc: 4c0c ldr r4, [pc, #48] @ (8004b30 <__libc_init_array+0x38>) 8004afe: 4d0d ldr r5, [pc, #52] @ (8004b34 <__libc_init_array+0x3c>) 8004b00: 1b64 subs r4, r4, r5 8004b02: 10a4 asrs r4, r4, #2 8004b04: 42a6 cmp r6, r4 8004b06: d109 bne.n 8004b1c <__libc_init_array+0x24> 8004b08: 2600 movs r6, #0 8004b0a: f000 ffe5 bl 8005ad8 <_init> 8004b0e: 4c0a ldr r4, [pc, #40] @ (8004b38 <__libc_init_array+0x40>) 8004b10: 4d0a ldr r5, [pc, #40] @ (8004b3c <__libc_init_array+0x44>) 8004b12: 1b64 subs r4, r4, r5 8004b14: 10a4 asrs r4, r4, #2 8004b16: 42a6 cmp r6, r4 8004b18: d105 bne.n 8004b26 <__libc_init_array+0x2e> 8004b1a: bd70 pop {r4, r5, r6, pc} 8004b1c: 00b3 lsls r3, r6, #2 8004b1e: 58eb ldr r3, [r5, r3] 8004b20: 4798 blx r3 8004b22: 3601 adds r6, #1 8004b24: e7ee b.n 8004b04 <__libc_init_array+0xc> 8004b26: 00b3 lsls r3, r6, #2 8004b28: 58eb ldr r3, [r5, r3] 8004b2a: 4798 blx r3 8004b2c: 3601 adds r6, #1 8004b2e: e7f2 b.n 8004b16 <__libc_init_array+0x1e> 8004b30: 08005d48 .word 0x08005d48 8004b34: 08005d48 .word 0x08005d48 8004b38: 08005d4c .word 0x08005d4c 8004b3c: 08005d48 .word 0x08005d48 08004b40 <sin>: 8004b40: b530 push {r4, r5, lr} 8004b42: 4a1f ldr r2, [pc, #124] @ (8004bc0 <sin+0x80>) 8004b44: 004b lsls r3, r1, #1 8004b46: b087 sub sp, #28 8004b48: 085b lsrs r3, r3, #1 8004b4a: 4293 cmp r3, r2 8004b4c: d806 bhi.n 8004b5c <sin+0x1c> 8004b4e: 2300 movs r3, #0 8004b50: 2200 movs r2, #0 8004b52: 9300 str r3, [sp, #0] 8004b54: 2300 movs r3, #0 8004b56: f000 f8f7 bl 8004d48 <__kernel_sin> 8004b5a: e006 b.n 8004b6a <sin+0x2a> 8004b5c: 4a19 ldr r2, [pc, #100] @ (8004bc4 <sin+0x84>) 8004b5e: 4293 cmp r3, r2 8004b60: d905 bls.n 8004b6e <sin+0x2e> 8004b62: 0002 movs r2, r0 8004b64: 000b movs r3, r1 8004b66: f7fc ffcb bl 8001b00 <__aeabi_dsub> 8004b6a: b007 add sp, #28 8004b6c: bd30 pop {r4, r5, pc} 8004b6e: aa02 add r2, sp, #8 8004b70: f000 f996 bl 8004ea0 <__ieee754_rem_pio2> 8004b74: 9c04 ldr r4, [sp, #16] 8004b76: 9d05 ldr r5, [sp, #20] 8004b78: 2303 movs r3, #3 8004b7a: 4003 ands r3, r0 8004b7c: 9802 ldr r0, [sp, #8] 8004b7e: 9903 ldr r1, [sp, #12] 8004b80: 2b01 cmp r3, #1 8004b82: d008 beq.n 8004b96 <sin+0x56> 8004b84: 2b02 cmp r3, #2 8004b86: d00b beq.n 8004ba0 <sin+0x60> 8004b88: 2b00 cmp r3, #0 8004b8a: d113 bne.n 8004bb4 <sin+0x74> 8004b8c: 3301 adds r3, #1 8004b8e: 9300 str r3, [sp, #0] 8004b90: 0022 movs r2, r4 8004b92: 002b movs r3, r5 8004b94: e7df b.n 8004b56 <sin+0x16> 8004b96: 0022 movs r2, r4 8004b98: 002b movs r3, r5 8004b9a: f000 f815 bl 8004bc8 <__kernel_cos> 8004b9e: e7e4 b.n 8004b6a <sin+0x2a> 8004ba0: 2301 movs r3, #1 8004ba2: 0022 movs r2, r4 8004ba4: 9300 str r3, [sp, #0] 8004ba6: 002b movs r3, r5 8004ba8: f000 f8ce bl 8004d48 <__kernel_sin> 8004bac: 2380 movs r3, #128 @ 0x80 8004bae: 061b lsls r3, r3, #24 8004bb0: 18c9 adds r1, r1, r3 8004bb2: e7da b.n 8004b6a <sin+0x2a> 8004bb4: 0022 movs r2, r4 8004bb6: 002b movs r3, r5 8004bb8: f000 f806 bl 8004bc8 <__kernel_cos> 8004bbc: e7f6 b.n 8004bac <sin+0x6c> 8004bbe: 46c0 nop @ (mov r8, r8) 8004bc0: 3fe921fb .word 0x3fe921fb 8004bc4: 7fefffff .word 0x7fefffff 08004bc8 <__kernel_cos>: 8004bc8: b5f0 push {r4, r5, r6, r7, lr} 8004bca: b087 sub sp, #28 8004bcc: 9204 str r2, [sp, #16] 8004bce: 9305 str r3, [sp, #20] 8004bd0: 004b lsls r3, r1, #1 8004bd2: 085b lsrs r3, r3, #1 8004bd4: 9301 str r3, [sp, #4] 8004bd6: 23f9 movs r3, #249 @ 0xf9 8004bd8: 9a01 ldr r2, [sp, #4] 8004bda: 0004 movs r4, r0 8004bdc: 000d movs r5, r1 8004bde: 059b lsls r3, r3, #22 8004be0: 429a cmp r2, r3 8004be2: d204 bcs.n 8004bee <__kernel_cos+0x26> 8004be4: f7fd fb96 bl 8002314 <__aeabi_d2iz> 8004be8: 2800 cmp r0, #0 8004bea: d100 bne.n 8004bee <__kernel_cos+0x26> 8004bec: e084 b.n 8004cf8 <__kernel_cos+0x130> 8004bee: 0022 movs r2, r4 8004bf0: 002b movs r3, r5 8004bf2: 0020 movs r0, r4 8004bf4: 0029 movs r1, r5 8004bf6: f7fc fc9d bl 8001534 <__aeabi_dmul> 8004bfa: 2200 movs r2, #0 8004bfc: 4b40 ldr r3, [pc, #256] @ (8004d00 <__kernel_cos+0x138>) 8004bfe: 0006 movs r6, r0 8004c00: 000f movs r7, r1 8004c02: f7fc fc97 bl 8001534 <__aeabi_dmul> 8004c06: 4a3f ldr r2, [pc, #252] @ (8004d04 <__kernel_cos+0x13c>) 8004c08: 9002 str r0, [sp, #8] 8004c0a: 9103 str r1, [sp, #12] 8004c0c: 4b3e ldr r3, [pc, #248] @ (8004d08 <__kernel_cos+0x140>) 8004c0e: 0030 movs r0, r6 8004c10: 0039 movs r1, r7 8004c12: f7fc fc8f bl 8001534 <__aeabi_dmul> 8004c16: 4a3d ldr r2, [pc, #244] @ (8004d0c <__kernel_cos+0x144>) 8004c18: 4b3d ldr r3, [pc, #244] @ (8004d10 <__kernel_cos+0x148>) 8004c1a: f7fb fc8b bl 8000534 <__aeabi_dadd> 8004c1e: 0032 movs r2, r6 8004c20: 003b movs r3, r7 8004c22: f7fc fc87 bl 8001534 <__aeabi_dmul> 8004c26: 4a3b ldr r2, [pc, #236] @ (8004d14 <__kernel_cos+0x14c>) 8004c28: 4b3b ldr r3, [pc, #236] @ (8004d18 <__kernel_cos+0x150>) 8004c2a: f7fc ff69 bl 8001b00 <__aeabi_dsub> 8004c2e: 0032 movs r2, r6 8004c30: 003b movs r3, r7 8004c32: f7fc fc7f bl 8001534 <__aeabi_dmul> 8004c36: 4a39 ldr r2, [pc, #228] @ (8004d1c <__kernel_cos+0x154>) 8004c38: 4b39 ldr r3, [pc, #228] @ (8004d20 <__kernel_cos+0x158>) 8004c3a: f7fb fc7b bl 8000534 <__aeabi_dadd> 8004c3e: 0032 movs r2, r6 8004c40: 003b movs r3, r7 8004c42: f7fc fc77 bl 8001534 <__aeabi_dmul> 8004c46: 4a37 ldr r2, [pc, #220] @ (8004d24 <__kernel_cos+0x15c>) 8004c48: 4b37 ldr r3, [pc, #220] @ (8004d28 <__kernel_cos+0x160>) 8004c4a: f7fc ff59 bl 8001b00 <__aeabi_dsub> 8004c4e: 0032 movs r2, r6 8004c50: 003b movs r3, r7 8004c52: f7fc fc6f bl 8001534 <__aeabi_dmul> 8004c56: 4a35 ldr r2, [pc, #212] @ (8004d2c <__kernel_cos+0x164>) 8004c58: 4b35 ldr r3, [pc, #212] @ (8004d30 <__kernel_cos+0x168>) 8004c5a: f7fb fc6b bl 8000534 <__aeabi_dadd> 8004c5e: 0032 movs r2, r6 8004c60: 003b movs r3, r7 8004c62: f7fc fc67 bl 8001534 <__aeabi_dmul> 8004c66: 0032 movs r2, r6 8004c68: 003b movs r3, r7 8004c6a: f7fc fc63 bl 8001534 <__aeabi_dmul> 8004c6e: 9a04 ldr r2, [sp, #16] 8004c70: 9b05 ldr r3, [sp, #20] 8004c72: 0006 movs r6, r0 8004c74: 000f movs r7, r1 8004c76: 0020 movs r0, r4 8004c78: 0029 movs r1, r5 8004c7a: f7fc fc5b bl 8001534 <__aeabi_dmul> 8004c7e: 0002 movs r2, r0 8004c80: 000b movs r3, r1 8004c82: 0030 movs r0, r6 8004c84: 0039 movs r1, r7 8004c86: f7fc ff3b bl 8001b00 <__aeabi_dsub> 8004c8a: 4b2a ldr r3, [pc, #168] @ (8004d34 <__kernel_cos+0x16c>) 8004c8c: 9a01 ldr r2, [sp, #4] 8004c8e: 9004 str r0, [sp, #16] 8004c90: 9105 str r1, [sp, #20] 8004c92: 429a cmp r2, r3 8004c94: d80d bhi.n 8004cb2 <__kernel_cos+0xea> 8004c96: 0002 movs r2, r0 8004c98: 000b movs r3, r1 8004c9a: 9802 ldr r0, [sp, #8] 8004c9c: 9903 ldr r1, [sp, #12] 8004c9e: f7fc ff2f bl 8001b00 <__aeabi_dsub> 8004ca2: 0002 movs r2, r0 8004ca4: 2000 movs r0, #0 8004ca6: 000b movs r3, r1 8004ca8: 4923 ldr r1, [pc, #140] @ (8004d38 <__kernel_cos+0x170>) 8004caa: f7fc ff29 bl 8001b00 <__aeabi_dsub> 8004cae: b007 add sp, #28 8004cb0: bdf0 pop {r4, r5, r6, r7, pc} 8004cb2: 4b22 ldr r3, [pc, #136] @ (8004d3c <__kernel_cos+0x174>) 8004cb4: 9a01 ldr r2, [sp, #4] 8004cb6: 2600 movs r6, #0 8004cb8: 429a cmp r2, r3 8004cba: d81b bhi.n 8004cf4 <__kernel_cos+0x12c> 8004cbc: 0013 movs r3, r2 8004cbe: 4a20 ldr r2, [pc, #128] @ (8004d40 <__kernel_cos+0x178>) 8004cc0: 4694 mov ip, r2 8004cc2: 4463 add r3, ip 8004cc4: 001f movs r7, r3 8004cc6: 0032 movs r2, r6 8004cc8: 003b movs r3, r7 8004cca: 2000 movs r0, #0 8004ccc: 491a ldr r1, [pc, #104] @ (8004d38 <__kernel_cos+0x170>) 8004cce: f7fc ff17 bl 8001b00 <__aeabi_dsub> 8004cd2: 0032 movs r2, r6 8004cd4: 0004 movs r4, r0 8004cd6: 000d movs r5, r1 8004cd8: 9802 ldr r0, [sp, #8] 8004cda: 9903 ldr r1, [sp, #12] 8004cdc: 003b movs r3, r7 8004cde: f7fc ff0f bl 8001b00 <__aeabi_dsub> 8004ce2: 9a04 ldr r2, [sp, #16] 8004ce4: 9b05 ldr r3, [sp, #20] 8004ce6: f7fc ff0b bl 8001b00 <__aeabi_dsub> 8004cea: 0002 movs r2, r0 8004cec: 000b movs r3, r1 8004cee: 0020 movs r0, r4 8004cf0: 0029 movs r1, r5 8004cf2: e7da b.n 8004caa <__kernel_cos+0xe2> 8004cf4: 4f13 ldr r7, [pc, #76] @ (8004d44 <__kernel_cos+0x17c>) 8004cf6: e7e6 b.n 8004cc6 <__kernel_cos+0xfe> 8004cf8: 2000 movs r0, #0 8004cfa: 490f ldr r1, [pc, #60] @ (8004d38 <__kernel_cos+0x170>) 8004cfc: e7d7 b.n 8004cae <__kernel_cos+0xe6> 8004cfe: 46c0 nop @ (mov r8, r8) 8004d00: 3fe00000 .word 0x3fe00000 8004d04: be8838d4 .word 0xbe8838d4 8004d08: bda8fae9 .word 0xbda8fae9 8004d0c: bdb4b1c4 .word 0xbdb4b1c4 8004d10: 3e21ee9e .word 0x3e21ee9e 8004d14: 809c52ad .word 0x809c52ad 8004d18: 3e927e4f .word 0x3e927e4f 8004d1c: 19cb1590 .word 0x19cb1590 8004d20: 3efa01a0 .word 0x3efa01a0 8004d24: 16c15177 .word 0x16c15177 8004d28: 3f56c16c .word 0x3f56c16c 8004d2c: 5555554c .word 0x5555554c 8004d30: 3fa55555 .word 0x3fa55555 8004d34: 3fd33332 .word 0x3fd33332 8004d38: 3ff00000 .word 0x3ff00000 8004d3c: 3fe90000 .word 0x3fe90000 8004d40: ffe00000 .word 0xffe00000 8004d44: 3fd20000 .word 0x3fd20000 08004d48 <__kernel_sin>: 8004d48: b5f0 push {r4, r5, r6, r7, lr} 8004d4a: b089 sub sp, #36 @ 0x24 8004d4c: 9202 str r2, [sp, #8] 8004d4e: 9303 str r3, [sp, #12] 8004d50: 22f9 movs r2, #249 @ 0xf9 8004d52: 004b lsls r3, r1, #1 8004d54: 0006 movs r6, r0 8004d56: 000f movs r7, r1 8004d58: 085b lsrs r3, r3, #1 8004d5a: 0592 lsls r2, r2, #22 8004d5c: 4293 cmp r3, r2 8004d5e: d203 bcs.n 8004d68 <__kernel_sin+0x20> 8004d60: f7fd fad8 bl 8002314 <__aeabi_d2iz> 8004d64: 2800 cmp r0, #0 8004d66: d04c beq.n 8004e02 <__kernel_sin+0xba> 8004d68: 0032 movs r2, r6 8004d6a: 003b movs r3, r7 8004d6c: 0030 movs r0, r6 8004d6e: 0039 movs r1, r7 8004d70: f7fc fbe0 bl 8001534 <__aeabi_dmul> 8004d74: 0004 movs r4, r0 8004d76: 000d movs r5, r1 8004d78: 0002 movs r2, r0 8004d7a: 000b movs r3, r1 8004d7c: 0030 movs r0, r6 8004d7e: 0039 movs r1, r7 8004d80: f7fc fbd8 bl 8001534 <__aeabi_dmul> 8004d84: 4a39 ldr r2, [pc, #228] @ (8004e6c <__kernel_sin+0x124>) 8004d86: 9000 str r0, [sp, #0] 8004d88: 9101 str r1, [sp, #4] 8004d8a: 4b39 ldr r3, [pc, #228] @ (8004e70 <__kernel_sin+0x128>) 8004d8c: 0020 movs r0, r4 8004d8e: 0029 movs r1, r5 8004d90: f7fc fbd0 bl 8001534 <__aeabi_dmul> 8004d94: 4a37 ldr r2, [pc, #220] @ (8004e74 <__kernel_sin+0x12c>) 8004d96: 4b38 ldr r3, [pc, #224] @ (8004e78 <__kernel_sin+0x130>) 8004d98: f7fc feb2 bl 8001b00 <__aeabi_dsub> 8004d9c: 0022 movs r2, r4 8004d9e: 002b movs r3, r5 8004da0: f7fc fbc8 bl 8001534 <__aeabi_dmul> 8004da4: 4a35 ldr r2, [pc, #212] @ (8004e7c <__kernel_sin+0x134>) 8004da6: 4b36 ldr r3, [pc, #216] @ (8004e80 <__kernel_sin+0x138>) 8004da8: f7fb fbc4 bl 8000534 <__aeabi_dadd> 8004dac: 0022 movs r2, r4 8004dae: 002b movs r3, r5 8004db0: f7fc fbc0 bl 8001534 <__aeabi_dmul> 8004db4: 4a33 ldr r2, [pc, #204] @ (8004e84 <__kernel_sin+0x13c>) 8004db6: 4b34 ldr r3, [pc, #208] @ (8004e88 <__kernel_sin+0x140>) 8004db8: f7fc fea2 bl 8001b00 <__aeabi_dsub> 8004dbc: 0022 movs r2, r4 8004dbe: 002b movs r3, r5 8004dc0: f7fc fbb8 bl 8001534 <__aeabi_dmul> 8004dc4: 4b31 ldr r3, [pc, #196] @ (8004e8c <__kernel_sin+0x144>) 8004dc6: 4a32 ldr r2, [pc, #200] @ (8004e90 <__kernel_sin+0x148>) 8004dc8: f7fb fbb4 bl 8000534 <__aeabi_dadd> 8004dcc: 9b0e ldr r3, [sp, #56] @ 0x38 8004dce: 9004 str r0, [sp, #16] 8004dd0: 9105 str r1, [sp, #20] 8004dd2: 2b00 cmp r3, #0 8004dd4: d119 bne.n 8004e0a <__kernel_sin+0xc2> 8004dd6: 0002 movs r2, r0 8004dd8: 000b movs r3, r1 8004dda: 0020 movs r0, r4 8004ddc: 0029 movs r1, r5 8004dde: f7fc fba9 bl 8001534 <__aeabi_dmul> 8004de2: 4a2c ldr r2, [pc, #176] @ (8004e94 <__kernel_sin+0x14c>) 8004de4: 4b2c ldr r3, [pc, #176] @ (8004e98 <__kernel_sin+0x150>) 8004de6: f7fc fe8b bl 8001b00 <__aeabi_dsub> 8004dea: 9a00 ldr r2, [sp, #0] 8004dec: 9b01 ldr r3, [sp, #4] 8004dee: f7fc fba1 bl 8001534 <__aeabi_dmul> 8004df2: 0002 movs r2, r0 8004df4: 000b movs r3, r1 8004df6: 0030 movs r0, r6 8004df8: 0039 movs r1, r7 8004dfa: f7fb fb9b bl 8000534 <__aeabi_dadd> 8004dfe: 0006 movs r6, r0 8004e00: 000f movs r7, r1 8004e02: 0030 movs r0, r6 8004e04: 0039 movs r1, r7 8004e06: b009 add sp, #36 @ 0x24 8004e08: bdf0 pop {r4, r5, r6, r7, pc} 8004e0a: 2200 movs r2, #0 8004e0c: 9802 ldr r0, [sp, #8] 8004e0e: 9903 ldr r1, [sp, #12] 8004e10: 4b22 ldr r3, [pc, #136] @ (8004e9c <__kernel_sin+0x154>) 8004e12: f7fc fb8f bl 8001534 <__aeabi_dmul> 8004e16: 9a04 ldr r2, [sp, #16] 8004e18: 9b05 ldr r3, [sp, #20] 8004e1a: 9006 str r0, [sp, #24] 8004e1c: 9107 str r1, [sp, #28] 8004e1e: 9800 ldr r0, [sp, #0] 8004e20: 9901 ldr r1, [sp, #4] 8004e22: f7fc fb87 bl 8001534 <__aeabi_dmul> 8004e26: 0002 movs r2, r0 8004e28: 000b movs r3, r1 8004e2a: 9806 ldr r0, [sp, #24] 8004e2c: 9907 ldr r1, [sp, #28] 8004e2e: f7fc fe67 bl 8001b00 <__aeabi_dsub> 8004e32: 0022 movs r2, r4 8004e34: 002b movs r3, r5 8004e36: f7fc fb7d bl 8001534 <__aeabi_dmul> 8004e3a: 9a02 ldr r2, [sp, #8] 8004e3c: 9b03 ldr r3, [sp, #12] 8004e3e: f7fc fe5f bl 8001b00 <__aeabi_dsub> 8004e42: 4a14 ldr r2, [pc, #80] @ (8004e94 <__kernel_sin+0x14c>) 8004e44: 0004 movs r4, r0 8004e46: 000d movs r5, r1 8004e48: 9800 ldr r0, [sp, #0] 8004e4a: 9901 ldr r1, [sp, #4] 8004e4c: 4b12 ldr r3, [pc, #72] @ (8004e98 <__kernel_sin+0x150>) 8004e4e: f7fc fb71 bl 8001534 <__aeabi_dmul> 8004e52: 0002 movs r2, r0 8004e54: 000b movs r3, r1 8004e56: 0020 movs r0, r4 8004e58: 0029 movs r1, r5 8004e5a: f7fb fb6b bl 8000534 <__aeabi_dadd> 8004e5e: 0002 movs r2, r0 8004e60: 000b movs r3, r1 8004e62: 0030 movs r0, r6 8004e64: 0039 movs r1, r7 8004e66: f7fc fe4b bl 8001b00 <__aeabi_dsub> 8004e6a: e7c8 b.n 8004dfe <__kernel_sin+0xb6> 8004e6c: 5acfd57c .word 0x5acfd57c 8004e70: 3de5d93a .word 0x3de5d93a 8004e74: 8a2b9ceb .word 0x8a2b9ceb 8004e78: 3e5ae5e6 .word 0x3e5ae5e6 8004e7c: 57b1fe7d .word 0x57b1fe7d 8004e80: 3ec71de3 .word 0x3ec71de3 8004e84: 19c161d5 .word 0x19c161d5 8004e88: 3f2a01a0 .word 0x3f2a01a0 8004e8c: 3f811111 .word 0x3f811111 8004e90: 1110f8a6 .word 0x1110f8a6 8004e94: 55555549 .word 0x55555549 8004e98: 3fc55555 .word 0x3fc55555 8004e9c: 3fe00000 .word 0x3fe00000 08004ea0 <__ieee754_rem_pio2>: 8004ea0: b5f0 push {r4, r5, r6, r7, lr} 8004ea2: 4baf ldr r3, [pc, #700] @ (8005160 <__ieee754_rem_pio2+0x2c0>) 8004ea4: b095 sub sp, #84 @ 0x54 8004ea6: 004d lsls r5, r1, #1 8004ea8: 0017 movs r7, r2 8004eaa: 910d str r1, [sp, #52] @ 0x34 8004eac: 086d lsrs r5, r5, #1 8004eae: 429d cmp r5, r3 8004eb0: d807 bhi.n 8004ec2 <__ieee754_rem_pio2+0x22> 8004eb2: 6010 str r0, [r2, #0] 8004eb4: 6051 str r1, [r2, #4] 8004eb6: 2300 movs r3, #0 8004eb8: 2200 movs r2, #0 8004eba: 60ba str r2, [r7, #8] 8004ebc: 60fb str r3, [r7, #12] 8004ebe: 2300 movs r3, #0 8004ec0: e024 b.n 8004f0c <__ieee754_rem_pio2+0x6c> 8004ec2: 4ba8 ldr r3, [pc, #672] @ (8005164 <__ieee754_rem_pio2+0x2c4>) 8004ec4: 429d cmp r5, r3 8004ec6: d900 bls.n 8004eca <__ieee754_rem_pio2+0x2a> 8004ec8: e072 b.n 8004fb0 <__ieee754_rem_pio2+0x110> 8004eca: 9b0d ldr r3, [sp, #52] @ 0x34 8004ecc: 4ca6 ldr r4, [pc, #664] @ (8005168 <__ieee754_rem_pio2+0x2c8>) 8004ece: 4aa7 ldr r2, [pc, #668] @ (800516c <__ieee754_rem_pio2+0x2cc>) 8004ed0: 2b00 cmp r3, #0 8004ed2: dd37 ble.n 8004f44 <__ieee754_rem_pio2+0xa4> 8004ed4: 4ba4 ldr r3, [pc, #656] @ (8005168 <__ieee754_rem_pio2+0x2c8>) 8004ed6: f7fc fe13 bl 8001b00 <__aeabi_dsub> 8004eda: 9002 str r0, [sp, #8] 8004edc: 9103 str r1, [sp, #12] 8004ede: 42a5 cmp r5, r4 8004ee0: d018 beq.n 8004f14 <__ieee754_rem_pio2+0x74> 8004ee2: 4aa3 ldr r2, [pc, #652] @ (8005170 <__ieee754_rem_pio2+0x2d0>) 8004ee4: 4ba3 ldr r3, [pc, #652] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004ee6: f7fc fe0b bl 8001b00 <__aeabi_dsub> 8004eea: 0002 movs r2, r0 8004eec: 000b movs r3, r1 8004eee: 0004 movs r4, r0 8004ef0: 000d movs r5, r1 8004ef2: 9802 ldr r0, [sp, #8] 8004ef4: 9903 ldr r1, [sp, #12] 8004ef6: f7fc fe03 bl 8001b00 <__aeabi_dsub> 8004efa: 4a9d ldr r2, [pc, #628] @ (8005170 <__ieee754_rem_pio2+0x2d0>) 8004efc: 4b9d ldr r3, [pc, #628] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004efe: f7fc fdff bl 8001b00 <__aeabi_dsub> 8004f02: 2301 movs r3, #1 8004f04: 603c str r4, [r7, #0] 8004f06: 607d str r5, [r7, #4] 8004f08: 60b8 str r0, [r7, #8] 8004f0a: 60f9 str r1, [r7, #12] 8004f0c: 9302 str r3, [sp, #8] 8004f0e: 9802 ldr r0, [sp, #8] 8004f10: b015 add sp, #84 @ 0x54 8004f12: bdf0 pop {r4, r5, r6, r7, pc} 8004f14: 22d3 movs r2, #211 @ 0xd3 8004f16: 9802 ldr r0, [sp, #8] 8004f18: 9903 ldr r1, [sp, #12] 8004f1a: 4b96 ldr r3, [pc, #600] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004f1c: 0552 lsls r2, r2, #21 8004f1e: f7fc fdef bl 8001b00 <__aeabi_dsub> 8004f22: 4a95 ldr r2, [pc, #596] @ (8005178 <__ieee754_rem_pio2+0x2d8>) 8004f24: 4b95 ldr r3, [pc, #596] @ (800517c <__ieee754_rem_pio2+0x2dc>) 8004f26: 9002 str r0, [sp, #8] 8004f28: 9103 str r1, [sp, #12] 8004f2a: f7fc fde9 bl 8001b00 <__aeabi_dsub> 8004f2e: 0002 movs r2, r0 8004f30: 000b movs r3, r1 8004f32: 0004 movs r4, r0 8004f34: 000d movs r5, r1 8004f36: 9802 ldr r0, [sp, #8] 8004f38: 9903 ldr r1, [sp, #12] 8004f3a: f7fc fde1 bl 8001b00 <__aeabi_dsub> 8004f3e: 4a8e ldr r2, [pc, #568] @ (8005178 <__ieee754_rem_pio2+0x2d8>) 8004f40: 4b8e ldr r3, [pc, #568] @ (800517c <__ieee754_rem_pio2+0x2dc>) 8004f42: e7dc b.n 8004efe <__ieee754_rem_pio2+0x5e> 8004f44: 4b88 ldr r3, [pc, #544] @ (8005168 <__ieee754_rem_pio2+0x2c8>) 8004f46: f7fb faf5 bl 8000534 <__aeabi_dadd> 8004f4a: 9002 str r0, [sp, #8] 8004f4c: 9103 str r1, [sp, #12] 8004f4e: 42a5 cmp r5, r4 8004f50: d016 beq.n 8004f80 <__ieee754_rem_pio2+0xe0> 8004f52: 4a87 ldr r2, [pc, #540] @ (8005170 <__ieee754_rem_pio2+0x2d0>) 8004f54: 4b87 ldr r3, [pc, #540] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004f56: f7fb faed bl 8000534 <__aeabi_dadd> 8004f5a: 0002 movs r2, r0 8004f5c: 000b movs r3, r1 8004f5e: 0004 movs r4, r0 8004f60: 000d movs r5, r1 8004f62: 9802 ldr r0, [sp, #8] 8004f64: 9903 ldr r1, [sp, #12] 8004f66: f7fc fdcb bl 8001b00 <__aeabi_dsub> 8004f6a: 4a81 ldr r2, [pc, #516] @ (8005170 <__ieee754_rem_pio2+0x2d0>) 8004f6c: 4b81 ldr r3, [pc, #516] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004f6e: f7fb fae1 bl 8000534 <__aeabi_dadd> 8004f72: 2301 movs r3, #1 8004f74: 603c str r4, [r7, #0] 8004f76: 607d str r5, [r7, #4] 8004f78: 60b8 str r0, [r7, #8] 8004f7a: 60f9 str r1, [r7, #12] 8004f7c: 425b negs r3, r3 8004f7e: e7c5 b.n 8004f0c <__ieee754_rem_pio2+0x6c> 8004f80: 22d3 movs r2, #211 @ 0xd3 8004f82: 9802 ldr r0, [sp, #8] 8004f84: 9903 ldr r1, [sp, #12] 8004f86: 4b7b ldr r3, [pc, #492] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004f88: 0552 lsls r2, r2, #21 8004f8a: f7fb fad3 bl 8000534 <__aeabi_dadd> 8004f8e: 4a7a ldr r2, [pc, #488] @ (8005178 <__ieee754_rem_pio2+0x2d8>) 8004f90: 4b7a ldr r3, [pc, #488] @ (800517c <__ieee754_rem_pio2+0x2dc>) 8004f92: 9002 str r0, [sp, #8] 8004f94: 9103 str r1, [sp, #12] 8004f96: f7fb facd bl 8000534 <__aeabi_dadd> 8004f9a: 0002 movs r2, r0 8004f9c: 000b movs r3, r1 8004f9e: 0004 movs r4, r0 8004fa0: 000d movs r5, r1 8004fa2: 9802 ldr r0, [sp, #8] 8004fa4: 9903 ldr r1, [sp, #12] 8004fa6: f7fc fdab bl 8001b00 <__aeabi_dsub> 8004faa: 4a73 ldr r2, [pc, #460] @ (8005178 <__ieee754_rem_pio2+0x2d8>) 8004fac: 4b73 ldr r3, [pc, #460] @ (800517c <__ieee754_rem_pio2+0x2dc>) 8004fae: e7de b.n 8004f6e <__ieee754_rem_pio2+0xce> 8004fb0: 4b73 ldr r3, [pc, #460] @ (8005180 <__ieee754_rem_pio2+0x2e0>) 8004fb2: 429d cmp r5, r3 8004fb4: d900 bls.n 8004fb8 <__ieee754_rem_pio2+0x118> 8004fb6: e0c6 b.n 8005146 <__ieee754_rem_pio2+0x2a6> 8004fb8: f000 f94e bl 8005258 <fabs> 8004fbc: 4a71 ldr r2, [pc, #452] @ (8005184 <__ieee754_rem_pio2+0x2e4>) 8004fbe: 4b72 ldr r3, [pc, #456] @ (8005188 <__ieee754_rem_pio2+0x2e8>) 8004fc0: 9004 str r0, [sp, #16] 8004fc2: 9105 str r1, [sp, #20] 8004fc4: f7fc fab6 bl 8001534 <__aeabi_dmul> 8004fc8: 2200 movs r2, #0 8004fca: 4b70 ldr r3, [pc, #448] @ (800518c <__ieee754_rem_pio2+0x2ec>) 8004fcc: f7fb fab2 bl 8000534 <__aeabi_dadd> 8004fd0: f7fd f9a0 bl 8002314 <__aeabi_d2iz> 8004fd4: 9002 str r0, [sp, #8] 8004fd6: f7fd f9d9 bl 800238c <__aeabi_i2d> 8004fda: 4a64 ldr r2, [pc, #400] @ (800516c <__ieee754_rem_pio2+0x2cc>) 8004fdc: 4b62 ldr r3, [pc, #392] @ (8005168 <__ieee754_rem_pio2+0x2c8>) 8004fde: 9008 str r0, [sp, #32] 8004fe0: 9109 str r1, [sp, #36] @ 0x24 8004fe2: f7fc faa7 bl 8001534 <__aeabi_dmul> 8004fe6: 0002 movs r2, r0 8004fe8: 000b movs r3, r1 8004fea: 9804 ldr r0, [sp, #16] 8004fec: 9905 ldr r1, [sp, #20] 8004fee: f7fc fd87 bl 8001b00 <__aeabi_dsub> 8004ff2: 4b60 ldr r3, [pc, #384] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 8004ff4: 9004 str r0, [sp, #16] 8004ff6: 9105 str r1, [sp, #20] 8004ff8: 9808 ldr r0, [sp, #32] 8004ffa: 9909 ldr r1, [sp, #36] @ 0x24 8004ffc: 4a5c ldr r2, [pc, #368] @ (8005170 <__ieee754_rem_pio2+0x2d0>) 8004ffe: f7fc fa99 bl 8001534 <__aeabi_dmul> 8005002: 9b02 ldr r3, [sp, #8] 8005004: 9006 str r0, [sp, #24] 8005006: 9107 str r1, [sp, #28] 8005008: 2b1f cmp r3, #31 800500a: dc0d bgt.n 8005028 <__ieee754_rem_pio2+0x188> 800500c: 9a02 ldr r2, [sp, #8] 800500e: 4b60 ldr r3, [pc, #384] @ (8005190 <__ieee754_rem_pio2+0x2f0>) 8005010: 3a01 subs r2, #1 8005012: 0092 lsls r2, r2, #2 8005014: 58d3 ldr r3, [r2, r3] 8005016: 42ab cmp r3, r5 8005018: d006 beq.n 8005028 <__ieee754_rem_pio2+0x188> 800501a: 0002 movs r2, r0 800501c: 000b movs r3, r1 800501e: 9804 ldr r0, [sp, #16] 8005020: 9905 ldr r1, [sp, #20] 8005022: f7fc fd6d bl 8001b00 <__aeabi_dsub> 8005026: e00b b.n 8005040 <__ieee754_rem_pio2+0x1a0> 8005028: 9a06 ldr r2, [sp, #24] 800502a: 9b07 ldr r3, [sp, #28] 800502c: 9804 ldr r0, [sp, #16] 800502e: 9905 ldr r1, [sp, #20] 8005030: f7fc fd66 bl 8001b00 <__aeabi_dsub> 8005034: 004b lsls r3, r1, #1 8005036: 152e asrs r6, r5, #20 8005038: 0d5b lsrs r3, r3, #21 800503a: 1af3 subs r3, r6, r3 800503c: 2b10 cmp r3, #16 800503e: dc02 bgt.n 8005046 <__ieee754_rem_pio2+0x1a6> 8005040: 6038 str r0, [r7, #0] 8005042: 6079 str r1, [r7, #4] 8005044: e039 b.n 80050ba <__ieee754_rem_pio2+0x21a> 8005046: 22d3 movs r2, #211 @ 0xd3 8005048: 9808 ldr r0, [sp, #32] 800504a: 9909 ldr r1, [sp, #36] @ 0x24 800504c: 4b49 ldr r3, [pc, #292] @ (8005174 <__ieee754_rem_pio2+0x2d4>) 800504e: 0552 lsls r2, r2, #21 8005050: f7fc fa70 bl 8001534 <__aeabi_dmul> 8005054: 0004 movs r4, r0 8005056: 000d movs r5, r1 8005058: 0002 movs r2, r0 800505a: 000b movs r3, r1 800505c: 9804 ldr r0, [sp, #16] 800505e: 9905 ldr r1, [sp, #20] 8005060: f7fc fd4e bl 8001b00 <__aeabi_dsub> 8005064: 0002 movs r2, r0 8005066: 000b movs r3, r1 8005068: 900a str r0, [sp, #40] @ 0x28 800506a: 910b str r1, [sp, #44] @ 0x2c 800506c: 9804 ldr r0, [sp, #16] 800506e: 9905 ldr r1, [sp, #20] 8005070: f7fc fd46 bl 8001b00 <__aeabi_dsub> 8005074: 0022 movs r2, r4 8005076: 002b movs r3, r5 8005078: f7fc fd42 bl 8001b00 <__aeabi_dsub> 800507c: 0004 movs r4, r0 800507e: 000d movs r5, r1 8005080: 9808 ldr r0, [sp, #32] 8005082: 9909 ldr r1, [sp, #36] @ 0x24 8005084: 4a3c ldr r2, [pc, #240] @ (8005178 <__ieee754_rem_pio2+0x2d8>) 8005086: 4b3d ldr r3, [pc, #244] @ (800517c <__ieee754_rem_pio2+0x2dc>) 8005088: f7fc fa54 bl 8001534 <__aeabi_dmul> 800508c: 0022 movs r2, r4 800508e: 002b movs r3, r5 8005090: f7fc fd36 bl 8001b00 <__aeabi_dsub> 8005094: 000b movs r3, r1 8005096: 0002 movs r2, r0 8005098: 9006 str r0, [sp, #24] 800509a: 9107 str r1, [sp, #28] 800509c: 980a ldr r0, [sp, #40] @ 0x28 800509e: 990b ldr r1, [sp, #44] @ 0x2c 80050a0: f7fc fd2e bl 8001b00 <__aeabi_dsub> 80050a4: 004b lsls r3, r1, #1 80050a6: 0d5b lsrs r3, r3, #21 80050a8: 1af3 subs r3, r6, r3 80050aa: 2b31 cmp r3, #49 @ 0x31 80050ac: dc21 bgt.n 80050f2 <__ieee754_rem_pio2+0x252> 80050ae: 9b0a ldr r3, [sp, #40] @ 0x28 80050b0: 9c0b ldr r4, [sp, #44] @ 0x2c 80050b2: 6038 str r0, [r7, #0] 80050b4: 6079 str r1, [r7, #4] 80050b6: 9304 str r3, [sp, #16] 80050b8: 9405 str r4, [sp, #20] 80050ba: 683c ldr r4, [r7, #0] 80050bc: 687d ldr r5, [r7, #4] 80050be: 9804 ldr r0, [sp, #16] 80050c0: 9905 ldr r1, [sp, #20] 80050c2: 0022 movs r2, r4 80050c4: 002b movs r3, r5 80050c6: f7fc fd1b bl 8001b00 <__aeabi_dsub> 80050ca: 9a06 ldr r2, [sp, #24] 80050cc: 9b07 ldr r3, [sp, #28] 80050ce: f7fc fd17 bl 8001b00 <__aeabi_dsub> 80050d2: 9b0d ldr r3, [sp, #52] @ 0x34 80050d4: 60b8 str r0, [r7, #8] 80050d6: 60f9 str r1, [r7, #12] 80050d8: 2b00 cmp r3, #0 80050da: db00 blt.n 80050de <__ieee754_rem_pio2+0x23e> 80050dc: e717 b.n 8004f0e <__ieee754_rem_pio2+0x6e> 80050de: 2280 movs r2, #128 @ 0x80 80050e0: 0612 lsls r2, r2, #24 80050e2: 18ab adds r3, r5, r2 80050e4: 607b str r3, [r7, #4] 80050e6: 188b adds r3, r1, r2 80050e8: 603c str r4, [r7, #0] 80050ea: 60b8 str r0, [r7, #8] 80050ec: 60fb str r3, [r7, #12] 80050ee: 9b02 ldr r3, [sp, #8] 80050f0: e744 b.n 8004f7c <__ieee754_rem_pio2+0xdc> 80050f2: 22b8 movs r2, #184 @ 0xb8 80050f4: 9808 ldr r0, [sp, #32] 80050f6: 9909 ldr r1, [sp, #36] @ 0x24 80050f8: 4b20 ldr r3, [pc, #128] @ (800517c <__ieee754_rem_pio2+0x2dc>) 80050fa: 0592 lsls r2, r2, #22 80050fc: f7fc fa1a bl 8001534 <__aeabi_dmul> 8005100: 0004 movs r4, r0 8005102: 000d movs r5, r1 8005104: 0002 movs r2, r0 8005106: 000b movs r3, r1 8005108: 980a ldr r0, [sp, #40] @ 0x28 800510a: 990b ldr r1, [sp, #44] @ 0x2c 800510c: f7fc fcf8 bl 8001b00 <__aeabi_dsub> 8005110: 0002 movs r2, r0 8005112: 000b movs r3, r1 8005114: 9004 str r0, [sp, #16] 8005116: 9105 str r1, [sp, #20] 8005118: 980a ldr r0, [sp, #40] @ 0x28 800511a: 990b ldr r1, [sp, #44] @ 0x2c 800511c: f7fc fcf0 bl 8001b00 <__aeabi_dsub> 8005120: 0022 movs r2, r4 8005122: 002b movs r3, r5 8005124: f7fc fcec bl 8001b00 <__aeabi_dsub> 8005128: 0004 movs r4, r0 800512a: 000d movs r5, r1 800512c: 9808 ldr r0, [sp, #32] 800512e: 9909 ldr r1, [sp, #36] @ 0x24 8005130: 4a18 ldr r2, [pc, #96] @ (8005194 <__ieee754_rem_pio2+0x2f4>) 8005132: 4b19 ldr r3, [pc, #100] @ (8005198 <__ieee754_rem_pio2+0x2f8>) 8005134: f7fc f9fe bl 8001534 <__aeabi_dmul> 8005138: 0022 movs r2, r4 800513a: 002b movs r3, r5 800513c: f7fc fce0 bl 8001b00 <__aeabi_dsub> 8005140: 9006 str r0, [sp, #24] 8005142: 9107 str r1, [sp, #28] 8005144: e769 b.n 800501a <__ieee754_rem_pio2+0x17a> 8005146: 4b15 ldr r3, [pc, #84] @ (800519c <__ieee754_rem_pio2+0x2fc>) 8005148: 429d cmp r5, r3 800514a: d929 bls.n 80051a0 <__ieee754_rem_pio2+0x300> 800514c: 0002 movs r2, r0 800514e: 000b movs r3, r1 8005150: f7fc fcd6 bl 8001b00 <__aeabi_dsub> 8005154: 60b8 str r0, [r7, #8] 8005156: 60f9 str r1, [r7, #12] 8005158: 6038 str r0, [r7, #0] 800515a: 6079 str r1, [r7, #4] 800515c: e6af b.n 8004ebe <__ieee754_rem_pio2+0x1e> 800515e: 46c0 nop @ (mov r8, r8) 8005160: 3fe921fb .word 0x3fe921fb 8005164: 4002d97b .word 0x4002d97b 8005168: 3ff921fb .word 0x3ff921fb 800516c: 54400000 .word 0x54400000 8005170: 1a626331 .word 0x1a626331 8005174: 3dd0b461 .word 0x3dd0b461 8005178: 2e037073 .word 0x2e037073 800517c: 3ba3198a .word 0x3ba3198a 8005180: 413921fb .word 0x413921fb 8005184: 6dc9c883 .word 0x6dc9c883 8005188: 3fe45f30 .word 0x3fe45f30 800518c: 3fe00000 .word 0x3fe00000 8005190: 08005b70 .word 0x08005b70 8005194: 252049c1 .word 0x252049c1 8005198: 397b839a .word 0x397b839a 800519c: 7fefffff .word 0x7fefffff 80051a0: 4b2a ldr r3, [pc, #168] @ (800524c <__ieee754_rem_pio2+0x3ac>) 80051a2: 152e asrs r6, r5, #20 80051a4: 18f6 adds r6, r6, r3 80051a6: 0531 lsls r1, r6, #20 80051a8: 1a6b subs r3, r5, r1 80051aa: 0019 movs r1, r3 80051ac: 001d movs r5, r3 80051ae: 0004 movs r4, r0 80051b0: f7fd f8b0 bl 8002314 <__aeabi_d2iz> 80051b4: f7fd f8ea bl 800238c <__aeabi_i2d> 80051b8: 0002 movs r2, r0 80051ba: 000b movs r3, r1 80051bc: 0020 movs r0, r4 80051be: 0029 movs r1, r5 80051c0: 920e str r2, [sp, #56] @ 0x38 80051c2: 930f str r3, [sp, #60] @ 0x3c 80051c4: f7fc fc9c bl 8001b00 <__aeabi_dsub> 80051c8: 2200 movs r2, #0 80051ca: 4b21 ldr r3, [pc, #132] @ (8005250 <__ieee754_rem_pio2+0x3b0>) 80051cc: f7fc f9b2 bl 8001534 <__aeabi_dmul> 80051d0: 000d movs r5, r1 80051d2: 0004 movs r4, r0 80051d4: f7fd f89e bl 8002314 <__aeabi_d2iz> 80051d8: f7fd f8d8 bl 800238c <__aeabi_i2d> 80051dc: 0002 movs r2, r0 80051de: 000b movs r3, r1 80051e0: 0020 movs r0, r4 80051e2: 0029 movs r1, r5 80051e4: 9210 str r2, [sp, #64] @ 0x40 80051e6: 9311 str r3, [sp, #68] @ 0x44 80051e8: f7fc fc8a bl 8001b00 <__aeabi_dsub> 80051ec: 2200 movs r2, #0 80051ee: 4b18 ldr r3, [pc, #96] @ (8005250 <__ieee754_rem_pio2+0x3b0>) 80051f0: f7fc f9a0 bl 8001534 <__aeabi_dmul> 80051f4: 2503 movs r5, #3 80051f6: 9012 str r0, [sp, #72] @ 0x48 80051f8: 9113 str r1, [sp, #76] @ 0x4c 80051fa: ac0e add r4, sp, #56 @ 0x38 80051fc: 2200 movs r2, #0 80051fe: 6920 ldr r0, [r4, #16] 8005200: 6961 ldr r1, [r4, #20] 8005202: 2300 movs r3, #0 8005204: 9502 str r5, [sp, #8] 8005206: 3c08 subs r4, #8 8005208: 3d01 subs r5, #1 800520a: f7fb f901 bl 8000410 <__aeabi_dcmpeq> 800520e: 2800 cmp r0, #0 8005210: d1f4 bne.n 80051fc <__ieee754_rem_pio2+0x35c> 8005212: 4b10 ldr r3, [pc, #64] @ (8005254 <__ieee754_rem_pio2+0x3b4>) 8005214: 0032 movs r2, r6 8005216: 9301 str r3, [sp, #4] 8005218: 2302 movs r3, #2 800521a: 0039 movs r1, r7 800521c: 9300 str r3, [sp, #0] 800521e: a80e add r0, sp, #56 @ 0x38 8005220: 9b02 ldr r3, [sp, #8] 8005222: f000 f81d bl 8005260 <__kernel_rem_pio2> 8005226: 9b0d ldr r3, [sp, #52] @ 0x34 8005228: 9002 str r0, [sp, #8] 800522a: 2b00 cmp r3, #0 800522c: db00 blt.n 8005230 <__ieee754_rem_pio2+0x390> 800522e: e66e b.n 8004f0e <__ieee754_rem_pio2+0x6e> 8005230: 2080 movs r0, #128 @ 0x80 8005232: 6879 ldr r1, [r7, #4] 8005234: 683a ldr r2, [r7, #0] 8005236: 0600 lsls r0, r0, #24 8005238: 180b adds r3, r1, r0 800523a: 68f9 ldr r1, [r7, #12] 800523c: 603a str r2, [r7, #0] 800523e: 607b str r3, [r7, #4] 8005240: 68ba ldr r2, [r7, #8] 8005242: 180b adds r3, r1, r0 8005244: 60ba str r2, [r7, #8] 8005246: 60fb str r3, [r7, #12] 8005248: e751 b.n 80050ee <__ieee754_rem_pio2+0x24e> 800524a: 46c0 nop @ (mov r8, r8) 800524c: fffffbea .word 0xfffffbea 8005250: 41700000 .word 0x41700000 8005254: 08005bf0 .word 0x08005bf0 08005258 <fabs>: 8005258: 0049 lsls r1, r1, #1 800525a: 084b lsrs r3, r1, #1 800525c: 0019 movs r1, r3 800525e: 4770 bx lr 08005260 <__kernel_rem_pio2>: 8005260: b5f0 push {r4, r5, r6, r7, lr} 8005262: 4cc6 ldr r4, [pc, #792] @ (800557c <__kernel_rem_pio2+0x31c>) 8005264: 44a5 add sp, r4 8005266: 0014 movs r4, r2 8005268: 9aa4 ldr r2, [sp, #656] @ 0x290 800526a: 930e str r3, [sp, #56] @ 0x38 800526c: 4bc4 ldr r3, [pc, #784] @ (8005580 <__kernel_rem_pio2+0x320>) 800526e: 0092 lsls r2, r2, #2 8005270: 58d3 ldr r3, [r2, r3] 8005272: 900f str r0, [sp, #60] @ 0x3c 8005274: 9308 str r3, [sp, #32] 8005276: 9b0e ldr r3, [sp, #56] @ 0x38 8005278: 9105 str r1, [sp, #20] 800527a: 3b01 subs r3, #1 800527c: 930d str r3, [sp, #52] @ 0x34 800527e: 2300 movs r3, #0 8005280: 9300 str r3, [sp, #0] 8005282: 0023 movs r3, r4 8005284: 3314 adds r3, #20 8005286: db04 blt.n 8005292 <__kernel_rem_pio2+0x32> 8005288: 2118 movs r1, #24 800528a: 1ee0 subs r0, r4, #3 800528c: f7fa ffc4 bl 8000218 <__divsi3> 8005290: 9000 str r0, [sp, #0] 8005292: 9b00 ldr r3, [sp, #0] 8005294: ae26 add r6, sp, #152 @ 0x98 8005296: 1c5a adds r2, r3, #1 8005298: 2318 movs r3, #24 800529a: 425b negs r3, r3 800529c: 4353 muls r3, r2 800529e: 191b adds r3, r3, r4 80052a0: 9a0d ldr r2, [sp, #52] @ 0x34 80052a2: 9302 str r3, [sp, #8] 80052a4: 9b00 ldr r3, [sp, #0] 80052a6: 1a9d subs r5, r3, r2 80052a8: 002c movs r4, r5 80052aa: 9b08 ldr r3, [sp, #32] 80052ac: 189f adds r7, r3, r2 80052ae: 1b63 subs r3, r4, r5 80052b0: 429f cmp r7, r3 80052b2: da0f bge.n 80052d4 <__kernel_rem_pio2+0x74> 80052b4: 9d0e ldr r5, [sp, #56] @ 0x38 80052b6: af76 add r7, sp, #472 @ 0x1d8 80052b8: 9b0e ldr r3, [sp, #56] @ 0x38 80052ba: 9a08 ldr r2, [sp, #32] 80052bc: 1aeb subs r3, r5, r3 80052be: 429a cmp r2, r3 80052c0: db30 blt.n 8005324 <__kernel_rem_pio2+0xc4> 80052c2: 00eb lsls r3, r5, #3 80052c4: aa26 add r2, sp, #152 @ 0x98 80052c6: 2400 movs r4, #0 80052c8: 189e adds r6, r3, r2 80052ca: 2300 movs r3, #0 80052cc: 9306 str r3, [sp, #24] 80052ce: 9407 str r4, [sp, #28] 80052d0: 2400 movs r4, #0 80052d2: e01e b.n 8005312 <__kernel_rem_pio2+0xb2> 80052d4: 2c00 cmp r4, #0 80052d6: db07 blt.n 80052e8 <__kernel_rem_pio2+0x88> 80052d8: 9aa5 ldr r2, [sp, #660] @ 0x294 80052da: 00a3 lsls r3, r4, #2 80052dc: 58d0 ldr r0, [r2, r3] 80052de: f7fd f855 bl 800238c <__aeabi_i2d> 80052e2: c603 stmia r6!, {r0, r1} 80052e4: 3401 adds r4, #1 80052e6: e7e2 b.n 80052ae <__kernel_rem_pio2+0x4e> 80052e8: 2000 movs r0, #0 80052ea: 2100 movs r1, #0 80052ec: e7f9 b.n 80052e2 <__kernel_rem_pio2+0x82> 80052ee: 9b0f ldr r3, [sp, #60] @ 0x3c 80052f0: 00e1 lsls r1, r4, #3 80052f2: 1859 adds r1, r3, r1 80052f4: 6808 ldr r0, [r1, #0] 80052f6: 6849 ldr r1, [r1, #4] 80052f8: 6832 ldr r2, [r6, #0] 80052fa: 6873 ldr r3, [r6, #4] 80052fc: f7fc f91a bl 8001534 <__aeabi_dmul> 8005300: 0002 movs r2, r0 8005302: 000b movs r3, r1 8005304: 9806 ldr r0, [sp, #24] 8005306: 9907 ldr r1, [sp, #28] 8005308: f7fb f914 bl 8000534 <__aeabi_dadd> 800530c: 9006 str r0, [sp, #24] 800530e: 9107 str r1, [sp, #28] 8005310: 3401 adds r4, #1 8005312: 9b0d ldr r3, [sp, #52] @ 0x34 8005314: 3e08 subs r6, #8 8005316: 429c cmp r4, r3 8005318: dde9 ble.n 80052ee <__kernel_rem_pio2+0x8e> 800531a: 9b06 ldr r3, [sp, #24] 800531c: 9c07 ldr r4, [sp, #28] 800531e: 3501 adds r5, #1 8005320: c718 stmia r7!, {r3, r4} 8005322: e7c9 b.n 80052b8 <__kernel_rem_pio2+0x58> 8005324: 9b08 ldr r3, [sp, #32] 8005326: aa12 add r2, sp, #72 @ 0x48 8005328: 009b lsls r3, r3, #2 800532a: 189b adds r3, r3, r2 800532c: 9311 str r3, [sp, #68] @ 0x44 800532e: 9b00 ldr r3, [sp, #0] 8005330: 9aa5 ldr r2, [sp, #660] @ 0x294 8005332: 009b lsls r3, r3, #2 8005334: 18d3 adds r3, r2, r3 8005336: 9310 str r3, [sp, #64] @ 0x40 8005338: 9b08 ldr r3, [sp, #32] 800533a: 9300 str r3, [sp, #0] 800533c: 9b00 ldr r3, [sp, #0] 800533e: aa76 add r2, sp, #472 @ 0x1d8 8005340: 00db lsls r3, r3, #3 8005342: 18d3 adds r3, r2, r3 8005344: 681e ldr r6, [r3, #0] 8005346: 685f ldr r7, [r3, #4] 8005348: ab12 add r3, sp, #72 @ 0x48 800534a: 001d movs r5, r3 800534c: 9c00 ldr r4, [sp, #0] 800534e: 930a str r3, [sp, #40] @ 0x28 8005350: 2c00 cmp r4, #0 8005352: dc73 bgt.n 800543c <__kernel_rem_pio2+0x1dc> 8005354: 0030 movs r0, r6 8005356: 0039 movs r1, r7 8005358: 9a02 ldr r2, [sp, #8] 800535a: f000 fad5 bl 8005908 <scalbn> 800535e: 23ff movs r3, #255 @ 0xff 8005360: 2200 movs r2, #0 8005362: 059b lsls r3, r3, #22 8005364: 0004 movs r4, r0 8005366: 000d movs r5, r1 8005368: f7fc f8e4 bl 8001534 <__aeabi_dmul> 800536c: f000 fb38 bl 80059e0 <floor> 8005370: 2200 movs r2, #0 8005372: 4b84 ldr r3, [pc, #528] @ (8005584 <__kernel_rem_pio2+0x324>) 8005374: f7fc f8de bl 8001534 <__aeabi_dmul> 8005378: 0002 movs r2, r0 800537a: 000b movs r3, r1 800537c: 0020 movs r0, r4 800537e: 0029 movs r1, r5 8005380: f7fc fbbe bl 8001b00 <__aeabi_dsub> 8005384: 000d movs r5, r1 8005386: 0004 movs r4, r0 8005388: f7fc ffc4 bl 8002314 <__aeabi_d2iz> 800538c: 900c str r0, [sp, #48] @ 0x30 800538e: f7fc fffd bl 800238c <__aeabi_i2d> 8005392: 000b movs r3, r1 8005394: 0002 movs r2, r0 8005396: 0029 movs r1, r5 8005398: 0020 movs r0, r4 800539a: f7fc fbb1 bl 8001b00 <__aeabi_dsub> 800539e: 9b02 ldr r3, [sp, #8] 80053a0: 0006 movs r6, r0 80053a2: 000f movs r7, r1 80053a4: 2b00 cmp r3, #0 80053a6: dd6f ble.n 8005488 <__kernel_rem_pio2+0x228> 80053a8: 2018 movs r0, #24 80053aa: 9b00 ldr r3, [sp, #0] 80053ac: aa12 add r2, sp, #72 @ 0x48 80053ae: 3b01 subs r3, #1 80053b0: 009b lsls r3, r3, #2 80053b2: 589a ldr r2, [r3, r2] 80053b4: 9902 ldr r1, [sp, #8] 80053b6: 9c0c ldr r4, [sp, #48] @ 0x30 80053b8: 1a40 subs r0, r0, r1 80053ba: 0011 movs r1, r2 80053bc: 4101 asrs r1, r0 80053be: 1864 adds r4, r4, r1 80053c0: 4081 lsls r1, r0 80053c2: 1a52 subs r2, r2, r1 80053c4: a912 add r1, sp, #72 @ 0x48 80053c6: 505a str r2, [r3, r1] 80053c8: 2317 movs r3, #23 80053ca: 9902 ldr r1, [sp, #8] 80053cc: 940c str r4, [sp, #48] @ 0x30 80053ce: 1a5b subs r3, r3, r1 80053d0: 411a asrs r2, r3 80053d2: 9206 str r2, [sp, #24] 80053d4: 9b06 ldr r3, [sp, #24] 80053d6: 2b00 cmp r3, #0 80053d8: dd68 ble.n 80054ac <__kernel_rem_pio2+0x24c> 80053da: 2200 movs r2, #0 80053dc: 2580 movs r5, #128 @ 0x80 80053de: 0014 movs r4, r2 80053e0: 2101 movs r1, #1 80053e2: 9b0c ldr r3, [sp, #48] @ 0x30 80053e4: 4868 ldr r0, [pc, #416] @ (8005588 <__kernel_rem_pio2+0x328>) 80053e6: 3301 adds r3, #1 80053e8: 930c str r3, [sp, #48] @ 0x30 80053ea: 046d lsls r5, r5, #17 80053ec: 9b00 ldr r3, [sp, #0] 80053ee: 4293 cmp r3, r2 80053f0: dd00 ble.n 80053f4 <__kernel_rem_pio2+0x194> 80053f2: e098 b.n 8005526 <__kernel_rem_pio2+0x2c6> 80053f4: 9b02 ldr r3, [sp, #8] 80053f6: 2b00 cmp r3, #0 80053f8: dd05 ble.n 8005406 <__kernel_rem_pio2+0x1a6> 80053fa: 2b01 cmp r3, #1 80053fc: d100 bne.n 8005400 <__kernel_rem_pio2+0x1a0> 80053fe: e0a4 b.n 800554a <__kernel_rem_pio2+0x2ea> 8005400: 2b02 cmp r3, #2 8005402: d100 bne.n 8005406 <__kernel_rem_pio2+0x1a6> 8005404: e0ab b.n 800555e <__kernel_rem_pio2+0x2fe> 8005406: 9b06 ldr r3, [sp, #24] 8005408: 2b02 cmp r3, #2 800540a: d14f bne.n 80054ac <__kernel_rem_pio2+0x24c> 800540c: 0032 movs r2, r6 800540e: 003b movs r3, r7 8005410: 2000 movs r0, #0 8005412: 495e ldr r1, [pc, #376] @ (800558c <__kernel_rem_pio2+0x32c>) 8005414: f7fc fb74 bl 8001b00 <__aeabi_dsub> 8005418: 0006 movs r6, r0 800541a: 000f movs r7, r1 800541c: 2c00 cmp r4, #0 800541e: d045 beq.n 80054ac <__kernel_rem_pio2+0x24c> 8005420: 9a02 ldr r2, [sp, #8] 8005422: 2000 movs r0, #0 8005424: 4959 ldr r1, [pc, #356] @ (800558c <__kernel_rem_pio2+0x32c>) 8005426: f000 fa6f bl 8005908 <scalbn> 800542a: 0002 movs r2, r0 800542c: 000b movs r3, r1 800542e: 0030 movs r0, r6 8005430: 0039 movs r1, r7 8005432: f7fc fb65 bl 8001b00 <__aeabi_dsub> 8005436: 0006 movs r6, r0 8005438: 000f movs r7, r1 800543a: e037 b.n 80054ac <__kernel_rem_pio2+0x24c> 800543c: 2200 movs r2, #0 800543e: 4b54 ldr r3, [pc, #336] @ (8005590 <__kernel_rem_pio2+0x330>) 8005440: 0030 movs r0, r6 8005442: 0039 movs r1, r7 8005444: f7fc f876 bl 8001534 <__aeabi_dmul> 8005448: f7fc ff64 bl 8002314 <__aeabi_d2iz> 800544c: f7fc ff9e bl 800238c <__aeabi_i2d> 8005450: 2200 movs r2, #0 8005452: 4b50 ldr r3, [pc, #320] @ (8005594 <__kernel_rem_pio2+0x334>) 8005454: 9006 str r0, [sp, #24] 8005456: 9107 str r1, [sp, #28] 8005458: f7fc f86c bl 8001534 <__aeabi_dmul> 800545c: 0002 movs r2, r0 800545e: 000b movs r3, r1 8005460: 0030 movs r0, r6 8005462: 0039 movs r1, r7 8005464: f7fc fb4c bl 8001b00 <__aeabi_dsub> 8005468: f7fc ff54 bl 8002314 <__aeabi_d2iz> 800546c: 3c01 subs r4, #1 800546e: aa76 add r2, sp, #472 @ 0x1d8 8005470: 00e3 lsls r3, r4, #3 8005472: 18d3 adds r3, r2, r3 8005474: c501 stmia r5!, {r0} 8005476: 681a ldr r2, [r3, #0] 8005478: 685b ldr r3, [r3, #4] 800547a: 9806 ldr r0, [sp, #24] 800547c: 9907 ldr r1, [sp, #28] 800547e: f7fb f859 bl 8000534 <__aeabi_dadd> 8005482: 0006 movs r6, r0 8005484: 000f movs r7, r1 8005486: e763 b.n 8005350 <__kernel_rem_pio2+0xf0> 8005488: 9b02 ldr r3, [sp, #8] 800548a: 2b00 cmp r3, #0 800548c: d107 bne.n 800549e <__kernel_rem_pio2+0x23e> 800548e: 9b00 ldr r3, [sp, #0] 8005490: aa12 add r2, sp, #72 @ 0x48 8005492: 3b01 subs r3, #1 8005494: 009b lsls r3, r3, #2 8005496: 589b ldr r3, [r3, r2] 8005498: 15db asrs r3, r3, #23 800549a: 9306 str r3, [sp, #24] 800549c: e79a b.n 80053d4 <__kernel_rem_pio2+0x174> 800549e: 2200 movs r2, #0 80054a0: 4b3d ldr r3, [pc, #244] @ (8005598 <__kernel_rem_pio2+0x338>) 80054a2: f7fa ffd9 bl 8000458 <__aeabi_dcmpge> 80054a6: 2800 cmp r0, #0 80054a8: d13a bne.n 8005520 <__kernel_rem_pio2+0x2c0> 80054aa: 9006 str r0, [sp, #24] 80054ac: 2200 movs r2, #0 80054ae: 2300 movs r3, #0 80054b0: 0030 movs r0, r6 80054b2: 0039 movs r1, r7 80054b4: f7fa ffac bl 8000410 <__aeabi_dcmpeq> 80054b8: 2800 cmp r0, #0 80054ba: d100 bne.n 80054be <__kernel_rem_pio2+0x25e> 80054bc: e0b5 b.n 800562a <__kernel_rem_pio2+0x3ca> 80054be: 2200 movs r2, #0 80054c0: 9b00 ldr r3, [sp, #0] 80054c2: 3b01 subs r3, #1 80054c4: 9908 ldr r1, [sp, #32] 80054c6: 428b cmp r3, r1 80054c8: da51 bge.n 800556e <__kernel_rem_pio2+0x30e> 80054ca: 2a00 cmp r2, #0 80054cc: d100 bne.n 80054d0 <__kernel_rem_pio2+0x270> 80054ce: e096 b.n 80055fe <__kernel_rem_pio2+0x39e> 80054d0: 9b00 ldr r3, [sp, #0] 80054d2: aa12 add r2, sp, #72 @ 0x48 80054d4: 3b01 subs r3, #1 80054d6: 9300 str r3, [sp, #0] 80054d8: 9b02 ldr r3, [sp, #8] 80054da: 3b18 subs r3, #24 80054dc: 9302 str r3, [sp, #8] 80054de: 9b00 ldr r3, [sp, #0] 80054e0: 009b lsls r3, r3, #2 80054e2: 589b ldr r3, [r3, r2] 80054e4: 2b00 cmp r3, #0 80054e6: d0f3 beq.n 80054d0 <__kernel_rem_pio2+0x270> 80054e8: 2000 movs r0, #0 80054ea: 9a02 ldr r2, [sp, #8] 80054ec: 4927 ldr r1, [pc, #156] @ (800558c <__kernel_rem_pio2+0x32c>) 80054ee: f000 fa0b bl 8005908 <scalbn> 80054f2: 0004 movs r4, r0 80054f4: 000d movs r5, r1 80054f6: 9e00 ldr r6, [sp, #0] 80054f8: 2e00 cmp r6, #0 80054fa: db00 blt.n 80054fe <__kernel_rem_pio2+0x29e> 80054fc: e0d2 b.n 80056a4 <__kernel_rem_pio2+0x444> 80054fe: 4b27 ldr r3, [pc, #156] @ (800559c <__kernel_rem_pio2+0x33c>) 8005500: 9c00 ldr r4, [sp, #0] 8005502: 930a str r3, [sp, #40] @ 0x28 8005504: 2c00 cmp r4, #0 8005506: da00 bge.n 800550a <__kernel_rem_pio2+0x2aa> 8005508: e103 b.n 8005712 <__kernel_rem_pio2+0x4b2> 800550a: 00e3 lsls r3, r4, #3 800550c: aa76 add r2, sp, #472 @ 0x1d8 800550e: 189f adds r7, r3, r2 8005510: 2300 movs r3, #0 8005512: 2200 movs r2, #0 8005514: 9202 str r2, [sp, #8] 8005516: 9303 str r3, [sp, #12] 8005518: 9b00 ldr r3, [sp, #0] 800551a: 2500 movs r5, #0 800551c: 1b1e subs r6, r3, r4 800551e: e0ea b.n 80056f6 <__kernel_rem_pio2+0x496> 8005520: 2302 movs r3, #2 8005522: 9306 str r3, [sp, #24] 8005524: e759 b.n 80053da <__kernel_rem_pio2+0x17a> 8005526: 9b0a ldr r3, [sp, #40] @ 0x28 8005528: 681b ldr r3, [r3, #0] 800552a: 2c00 cmp r4, #0 800552c: d10b bne.n 8005546 <__kernel_rem_pio2+0x2e6> 800552e: 2b00 cmp r3, #0 8005530: d003 beq.n 800553a <__kernel_rem_pio2+0x2da> 8005532: 1aeb subs r3, r5, r3 8005534: 9c0a ldr r4, [sp, #40] @ 0x28 8005536: 6023 str r3, [r4, #0] 8005538: 000b movs r3, r1 800553a: 9c0a ldr r4, [sp, #40] @ 0x28 800553c: 3201 adds r2, #1 800553e: 3404 adds r4, #4 8005540: 940a str r4, [sp, #40] @ 0x28 8005542: 001c movs r4, r3 8005544: e752 b.n 80053ec <__kernel_rem_pio2+0x18c> 8005546: 1ac3 subs r3, r0, r3 8005548: e7f4 b.n 8005534 <__kernel_rem_pio2+0x2d4> 800554a: 9b00 ldr r3, [sp, #0] 800554c: aa12 add r2, sp, #72 @ 0x48 800554e: 3b01 subs r3, #1 8005550: 009b lsls r3, r3, #2 8005552: 589a ldr r2, [r3, r2] 8005554: 0252 lsls r2, r2, #9 8005556: 0a52 lsrs r2, r2, #9 8005558: a912 add r1, sp, #72 @ 0x48 800555a: 505a str r2, [r3, r1] 800555c: e753 b.n 8005406 <__kernel_rem_pio2+0x1a6> 800555e: 9b00 ldr r3, [sp, #0] 8005560: aa12 add r2, sp, #72 @ 0x48 8005562: 3b01 subs r3, #1 8005564: 009b lsls r3, r3, #2 8005566: 589a ldr r2, [r3, r2] 8005568: 0292 lsls r2, r2, #10 800556a: 0a92 lsrs r2, r2, #10 800556c: e7f4 b.n 8005558 <__kernel_rem_pio2+0x2f8> 800556e: 0099 lsls r1, r3, #2 8005570: a812 add r0, sp, #72 @ 0x48 8005572: 5809 ldr r1, [r1, r0] 8005574: 3b01 subs r3, #1 8005576: 430a orrs r2, r1 8005578: e7a4 b.n 80054c4 <__kernel_rem_pio2+0x264> 800557a: 46c0 nop @ (mov r8, r8) 800557c: fffffd84 .word 0xfffffd84 8005580: 08005d38 .word 0x08005d38 8005584: 40200000 .word 0x40200000 8005588: 00ffffff .word 0x00ffffff 800558c: 3ff00000 .word 0x3ff00000 8005590: 3e700000 .word 0x3e700000 8005594: 41700000 .word 0x41700000 8005598: 3fe00000 .word 0x3fe00000 800559c: 08005cf8 .word 0x08005cf8 80055a0: 3301 adds r3, #1 80055a2: 9911 ldr r1, [sp, #68] @ 0x44 80055a4: 009a lsls r2, r3, #2 80055a6: 4252 negs r2, r2 80055a8: 588a ldr r2, [r1, r2] 80055aa: 2a00 cmp r2, #0 80055ac: d0f8 beq.n 80055a0 <__kernel_rem_pio2+0x340> 80055ae: 9a00 ldr r2, [sp, #0] 80055b0: 990e ldr r1, [sp, #56] @ 0x38 80055b2: 1c55 adds r5, r2, #1 80055b4: 1852 adds r2, r2, r1 80055b6: 00d2 lsls r2, r2, #3 80055b8: a926 add r1, sp, #152 @ 0x98 80055ba: 188c adds r4, r1, r2 80055bc: 9a00 ldr r2, [sp, #0] 80055be: 18d3 adds r3, r2, r3 80055c0: 9306 str r3, [sp, #24] 80055c2: 9b06 ldr r3, [sp, #24] 80055c4: 42ab cmp r3, r5 80055c6: da00 bge.n 80055ca <__kernel_rem_pio2+0x36a> 80055c8: e6b7 b.n 800533a <__kernel_rem_pio2+0xda> 80055ca: 9a10 ldr r2, [sp, #64] @ 0x40 80055cc: 00ab lsls r3, r5, #2 80055ce: 58d0 ldr r0, [r2, r3] 80055d0: f7fc fedc bl 800238c <__aeabi_i2d> 80055d4: 2200 movs r2, #0 80055d6: 2300 movs r3, #0 80055d8: 0027 movs r7, r4 80055da: 2600 movs r6, #0 80055dc: 6020 str r0, [r4, #0] 80055de: 6061 str r1, [r4, #4] 80055e0: 9200 str r2, [sp, #0] 80055e2: 9301 str r3, [sp, #4] 80055e4: 9b0d ldr r3, [sp, #52] @ 0x34 80055e6: 429e cmp r6, r3 80055e8: dd0b ble.n 8005602 <__kernel_rem_pio2+0x3a2> 80055ea: 00eb lsls r3, r5, #3 80055ec: aa76 add r2, sp, #472 @ 0x1d8 80055ee: 18d3 adds r3, r2, r3 80055f0: 3501 adds r5, #1 80055f2: 9900 ldr r1, [sp, #0] 80055f4: 9a01 ldr r2, [sp, #4] 80055f6: 3408 adds r4, #8 80055f8: 6019 str r1, [r3, #0] 80055fa: 605a str r2, [r3, #4] 80055fc: e7e1 b.n 80055c2 <__kernel_rem_pio2+0x362> 80055fe: 2301 movs r3, #1 8005600: e7cf b.n 80055a2 <__kernel_rem_pio2+0x342> 8005602: 9b0f ldr r3, [sp, #60] @ 0x3c 8005604: 00f1 lsls r1, r6, #3 8005606: 1859 adds r1, r3, r1 8005608: 6808 ldr r0, [r1, #0] 800560a: 6849 ldr r1, [r1, #4] 800560c: 683a ldr r2, [r7, #0] 800560e: 687b ldr r3, [r7, #4] 8005610: f7fb ff90 bl 8001534 <__aeabi_dmul> 8005614: 0002 movs r2, r0 8005616: 000b movs r3, r1 8005618: 9800 ldr r0, [sp, #0] 800561a: 9901 ldr r1, [sp, #4] 800561c: f7fa ff8a bl 8000534 <__aeabi_dadd> 8005620: 3601 adds r6, #1 8005622: 9000 str r0, [sp, #0] 8005624: 9101 str r1, [sp, #4] 8005626: 3f08 subs r7, #8 8005628: e7dc b.n 80055e4 <__kernel_rem_pio2+0x384> 800562a: 9b02 ldr r3, [sp, #8] 800562c: 0030 movs r0, r6 800562e: 425a negs r2, r3 8005630: 0039 movs r1, r7 8005632: f000 f969 bl 8005908 <scalbn> 8005636: 2200 movs r2, #0 8005638: 4bb1 ldr r3, [pc, #708] @ (8005900 <__kernel_rem_pio2+0x6a0>) 800563a: 0006 movs r6, r0 800563c: 000f movs r7, r1 800563e: f7fa ff0b bl 8000458 <__aeabi_dcmpge> 8005642: 2800 cmp r0, #0 8005644: d025 beq.n 8005692 <__kernel_rem_pio2+0x432> 8005646: 2200 movs r2, #0 8005648: 4bae ldr r3, [pc, #696] @ (8005904 <__kernel_rem_pio2+0x6a4>) 800564a: 0030 movs r0, r6 800564c: 0039 movs r1, r7 800564e: f7fb ff71 bl 8001534 <__aeabi_dmul> 8005652: f7fc fe5f bl 8002314 <__aeabi_d2iz> 8005656: 9b00 ldr r3, [sp, #0] 8005658: 0004 movs r4, r0 800565a: 009d lsls r5, r3, #2 800565c: f7fc fe96 bl 800238c <__aeabi_i2d> 8005660: 2200 movs r2, #0 8005662: 4ba7 ldr r3, [pc, #668] @ (8005900 <__kernel_rem_pio2+0x6a0>) 8005664: f7fb ff66 bl 8001534 <__aeabi_dmul> 8005668: 0002 movs r2, r0 800566a: 000b movs r3, r1 800566c: 0030 movs r0, r6 800566e: 0039 movs r1, r7 8005670: f7fc fa46 bl 8001b00 <__aeabi_dsub> 8005674: f7fc fe4e bl 8002314 <__aeabi_d2iz> 8005678: ab12 add r3, sp, #72 @ 0x48 800567a: 5158 str r0, [r3, r5] 800567c: 9b00 ldr r3, [sp, #0] 800567e: aa12 add r2, sp, #72 @ 0x48 8005680: 3301 adds r3, #1 8005682: 9300 str r3, [sp, #0] 8005684: 9b02 ldr r3, [sp, #8] 8005686: 3318 adds r3, #24 8005688: 9302 str r3, [sp, #8] 800568a: 9b00 ldr r3, [sp, #0] 800568c: 009b lsls r3, r3, #2 800568e: 509c str r4, [r3, r2] 8005690: e72a b.n 80054e8 <__kernel_rem_pio2+0x288> 8005692: 9b00 ldr r3, [sp, #0] 8005694: 0030 movs r0, r6 8005696: 0039 movs r1, r7 8005698: 009c lsls r4, r3, #2 800569a: f7fc fe3b bl 8002314 <__aeabi_d2iz> 800569e: ab12 add r3, sp, #72 @ 0x48 80056a0: 5118 str r0, [r3, r4] 80056a2: e721 b.n 80054e8 <__kernel_rem_pio2+0x288> 80056a4: 00f3 lsls r3, r6, #3 80056a6: aa76 add r2, sp, #472 @ 0x1d8 80056a8: 18d7 adds r7, r2, r3 80056aa: 00b3 lsls r3, r6, #2 80056ac: aa12 add r2, sp, #72 @ 0x48 80056ae: 5898 ldr r0, [r3, r2] 80056b0: f7fc fe6c bl 800238c <__aeabi_i2d> 80056b4: 0022 movs r2, r4 80056b6: 002b movs r3, r5 80056b8: f7fb ff3c bl 8001534 <__aeabi_dmul> 80056bc: 2200 movs r2, #0 80056be: 6038 str r0, [r7, #0] 80056c0: 6079 str r1, [r7, #4] 80056c2: 4b90 ldr r3, [pc, #576] @ (8005904 <__kernel_rem_pio2+0x6a4>) 80056c4: 0020 movs r0, r4 80056c6: 0029 movs r1, r5 80056c8: f7fb ff34 bl 8001534 <__aeabi_dmul> 80056cc: 3e01 subs r6, #1 80056ce: 0004 movs r4, r0 80056d0: 000d movs r5, r1 80056d2: e711 b.n 80054f8 <__kernel_rem_pio2+0x298> 80056d4: 9b0a ldr r3, [sp, #40] @ 0x28 80056d6: 00e9 lsls r1, r5, #3 80056d8: 18c9 adds r1, r1, r3 80056da: 6808 ldr r0, [r1, #0] 80056dc: 6849 ldr r1, [r1, #4] 80056de: cf0c ldmia r7!, {r2, r3} 80056e0: f7fb ff28 bl 8001534 <__aeabi_dmul> 80056e4: 0002 movs r2, r0 80056e6: 000b movs r3, r1 80056e8: 9802 ldr r0, [sp, #8] 80056ea: 9903 ldr r1, [sp, #12] 80056ec: f7fa ff22 bl 8000534 <__aeabi_dadd> 80056f0: 9002 str r0, [sp, #8] 80056f2: 9103 str r1, [sp, #12] 80056f4: 3501 adds r5, #1 80056f6: 9b08 ldr r3, [sp, #32] 80056f8: 429d cmp r5, r3 80056fa: dc01 bgt.n 8005700 <__kernel_rem_pio2+0x4a0> 80056fc: 42b5 cmp r5, r6 80056fe: dde9 ble.n 80056d4 <__kernel_rem_pio2+0x474> 8005700: 00f6 lsls r6, r6, #3 8005702: ab4e add r3, sp, #312 @ 0x138 8005704: 199b adds r3, r3, r6 8005706: 9902 ldr r1, [sp, #8] 8005708: 9a03 ldr r2, [sp, #12] 800570a: 3c01 subs r4, #1 800570c: 6019 str r1, [r3, #0] 800570e: 605a str r2, [r3, #4] 8005710: e6f8 b.n 8005504 <__kernel_rem_pio2+0x2a4> 8005712: 9ba4 ldr r3, [sp, #656] @ 0x290 8005714: 2b02 cmp r3, #2 8005716: dc0b bgt.n 8005730 <__kernel_rem_pio2+0x4d0> 8005718: 2b00 cmp r3, #0 800571a: dd00 ble.n 800571e <__kernel_rem_pio2+0x4be> 800571c: e084 b.n 8005828 <__kernel_rem_pio2+0x5c8> 800571e: d052 beq.n 80057c6 <__kernel_rem_pio2+0x566> 8005720: 2007 movs r0, #7 8005722: 9b0c ldr r3, [sp, #48] @ 0x30 8005724: 4003 ands r3, r0 8005726: 0018 movs r0, r3 8005728: 239f movs r3, #159 @ 0x9f 800572a: 009b lsls r3, r3, #2 800572c: 449d add sp, r3 800572e: bdf0 pop {r4, r5, r6, r7, pc} 8005730: 9ba4 ldr r3, [sp, #656] @ 0x290 8005732: 2b03 cmp r3, #3 8005734: d1f4 bne.n 8005720 <__kernel_rem_pio2+0x4c0> 8005736: 9b00 ldr r3, [sp, #0] 8005738: aa4e add r2, sp, #312 @ 0x138 800573a: 00db lsls r3, r3, #3 800573c: 18d4 adds r4, r2, r3 800573e: 0025 movs r5, r4 8005740: 9b00 ldr r3, [sp, #0] 8005742: 9302 str r3, [sp, #8] 8005744: 9b02 ldr r3, [sp, #8] 8005746: 3d08 subs r5, #8 8005748: 2b00 cmp r3, #0 800574a: dd00 ble.n 800574e <__kernel_rem_pio2+0x4ee> 800574c: e07a b.n 8005844 <__kernel_rem_pio2+0x5e4> 800574e: 9d00 ldr r5, [sp, #0] 8005750: 3c08 subs r4, #8 8005752: 2d01 cmp r5, #1 8005754: dd00 ble.n 8005758 <__kernel_rem_pio2+0x4f8> 8005756: e095 b.n 8005884 <__kernel_rem_pio2+0x624> 8005758: 2000 movs r0, #0 800575a: 2100 movs r1, #0 800575c: 9b00 ldr r3, [sp, #0] 800575e: 2b01 cmp r3, #1 8005760: dd00 ble.n 8005764 <__kernel_rem_pio2+0x504> 8005762: e0ad b.n 80058c0 <__kernel_rem_pio2+0x660> 8005764: 9b50 ldr r3, [sp, #320] @ 0x140 8005766: 9c51 ldr r4, [sp, #324] @ 0x144 8005768: 9d4e ldr r5, [sp, #312] @ 0x138 800576a: 9e4f ldr r6, [sp, #316] @ 0x13c 800576c: 9300 str r3, [sp, #0] 800576e: 9401 str r4, [sp, #4] 8005770: 9b06 ldr r3, [sp, #24] 8005772: 2b00 cmp r3, #0 8005774: d000 beq.n 8005778 <__kernel_rem_pio2+0x518> 8005776: e0af b.n 80058d8 <__kernel_rem_pio2+0x678> 8005778: 9b05 ldr r3, [sp, #20] 800577a: 601d str r5, [r3, #0] 800577c: 605e str r6, [r3, #4] 800577e: 9c00 ldr r4, [sp, #0] 8005780: 9d01 ldr r5, [sp, #4] 8005782: 6118 str r0, [r3, #16] 8005784: 6159 str r1, [r3, #20] 8005786: 609c str r4, [r3, #8] 8005788: 60dd str r5, [r3, #12] 800578a: e7c9 b.n 8005720 <__kernel_rem_pio2+0x4c0> 800578c: 9b00 ldr r3, [sp, #0] 800578e: aa4e add r2, sp, #312 @ 0x138 8005790: 00db lsls r3, r3, #3 8005792: 18d3 adds r3, r2, r3 8005794: 0020 movs r0, r4 8005796: 681a ldr r2, [r3, #0] 8005798: 685b ldr r3, [r3, #4] 800579a: 0029 movs r1, r5 800579c: f7fa feca bl 8000534 <__aeabi_dadd> 80057a0: 0004 movs r4, r0 80057a2: 000d movs r5, r1 80057a4: 9b00 ldr r3, [sp, #0] 80057a6: 3b01 subs r3, #1 80057a8: 9300 str r3, [sp, #0] 80057aa: 9b00 ldr r3, [sp, #0] 80057ac: 2b00 cmp r3, #0 80057ae: daed bge.n 800578c <__kernel_rem_pio2+0x52c> 80057b0: 9b06 ldr r3, [sp, #24] 80057b2: 2b00 cmp r3, #0 80057b4: d003 beq.n 80057be <__kernel_rem_pio2+0x55e> 80057b6: 2180 movs r1, #128 @ 0x80 80057b8: 0609 lsls r1, r1, #24 80057ba: 186b adds r3, r5, r1 80057bc: 001d movs r5, r3 80057be: 9b05 ldr r3, [sp, #20] 80057c0: 601c str r4, [r3, #0] 80057c2: 605d str r5, [r3, #4] 80057c4: e7ac b.n 8005720 <__kernel_rem_pio2+0x4c0> 80057c6: 2400 movs r4, #0 80057c8: 2500 movs r5, #0 80057ca: e7ee b.n 80057aa <__kernel_rem_pio2+0x54a> 80057cc: 00e3 lsls r3, r4, #3 80057ce: aa4e add r2, sp, #312 @ 0x138 80057d0: 18d3 adds r3, r2, r3 80057d2: 681a ldr r2, [r3, #0] 80057d4: 685b ldr r3, [r3, #4] 80057d6: f7fa fead bl 8000534 <__aeabi_dadd> 80057da: 3c01 subs r4, #1 80057dc: 2c00 cmp r4, #0 80057de: daf5 bge.n 80057cc <__kernel_rem_pio2+0x56c> 80057e0: 9c06 ldr r4, [sp, #24] 80057e2: 0002 movs r2, r0 80057e4: 000b movs r3, r1 80057e6: 2c00 cmp r4, #0 80057e8: d002 beq.n 80057f0 <__kernel_rem_pio2+0x590> 80057ea: 2480 movs r4, #128 @ 0x80 80057ec: 0624 lsls r4, r4, #24 80057ee: 190b adds r3, r1, r4 80057f0: 9c05 ldr r4, [sp, #20] 80057f2: 2501 movs r5, #1 80057f4: 6022 str r2, [r4, #0] 80057f6: 6063 str r3, [r4, #4] 80057f8: 0002 movs r2, r0 80057fa: 000b movs r3, r1 80057fc: 984e ldr r0, [sp, #312] @ 0x138 80057fe: 994f ldr r1, [sp, #316] @ 0x13c 8005800: f7fc f97e bl 8001b00 <__aeabi_dsub> 8005804: 0006 movs r6, r0 8005806: 000f movs r7, r1 8005808: ac4e add r4, sp, #312 @ 0x138 800580a: 9b00 ldr r3, [sp, #0] 800580c: 3408 adds r4, #8 800580e: 42ab cmp r3, r5 8005810: da0e bge.n 8005830 <__kernel_rem_pio2+0x5d0> 8005812: 9b06 ldr r3, [sp, #24] 8005814: 2b00 cmp r3, #0 8005816: d003 beq.n 8005820 <__kernel_rem_pio2+0x5c0> 8005818: 2180 movs r1, #128 @ 0x80 800581a: 0609 lsls r1, r1, #24 800581c: 187b adds r3, r7, r1 800581e: 001f movs r7, r3 8005820: 9b05 ldr r3, [sp, #20] 8005822: 609e str r6, [r3, #8] 8005824: 60df str r7, [r3, #12] 8005826: e77b b.n 8005720 <__kernel_rem_pio2+0x4c0> 8005828: 2000 movs r0, #0 800582a: 2100 movs r1, #0 800582c: 9c00 ldr r4, [sp, #0] 800582e: e7d5 b.n 80057dc <__kernel_rem_pio2+0x57c> 8005830: 0030 movs r0, r6 8005832: 6822 ldr r2, [r4, #0] 8005834: 6863 ldr r3, [r4, #4] 8005836: 0039 movs r1, r7 8005838: f7fa fe7c bl 8000534 <__aeabi_dadd> 800583c: 3501 adds r5, #1 800583e: 0006 movs r6, r0 8005840: 000f movs r7, r1 8005842: e7e2 b.n 800580a <__kernel_rem_pio2+0x5aa> 8005844: 9b02 ldr r3, [sp, #8] 8005846: 3b01 subs r3, #1 8005848: 9302 str r3, [sp, #8] 800584a: 682a ldr r2, [r5, #0] 800584c: 686b ldr r3, [r5, #4] 800584e: 9208 str r2, [sp, #32] 8005850: 9309 str r3, [sp, #36] @ 0x24 8005852: 9808 ldr r0, [sp, #32] 8005854: 9909 ldr r1, [sp, #36] @ 0x24 8005856: 68aa ldr r2, [r5, #8] 8005858: 68eb ldr r3, [r5, #12] 800585a: 920a str r2, [sp, #40] @ 0x28 800585c: 930b str r3, [sp, #44] @ 0x2c 800585e: f7fa fe69 bl 8000534 <__aeabi_dadd> 8005862: 0002 movs r2, r0 8005864: 000b movs r3, r1 8005866: 0006 movs r6, r0 8005868: 000f movs r7, r1 800586a: 9808 ldr r0, [sp, #32] 800586c: 9909 ldr r1, [sp, #36] @ 0x24 800586e: f7fc f947 bl 8001b00 <__aeabi_dsub> 8005872: 9a0a ldr r2, [sp, #40] @ 0x28 8005874: 9b0b ldr r3, [sp, #44] @ 0x2c 8005876: f7fa fe5d bl 8000534 <__aeabi_dadd> 800587a: 602e str r6, [r5, #0] 800587c: 606f str r7, [r5, #4] 800587e: 60a8 str r0, [r5, #8] 8005880: 60e9 str r1, [r5, #12] 8005882: e75f b.n 8005744 <__kernel_rem_pio2+0x4e4> 8005884: 6822 ldr r2, [r4, #0] 8005886: 6863 ldr r3, [r4, #4] 8005888: 9202 str r2, [sp, #8] 800588a: 9303 str r3, [sp, #12] 800588c: 9802 ldr r0, [sp, #8] 800588e: 9903 ldr r1, [sp, #12] 8005890: 68a2 ldr r2, [r4, #8] 8005892: 68e3 ldr r3, [r4, #12] 8005894: 9208 str r2, [sp, #32] 8005896: 9309 str r3, [sp, #36] @ 0x24 8005898: f7fa fe4c bl 8000534 <__aeabi_dadd> 800589c: 0002 movs r2, r0 800589e: 000b movs r3, r1 80058a0: 0006 movs r6, r0 80058a2: 000f movs r7, r1 80058a4: 9802 ldr r0, [sp, #8] 80058a6: 9903 ldr r1, [sp, #12] 80058a8: f7fc f92a bl 8001b00 <__aeabi_dsub> 80058ac: 9a08 ldr r2, [sp, #32] 80058ae: 9b09 ldr r3, [sp, #36] @ 0x24 80058b0: f7fa fe40 bl 8000534 <__aeabi_dadd> 80058b4: 3d01 subs r5, #1 80058b6: 60a0 str r0, [r4, #8] 80058b8: 60e1 str r1, [r4, #12] 80058ba: 6026 str r6, [r4, #0] 80058bc: 6067 str r7, [r4, #4] 80058be: e747 b.n 8005750 <__kernel_rem_pio2+0x4f0> 80058c0: 9b00 ldr r3, [sp, #0] 80058c2: aa4e add r2, sp, #312 @ 0x138 80058c4: 00db lsls r3, r3, #3 80058c6: 18d3 adds r3, r2, r3 80058c8: 681a ldr r2, [r3, #0] 80058ca: 685b ldr r3, [r3, #4] 80058cc: f7fa fe32 bl 8000534 <__aeabi_dadd> 80058d0: 9b00 ldr r3, [sp, #0] 80058d2: 3b01 subs r3, #1 80058d4: 9300 str r3, [sp, #0] 80058d6: e741 b.n 800575c <__kernel_rem_pio2+0x4fc> 80058d8: 9b05 ldr r3, [sp, #20] 80058da: 9a05 ldr r2, [sp, #20] 80058dc: 601d str r5, [r3, #0] 80058de: 2380 movs r3, #128 @ 0x80 80058e0: 061b lsls r3, r3, #24 80058e2: 18f4 adds r4, r6, r3 80058e4: 6054 str r4, [r2, #4] 80058e6: 9a00 ldr r2, [sp, #0] 80058e8: 9c05 ldr r4, [sp, #20] 80058ea: 60a2 str r2, [r4, #8] 80058ec: 001a movs r2, r3 80058ee: 9c01 ldr r4, [sp, #4] 80058f0: 18e3 adds r3, r4, r3 80058f2: 9c05 ldr r4, [sp, #20] 80058f4: 60e3 str r3, [r4, #12] 80058f6: 188b adds r3, r1, r2 80058f8: 6120 str r0, [r4, #16] 80058fa: 6163 str r3, [r4, #20] 80058fc: e710 b.n 8005720 <__kernel_rem_pio2+0x4c0> 80058fe: 46c0 nop @ (mov r8, r8) 8005900: 41700000 .word 0x41700000 8005904: 3e700000 .word 0x3e700000 08005908 <scalbn>: 8005908: 004b lsls r3, r1, #1 800590a: b570 push {r4, r5, r6, lr} 800590c: 0d5b lsrs r3, r3, #21 800590e: 0014 movs r4, r2 8005910: 000d movs r5, r1 8005912: 2b00 cmp r3, #0 8005914: d10f bne.n 8005936 <scalbn+0x2e> 8005916: 004b lsls r3, r1, #1 8005918: 085b lsrs r3, r3, #1 800591a: 4303 orrs r3, r0 800591c: d012 beq.n 8005944 <scalbn+0x3c> 800591e: 4b23 ldr r3, [pc, #140] @ (80059ac <scalbn+0xa4>) 8005920: 2200 movs r2, #0 8005922: f7fb fe07 bl 8001534 <__aeabi_dmul> 8005926: 4b22 ldr r3, [pc, #136] @ (80059b0 <scalbn+0xa8>) 8005928: 429c cmp r4, r3 800592a: da0c bge.n 8005946 <scalbn+0x3e> 800592c: 4a21 ldr r2, [pc, #132] @ (80059b4 <scalbn+0xac>) 800592e: 4b22 ldr r3, [pc, #136] @ (80059b8 <scalbn+0xb0>) 8005930: f7fb fe00 bl 8001534 <__aeabi_dmul> 8005934: e006 b.n 8005944 <scalbn+0x3c> 8005936: 4a21 ldr r2, [pc, #132] @ (80059bc <scalbn+0xb4>) 8005938: 4293 cmp r3, r2 800593a: d108 bne.n 800594e <scalbn+0x46> 800593c: 0002 movs r2, r0 800593e: 000b movs r3, r1 8005940: f7fa fdf8 bl 8000534 <__aeabi_dadd> 8005944: bd70 pop {r4, r5, r6, pc} 8005946: 000d movs r5, r1 8005948: 004b lsls r3, r1, #1 800594a: 0d5b lsrs r3, r3, #21 800594c: 3b36 subs r3, #54 @ 0x36 800594e: 4a1c ldr r2, [pc, #112] @ (80059c0 <scalbn+0xb8>) 8005950: 4294 cmp r4, r2 8005952: dd0a ble.n 800596a <scalbn+0x62> 8005954: 4c1b ldr r4, [pc, #108] @ (80059c4 <scalbn+0xbc>) 8005956: 4d1c ldr r5, [pc, #112] @ (80059c8 <scalbn+0xc0>) 8005958: 2900 cmp r1, #0 800595a: da01 bge.n 8005960 <scalbn+0x58> 800595c: 4c19 ldr r4, [pc, #100] @ (80059c4 <scalbn+0xbc>) 800595e: 4d1b ldr r5, [pc, #108] @ (80059cc <scalbn+0xc4>) 8005960: 4a18 ldr r2, [pc, #96] @ (80059c4 <scalbn+0xbc>) 8005962: 4b19 ldr r3, [pc, #100] @ (80059c8 <scalbn+0xc0>) 8005964: 0020 movs r0, r4 8005966: 0029 movs r1, r5 8005968: e7e2 b.n 8005930 <scalbn+0x28> 800596a: 18e2 adds r2, r4, r3 800596c: 4b18 ldr r3, [pc, #96] @ (80059d0 <scalbn+0xc8>) 800596e: 429a cmp r2, r3 8005970: dcf0 bgt.n 8005954 <scalbn+0x4c> 8005972: 2a00 cmp r2, #0 8005974: dd05 ble.n 8005982 <scalbn+0x7a> 8005976: 4b17 ldr r3, [pc, #92] @ (80059d4 <scalbn+0xcc>) 8005978: 0512 lsls r2, r2, #20 800597a: 402b ands r3, r5 800597c: 4313 orrs r3, r2 800597e: 0019 movs r1, r3 8005980: e7e0 b.n 8005944 <scalbn+0x3c> 8005982: 0013 movs r3, r2 8005984: 3335 adds r3, #53 @ 0x35 8005986: da08 bge.n 800599a <scalbn+0x92> 8005988: 4c0a ldr r4, [pc, #40] @ (80059b4 <scalbn+0xac>) 800598a: 4d0b ldr r5, [pc, #44] @ (80059b8 <scalbn+0xb0>) 800598c: 2900 cmp r1, #0 800598e: da01 bge.n 8005994 <scalbn+0x8c> 8005990: 4c08 ldr r4, [pc, #32] @ (80059b4 <scalbn+0xac>) 8005992: 4d11 ldr r5, [pc, #68] @ (80059d8 <scalbn+0xd0>) 8005994: 4a07 ldr r2, [pc, #28] @ (80059b4 <scalbn+0xac>) 8005996: 4b08 ldr r3, [pc, #32] @ (80059b8 <scalbn+0xb0>) 8005998: e7e4 b.n 8005964 <scalbn+0x5c> 800599a: 4b0e ldr r3, [pc, #56] @ (80059d4 <scalbn+0xcc>) 800599c: 3236 adds r2, #54 @ 0x36 800599e: 401d ands r5, r3 80059a0: 0512 lsls r2, r2, #20 80059a2: 432a orrs r2, r5 80059a4: 0011 movs r1, r2 80059a6: 4b0d ldr r3, [pc, #52] @ (80059dc <scalbn+0xd4>) 80059a8: 2200 movs r2, #0 80059aa: e7c1 b.n 8005930 <scalbn+0x28> 80059ac: 43500000 .word 0x43500000 80059b0: ffff3cb0 .word 0xffff3cb0 80059b4: c2f8f359 .word 0xc2f8f359 80059b8: 01a56e1f .word 0x01a56e1f 80059bc: 000007ff .word 0x000007ff 80059c0: 0000c350 .word 0x0000c350 80059c4: 8800759c .word 0x8800759c 80059c8: 7e37e43c .word 0x7e37e43c 80059cc: fe37e43c .word 0xfe37e43c 80059d0: 000007fe .word 0x000007fe 80059d4: 800fffff .word 0x800fffff 80059d8: 81a56e1f .word 0x81a56e1f 80059dc: 3c900000 .word 0x3c900000 080059e0 <floor>: 80059e0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80059e2: 004b lsls r3, r1, #1 80059e4: 4a36 ldr r2, [pc, #216] @ (8005ac0 <floor+0xe0>) 80059e6: 0d5b lsrs r3, r3, #21 80059e8: 189e adds r6, r3, r2 80059ea: 000c movs r4, r1 80059ec: 0005 movs r5, r0 80059ee: 9001 str r0, [sp, #4] 80059f0: 2e13 cmp r6, #19 80059f2: dc2f bgt.n 8005a54 <floor+0x74> 80059f4: 2e00 cmp r6, #0 80059f6: da14 bge.n 8005a22 <floor+0x42> 80059f8: 4a32 ldr r2, [pc, #200] @ (8005ac4 <floor+0xe4>) 80059fa: 4b33 ldr r3, [pc, #204] @ (8005ac8 <floor+0xe8>) 80059fc: f7fa fd9a bl 8000534 <__aeabi_dadd> 8005a00: 2200 movs r2, #0 8005a02: 2300 movs r3, #0 8005a04: f7fa fd1e bl 8000444 <__aeabi_dcmpgt> 8005a08: 2800 cmp r0, #0 8005a0a: d007 beq.n 8005a1c <floor+0x3c> 8005a0c: 2c00 cmp r4, #0 8005a0e: da50 bge.n 8005ab2 <floor+0xd2> 8005a10: 0064 lsls r4, r4, #1 8005a12: 0864 lsrs r4, r4, #1 8005a14: 4325 orrs r5, r4 8005a16: d14f bne.n 8005ab8 <floor+0xd8> 8005a18: 2480 movs r4, #128 @ 0x80 8005a1a: 0624 lsls r4, r4, #24 8005a1c: 0021 movs r1, r4 8005a1e: 0028 movs r0, r5 8005a20: e022 b.n 8005a68 <floor+0x88> 8005a22: 4f2a ldr r7, [pc, #168] @ (8005acc <floor+0xec>) 8005a24: 4137 asrs r7, r6 8005a26: 003b movs r3, r7 8005a28: 400b ands r3, r1 8005a2a: 4303 orrs r3, r0 8005a2c: d01c beq.n 8005a68 <floor+0x88> 8005a2e: 4a25 ldr r2, [pc, #148] @ (8005ac4 <floor+0xe4>) 8005a30: 4b25 ldr r3, [pc, #148] @ (8005ac8 <floor+0xe8>) 8005a32: f7fa fd7f bl 8000534 <__aeabi_dadd> 8005a36: 2200 movs r2, #0 8005a38: 2300 movs r3, #0 8005a3a: f7fa fd03 bl 8000444 <__aeabi_dcmpgt> 8005a3e: 2800 cmp r0, #0 8005a40: d0ec beq.n 8005a1c <floor+0x3c> 8005a42: 2c00 cmp r4, #0 8005a44: da03 bge.n 8005a4e <floor+0x6e> 8005a46: 2380 movs r3, #128 @ 0x80 8005a48: 035b lsls r3, r3, #13 8005a4a: 4133 asrs r3, r6 8005a4c: 18e4 adds r4, r4, r3 8005a4e: 2500 movs r5, #0 8005a50: 43bc bics r4, r7 8005a52: e7e3 b.n 8005a1c <floor+0x3c> 8005a54: 2e33 cmp r6, #51 @ 0x33 8005a56: dd09 ble.n 8005a6c <floor+0x8c> 8005a58: 2380 movs r3, #128 @ 0x80 8005a5a: 00db lsls r3, r3, #3 8005a5c: 429e cmp r6, r3 8005a5e: d103 bne.n 8005a68 <floor+0x88> 8005a60: 0002 movs r2, r0 8005a62: 000b movs r3, r1 8005a64: f7fa fd66 bl 8000534 <__aeabi_dadd> 8005a68: b003 add sp, #12 8005a6a: bdf0 pop {r4, r5, r6, r7, pc} 8005a6c: 2701 movs r7, #1 8005a6e: 4a18 ldr r2, [pc, #96] @ (8005ad0 <floor+0xf0>) 8005a70: 427f negs r7, r7 8005a72: 189b adds r3, r3, r2 8005a74: 40df lsrs r7, r3 8005a76: 4238 tst r0, r7 8005a78: d0f6 beq.n 8005a68 <floor+0x88> 8005a7a: 4a12 ldr r2, [pc, #72] @ (8005ac4 <floor+0xe4>) 8005a7c: 4b12 ldr r3, [pc, #72] @ (8005ac8 <floor+0xe8>) 8005a7e: f7fa fd59 bl 8000534 <__aeabi_dadd> 8005a82: 2200 movs r2, #0 8005a84: 2300 movs r3, #0 8005a86: f7fa fcdd bl 8000444 <__aeabi_dcmpgt> 8005a8a: 2800 cmp r0, #0 8005a8c: d0c6 beq.n 8005a1c <floor+0x3c> 8005a8e: 2c00 cmp r4, #0 8005a90: da02 bge.n 8005a98 <floor+0xb8> 8005a92: 2e14 cmp r6, #20 8005a94: d102 bne.n 8005a9c <floor+0xbc> 8005a96: 3401 adds r4, #1 8005a98: 43bd bics r5, r7 8005a9a: e7bf b.n 8005a1c <floor+0x3c> 8005a9c: 2234 movs r2, #52 @ 0x34 8005a9e: 2301 movs r3, #1 8005aa0: 1b92 subs r2, r2, r6 8005aa2: 4093 lsls r3, r2 8005aa4: 18ed adds r5, r5, r3 8005aa6: 9b01 ldr r3, [sp, #4] 8005aa8: 429d cmp r5, r3 8005aaa: 419b sbcs r3, r3 8005aac: 425b negs r3, r3 8005aae: 18e4 adds r4, r4, r3 8005ab0: e7f2 b.n 8005a98 <floor+0xb8> 8005ab2: 2500 movs r5, #0 8005ab4: 002c movs r4, r5 8005ab6: e7b1 b.n 8005a1c <floor+0x3c> 8005ab8: 2500 movs r5, #0 8005aba: 4c06 ldr r4, [pc, #24] @ (8005ad4 <floor+0xf4>) 8005abc: e7ae b.n 8005a1c <floor+0x3c> 8005abe: 46c0 nop @ (mov r8, r8) 8005ac0: fffffc01 .word 0xfffffc01 8005ac4: 8800759c .word 0x8800759c 8005ac8: 7e37e43c .word 0x7e37e43c 8005acc: 000fffff .word 0x000fffff 8005ad0: fffffbed .word 0xfffffbed 8005ad4: bff00000 .word 0xbff00000 08005ad8 <_init>: 8005ad8: b5f8 push {r3, r4, r5, r6, r7, lr} 8005ada: 46c0 nop @ (mov r8, r8) 8005adc: bcf8 pop {r3, r4, r5, r6, r7} 8005ade: bc08 pop {r3} 8005ae0: 469e mov lr, r3 8005ae2: 4770 bx lr 08005ae4 <_fini>: 8005ae4: b5f8 push {r3, r4, r5, r6, r7, lr} 8005ae6: 46c0 nop @ (mov r8, r8) 8005ae8: bcf8 pop {r3, r4, r5, r6, r7} 8005aea: bc08 pop {r3} 8005aec: 469e mov lr, r3 8005aee: 4770 bx lr