solar.kicad-drl.rpt
Drill report for ass kicad.kicad_pcb
Created on 2025-03-31T12:16:40+0530

Copper Layer Stackup:
    =============================================================
    L1 :  F.Cu                      front
    L1 :  B.Cu                      back


Drill file 'ass kicad.drl' contains
    plated through holes:
    =============================================================
    T1  0.200mm  0.0079"  (9 holes)
    T2  0.800mm  0.0315"  (2 holes)
    T3  0.920mm  0.0362"  (4 holes)
    T4  1.300mm  0.0512"  (7 holes)
    T5  2.300mm  0.0906"  (2 holes)

    Total plated holes count 24


Not plated through holes are merged with plated holes
    unplated through holes:
    =============================================================

    Total unplated holes count 0