Design Rule Check - ESP32 with USBC V1.drc
Protel Design System Design Rule Check
PCB File : \\Mac\Home\Documents\Hardware & Software\Altium Designer\ESP32 with USBC\ESP32 with USBC V1.1.PcbDoc
Date     : 11/18/2024
Time     : 6:29:34 PM

Processing Rule : Clearance Constraint (Gap=8mil) (InDifferentialPairClass('DIFF90')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=6mil) (WithinRoom('FTDI') or WithinRoom('USBC2')   or WithinRoom('USBC1')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
   Violation between Isolated copper: Split Plane  (GND) on L3. Dead copper detected. Copper area is : 1340.099 sq. mils
Rule Violations :1

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Routing Topology Rule(Topology=Shortest) (All)
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=12mil) (PreferredHoleWidth=12mil) (MinWidth=24mil) (MaxWidth=24mil) (PreferedWidth=24mil) (All)
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=8mil) (Max=8.1mil) (Prefered=8mil)  and Width Constraints (Min=5.1mil) (Max=6.23mil) (Prefered=6.03mil) (InDifferentialPairClass('DIFF90'))
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=20mil) (Air Gap=10mil) (Entries=4) (All)
   Violation between Starved Thermal on L3: Pad ESP-S4(64.724mil,44.921mil) on Multi-Layer. Blocked 3 out of 4 entries.
   Violation between Starved Thermal on L3: Pad J1-1(2675mil,950mil) on Multi-Layer. Blocked 3 out of 4 entries.
Rule Violations :2

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Pads and Vias to follow the Drill pairs settings
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C10-1(443.858mil,360mil) on L1 And Pad C10-2(410mil,360mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C1-1(446.929mil,630mil) on L1 And Pad C1-2(413.071mil,630mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C11-1(565mil,343.071mil) on L1 And Pad C11-2(565mil,376.929mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C12-1(580mil,236.929mil) on L1 And Pad C12-2(580mil,203.071mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C13-1(525mil,236.929mil) on L1 And Pad C13-2(525mil,203.071mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C14-1(2463.071mil,860mil) on L1 And Pad C14-2(2496.929mil,860mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C15-1(2581.929mil,860mil) on L1 And Pad C15-2(2548.071mil,860mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C16-1(1655mil,188.071mil) on L1 And Pad C16-2(1655mil,221.929mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C17-1(1650mil,645mil) on L1 And Pad C17-2(1650mil,678.858mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C2-1(745mil,575mil) on L1 And Pad C2-2(711.142mil,575mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C3-1(745mil,625mil) on L1 And Pad C3-2(711.142mil,625mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C4-1(2672.929mil,860mil) on L1 And Pad C4-2(2639.071mil,860mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C5-1(2638.071mil,145mil) on L1 And Pad C5-2(2671.929mil,145mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C6-1(906.929mil,790mil) on L1 And Pad C6-2(873.071mil,790mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C7-1(635mil,598.071mil) on L1 And Pad C7-2(635mil,631.929mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C8-1(498.071mil,692mil) on L1 And Pad C8-2(531.929mil,692mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.598mil < 10mil) Between Pad C9-1(498.142mil,856mil) on L1 And Pad C9-2(532mil,856mil) on L1 [Top Solder] Mask Sliver [8.598mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D1-1(334.409mil,630mil) on L1 And Pad D1-2(360mil,630mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D2-1(340mil,715mil) on L1 And Pad D2-2(340mil,740.591mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D3-1(340mil,850mil) on L1 And Pad D3-2(340mil,824.409mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (9.78mil < 10mil) Between Pad D4-1(1755mil,201.299mil) on L1 And Pad D4-2(1755mil,238.701mil) on L1 [Top Solder] Mask Sliver [9.78mil]
   Violation between Minimum Solder Mask Sliver Constraint: (9.78mil < 10mil) Between Pad D5-1(1755mil,818.701mil) on L1 And Pad D5-2(1755mil,781.299mil) on L1 [Top Solder] Mask Sliver [9.78mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D6-1(327.205mil,360mil) on L1 And Pad D6-2(352.795mil,360mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D7-1(345mil,155mil) on L1 And Pad D7-2(345mil,180.591mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.811mil < 10mil) Between Pad D8-1(345mil,255.591mil) on L1 And Pad D8-2(345mil,230mil) on L1 [Top Solder] Mask Sliver [7.811mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A1B12(244.843mil,340.984mil) on L1 And Pad ESP-A4B9(244.843mil,309.488mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A4B9(244.843mil,309.488mil) on L1 And Pad ESP-B8(244.843mil,283.898mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A5(244.843mil,264.213mil) on L1 And Pad ESP-B7(244.843mil,244.528mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A5(244.843mil,264.213mil) on L1 And Pad ESP-B8(244.843mil,283.898mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A6(244.843mil,224.843mil) on L1 And Pad ESP-A7(244.843mil,205.157mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A6(244.843mil,224.843mil) on L1 And Pad ESP-B7(244.843mil,244.528mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A7(244.843mil,205.157mil) on L1 And Pad ESP-B6(244.843mil,185.472mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A8(244.843mil,165.787mil) on L1 And Pad ESP-B5(244.843mil,146.102mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-A8(244.843mil,165.787mil) on L1 And Pad ESP-B6(244.843mil,185.472mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-B1A12(244.843mil,89.016mil) on L1 And Pad ESP-B4A9(244.843mil,120.512mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad ESP-B4A9(244.843mil,120.512mil) on L1 And Pad ESP-B5(244.843mil,146.102mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (4.479mil < 10mil) Between Pad J1-2(2575mil,950mil) on Multi-Layer And Via (2548mil,905mil) from L1 to L4 [Bottom Solder] Mask Sliver [4.479mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Pad J5-1(1375mil,500mil) on Multi-Layer And Pad J5-2(1425mil,500mil) on Multi-Layer [Top Solder] Mask Sliver [6mil] / [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Pad J6-1(375mil,550mil) on Multi-Layer And Pad J6-2(375mil,500mil) on Multi-Layer [Top Solder] Mask Sliver [6mil] / [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Pad J6-2(375mil,500mil) on Multi-Layer And Pad J6-3(375mil,450mil) on Multi-Layer [Top Solder] Mask Sliver [6mil] / [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R10-1(410mil,737.008mil) on L1 And Pad R10-2(410mil,702.992mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Pad R1-2(709.016mil,520mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R11-1(410mil,827.992mil) on L1 And Pad R11-2(410mil,862.008mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R12-1(1820mil,240mil) on L1 And Pad R12-2(1820mil,274.016mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R13-1(1815mil,817.008mil) on L1 And Pad R13-2(1815mil,782.992mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R14-1(430mil,177.008mil) on L1 And Pad R14-2(430mil,142.992mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R15-1(430mil,242.992mil) on L1 And Pad R15-2(430mil,277.008mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R16-1(1655mil,272.992mil) on L1 And Pad R16-2(1655mil,307.008mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R17-1(1005mil,607.992mil) on L1 And Pad R17-2(1005mil,642.008mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R18-1(1968.984mil,833mil) on L1 And Pad R18-2(2003mil,833mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R19-1(2079.016mil,150mil) on L1 And Pad R19-2(2045mil,150mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R20-1(1967.984mil,781mil) on L1 And Pad R20-2(2002mil,781mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Pad R2-2(714.992mil,520mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R21-1(2175mil,150mil) on L1 And Pad R21-2(2140.984mil,150mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R22-1(1005mil,852.008mil) on L1 And Pad R22-2(1005mil,817.992mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Pad R23-2(1960mil,515mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Pad R24-2(1959.992mil,450mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Pad R25-2(1965.992mil,515mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Pad R26-2(1965.984mil,450mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R3-1(908.016mil,847mil) on L1 And Pad R3-2(874mil,847mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R4-1(500.984mil,745mil) on L1 And Pad R4-2(535mil,745mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R5-1(500.992mil,798mil) on L1 And Pad R5-2(535.008mil,798mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R6-1(580mil,595.984mil) on L1 And Pad R6-2(580mil,630mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R7-1(897.008mil,535mil) on L1 And Pad R7-2(862.992mil,535mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R8-1(862.992mil,645mil) on L1 And Pad R8-2(897.008mil,645mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.756mil < 10mil) Between Pad R9-1(897.008mil,590mil) on L1 And Pad R9-2(862.992mil,590mil) on L1 [Top Solder] Mask Sliver [8.756mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A1B12(244.843mil,905.984mil) on L1 And Pad UART-A4B9(244.843mil,874.488mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A4B9(244.843mil,874.488mil) on L1 And Pad UART-B8(244.843mil,848.898mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A5(244.843mil,829.213mil) on L1 And Pad UART-B7(244.843mil,809.528mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A5(244.843mil,829.213mil) on L1 And Pad UART-B8(244.843mil,848.898mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A6(244.843mil,789.842mil) on L1 And Pad UART-A7(244.843mil,770.158mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A6(244.843mil,789.842mil) on L1 And Pad UART-B7(244.843mil,809.528mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A7(244.843mil,770.158mil) on L1 And Pad UART-B6(244.843mil,750.472mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A8(244.843mil,730.787mil) on L1 And Pad UART-B5(244.843mil,711.102mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-A8(244.843mil,730.787mil) on L1 And Pad UART-B6(244.843mil,750.472mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-B1A12(244.843mil,654.016mil) on L1 And Pad UART-B4A9(244.843mil,685.512mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.874mil < 10mil) Between Pad UART-B4A9(244.843mil,685.512mil) on L1 And Pad UART-B5(244.843mil,711.102mil) on L1 [Top Solder] Mask Sliver [7.874mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5mil < 10mil) Between Via (1003mil,376mil) from L1 to L4 And Via (1036mil,376mil) from L1 to L4 [Bottom Solder] Mask Sliver [5mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8mil < 10mil) Between Via (1003mil,376mil) from L1 to L4 And Via (967mil,376mil) from L1 to L4 [Bottom Solder] Mask Sliver [8mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5mil < 10mil) Between Via (1003mil,424mil) from L1 to L4 And Via (1036mil,424mil) from L1 to L4 [Bottom Solder] Mask Sliver [5mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8mil < 10mil) Between Via (1003mil,424mil) from L1 to L4 And Via (967mil,424mil) from L1 to L4 [Bottom Solder] Mask Sliver [8mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (1031mil,327mil) from L1 to L4 And Via (1065mil,327mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5mil < 10mil) Between Via (1031mil,327mil) from L1 to L4 And Via (998mil,327mil) from L1 to L4 [Bottom Solder] Mask Sliver [5mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (1036mil,376mil) from L1 to L4 And Via (1070mil,376mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (1036mil,424mil) from L1 to L4 And Via (1070mil,424mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.014mil < 10mil) Between Via (1065mil,327mil) from L1 to L4 And Via (1101mil,326mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.014mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.014mil < 10mil) Between Via (1070mil,376mil) from L1 to L4 And Via (1106mil,375mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.014mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.014mil < 10mil) Between Via (1070mil,424mil) from L1 to L4 And Via (1106mil,423mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.014mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (1730.982mil,595.982mil) from L1 to L4 And Via (1734mil,562.116mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5.02mil < 10mil) Between Via (1868.863mil,503mil) from L1 to L4 And Via (1870mil,470mil) from L1 to L4 [Bottom Solder] Mask Sliver [5.02mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.4mil < 10mil) Between Via (2015mil,645mil) from L1 to L4 And Via (2025mil,610mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.4mil]
   Violation between Minimum Solder Mask Sliver Constraint: (9.363mil < 10mil) Between Via (2025mil,610mil) from L1 to L4 And Via (2061mil,600mil) from L1 to L4 [Bottom Solder] Mask Sliver [9.363mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.967mil < 10mil) Between Via (2160mil,723mil) from L1 to L4 And Via (2193.361mil,709.558mil) from L1 to L4 [Bottom Solder] Mask Sliver [7.967mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.828mil < 10mil) Between Via (2193.361mil,709.558mil) from L1 to L4 And Via (2226.263mil,723.737mil) from L1 to L4 [Bottom Solder] Mask Sliver [7.828mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (2226.263mil,723.737mil) from L1 to L4 And Via (2256.059mil,707.359mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (2256.059mil,707.359mil) from L1 to L4 And Via (2286.335mil,722.83mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.81mil < 10mil) Between Via (2286.335mil,722.83mil) from L1 to L4 And Via (2319.15mil,708.492mil) from L1 to L4 [Bottom Solder] Mask Sliver [7.81mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (2319.15mil,708.492mil) from L1 to L4 And Via (2352.867mil,712.867mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.226mil < 10mil) Between Via (2394.361mil,709.558mil) from L1 to L4 And Via (2428mil,723mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.226mil]
   Violation between Minimum Solder Mask Sliver Constraint: (2.858mil < 10mil) Between Via (2517.145mil,904.527mil) from L1 to L4 And Via (2548mil,905mil) from L1 to L4 [Bottom Solder] Mask Sliver [2.858mil]
   Violation between Minimum Solder Mask Sliver Constraint: (3mil < 10mil) Between Via (2530mil,276mil) from L1 to L4 And Via (2561mil,276mil) from L1 to L4 [Bottom Solder] Mask Sliver [3mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5.061mil < 10mil) Between Via (2595mil,733mil) from L1 to L4 And Via (2628mil,735mil) from L1 to L4 [Bottom Solder] Mask Sliver [5.061mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5.015mil < 10mil) Between Via (2628mil,735mil) from L1 to L4 And Via (2629mil,702mil) from L1 to L4 [Bottom Solder] Mask Sliver [5.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (4mil < 10mil) Between Via (2629mil,267mil) from L1 to L4 And Via (2629mil,299mil) from L1 to L4 [Bottom Solder] Mask Sliver [4mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8mil < 10mil) Between Via (2629mil,299mil) from L1 to L4 And Via (2629mil,335mil) from L1 to L4 [Bottom Solder] Mask Sliver [8mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5.015mil < 10mil) Between Via (2629mil,335mil) from L1 to L4 And Via (2630mil,368mil) from L1 to L4 [Bottom Solder] Mask Sliver [5.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5.015mil < 10mil) Between Via (2629mil,702mil) from L1 to L4 And Via (2630mil,669mil) from L1 to L4 [Bottom Solder] Mask Sliver [5.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.015mil < 10mil) Between Via (2630mil,368mil) from L1 to L4 And Via (2631mil,402mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.015mil < 10mil) Between Via (2630mil,669mil) from L1 to L4 And Via (2631mil,635mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (3.016mil < 10mil) Between Via (2631mil,402mil) from L1 to L4 And Via (2632mil,433mil) from L1 to L4 [Bottom Solder] Mask Sliver [3.016mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.015mil < 10mil) Between Via (2631mil,501mil) from L1 to L4 And Via (2632mil,467mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7.014mil < 10mil) Between Via (2631mil,501mil) from L1 to L4 And Via (2632mil,536mil) from L1 to L4 [Bottom Solder] Mask Sliver [7.014mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.015mil < 10mil) Between Via (2631mil,635mil) from L1 to L4 And Via (2632mil,601mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.015mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Via (2632mil,433mil) from L1 to L4 And Via (2632mil,467mil) from L1 to L4 [Bottom Solder] Mask Sliver [6mil]
   Violation between Minimum Solder Mask Sliver Constraint: (5mil < 10mil) Between Via (2632mil,536mil) from L1 to L4 And Via (2632mil,569mil) from L1 to L4 [Bottom Solder] Mask Sliver [5mil]
   Violation between Minimum Solder Mask Sliver Constraint: (4mil < 10mil) Between Via (2632mil,569mil) from L1 to L4 And Via (2632mil,601mil) from L1 to L4 [Bottom Solder] Mask Sliver [4mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.504mil < 10mil) Between Via (445mil,715mil) from L1 to L4 And Via (463.576mil,746.424mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.504mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.176mil < 10mil) Between Via (450mil,840mil) from L1 to L4 And Via (462mil,872mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.176mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8.278mil < 10mil) Between Via (467.664mil,155.473mil) from L1 to L4 And Via (478.798mil,190.001mil) from L1 to L4 [Bottom Solder] Mask Sliver [8.278mil]
   Violation between Minimum Solder Mask Sliver Constraint: (6.582mil < 10mil) Between Via (469.881mil,255.358mil) from L1 to L4 And Via (479mil,222mil) from L1 to L4 [Bottom Solder] Mask Sliver [6.582mil]
   Violation between Minimum Solder Mask Sliver Constraint: (4mil < 10mil) Between Via (478.798mil,190.001mil) from L1 to L4 And Via (479mil,222mil) from L1 to L4 [Bottom Solder] Mask Sliver [4mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Via (695mil,750mil) from L1 to L4 And Via (695mil,785mil) from L1 to L4 [Bottom Solder] Mask Sliver [7mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Via (695mil,750mil) from L1 to L4 And Via (730mil,750mil) from L1 to L4 [Bottom Solder] Mask Sliver [7mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Via (695mil,785mil) from L1 to L4 And Via (730mil,785mil) from L1 to L4 [Bottom Solder] Mask Sliver [7mil]
   Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Via (730mil,750mil) from L1 to L4 And Via (730mil,785mil) from L1 to L4 [Bottom Solder] Mask Sliver [7mil]
   Violation between Minimum Solder Mask Sliver Constraint: (3mil < 10mil) Between Via (779mil,575mil) from L1 to L4 And Via (779mil,606mil) from L1 to L4 [Bottom Solder] Mask Sliver [3mil]
   Violation between Minimum Solder Mask Sliver Constraint: (8mil < 10mil) Between Via (962mil,327mil) from L1 to L4 And Via (998mil,327mil) from L1 to L4 [Bottom Solder] Mask Sliver [8mil]
Rule Violations :127

Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
   Violation between Silk To Solder Mask Clearance Constraint: (8.177mil < 10mil) Between Arc (2629.252mil,832.677mil) on Top Overlay And Pad C4-2(2639.071mil,860mil) on L1 [Top Overlay] to [Top Solder] clearance [8.177mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.858mil < 10mil) Between Area Fill (1727.5mil,181.5mil) (1735.5mil,182.5mil) on Top Overlay And Pad D4-1(1755mil,201.299mil) on L1 [Top Overlay] to [Top Solder] clearance [9.858mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.858mil < 10mil) Between Area Fill (1774.5mil,837.5mil) (1782.5mil,838.5mil) on Top Overlay And Pad D5-1(1755mil,818.701mil) on L1 [Top Overlay] to [Top Solder] clearance [9.858mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C10-1(443.858mil,360mil) on L1 And Track (391.929mil,338mil)(461.929mil,338mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C10-1(443.858mil,360mil) on L1 And Track (391.929mil,382mil)(461.929mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C10-1(443.858mil,360mil) on L1 And Track (461.929mil,338mil)(461.929mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C10-2(410mil,360mil) on L1 And Track (391.929mil,338mil)(391.929mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C10-2(410mil,360mil) on L1 And Track (391.929mil,338mil)(461.929mil,338mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C10-2(410mil,360mil) on L1 And Track (391.929mil,382mil)(461.929mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C1-1(446.929mil,630mil) on L1 And Track (395mil,608mil)(465mil,608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C1-1(446.929mil,630mil) on L1 And Track (395mil,652mil)(465mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C1-1(446.929mil,630mil) on L1 And Track (465mil,608mil)(465mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C11-1(565mil,343.071mil) on L1 And Track (543mil,325mil)(543mil,395mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C11-1(565mil,343.071mil) on L1 And Track (543mil,325mil)(587mil,325mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C11-1(565mil,343.071mil) on L1 And Track (587mil,325mil)(587mil,395mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C11-2(565mil,376.929mil) on L1 And Track (543mil,325mil)(543mil,395mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C11-2(565mil,376.929mil) on L1 And Track (543mil,395mil)(587mil,395mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C11-2(565mil,376.929mil) on L1 And Track (587mil,325mil)(587mil,395mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C1-2(413.071mil,630mil) on L1 And Track (395mil,608mil)(395mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C1-2(413.071mil,630mil) on L1 And Track (395mil,608mil)(465mil,608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C1-2(413.071mil,630mil) on L1 And Track (395mil,652mil)(465mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C12-1(580mil,236.929mil) on L1 And Track (558mil,185mil)(558mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C12-1(580mil,236.929mil) on L1 And Track (558mil,255mil)(602mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C12-1(580mil,236.929mil) on L1 And Track (602mil,185mil)(602mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C12-2(580mil,203.071mil) on L1 And Track (558mil,185mil)(558mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C12-2(580mil,203.071mil) on L1 And Track (558mil,185mil)(602mil,185mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C12-2(580mil,203.071mil) on L1 And Track (602mil,185mil)(602mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C13-1(525mil,236.929mil) on L1 And Track (503mil,185mil)(503mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C13-1(525mil,236.929mil) on L1 And Track (503mil,255mil)(547mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C13-1(525mil,236.929mil) on L1 And Track (547mil,185mil)(547mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C13-2(525mil,203.071mil) on L1 And Track (503mil,185mil)(503mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C13-2(525mil,203.071mil) on L1 And Track (503mil,185mil)(547mil,185mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C13-2(525mil,203.071mil) on L1 And Track (547mil,185mil)(547mil,255mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C14-1(2463.071mil,860mil) on L1 And Track (2445mil,838mil)(2445mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C14-1(2463.071mil,860mil) on L1 And Track (2445mil,838mil)(2515mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C14-1(2463.071mil,860mil) on L1 And Track (2445mil,882mil)(2515mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C14-2(2496.929mil,860mil) on L1 And Track (2445mil,838mil)(2515mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C14-2(2496.929mil,860mil) on L1 And Track (2445mil,882mil)(2515mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C14-2(2496.929mil,860mil) on L1 And Track (2515mil,838mil)(2515mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C15-1(2581.929mil,860mil) on L1 And Track (2530mil,838mil)(2600mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C15-1(2581.929mil,860mil) on L1 And Track (2530mil,882mil)(2600mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C15-1(2581.929mil,860mil) on L1 And Track (2600mil,838mil)(2600mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C15-2(2548.071mil,860mil) on L1 And Track (2530mil,838mil)(2530mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C15-2(2548.071mil,860mil) on L1 And Track (2530mil,838mil)(2600mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C15-2(2548.071mil,860mil) on L1 And Track (2530mil,882mil)(2600mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C16-1(1655mil,188.071mil) on L1 And Track (1633mil,170mil)(1633mil,240mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C16-1(1655mil,188.071mil) on L1 And Track (1633mil,170mil)(1677mil,170mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C16-1(1655mil,188.071mil) on L1 And Track (1677mil,170mil)(1677mil,240mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C16-2(1655mil,221.929mil) on L1 And Track (1633mil,170mil)(1633mil,240mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C16-2(1655mil,221.929mil) on L1 And Track (1633mil,240mil)(1677mil,240mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C16-2(1655mil,221.929mil) on L1 And Track (1677mil,170mil)(1677mil,240mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C17-1(1650mil,645mil) on L1 And Track (1628mil,626.929mil)(1628mil,696.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C17-1(1650mil,645mil) on L1 And Track (1628mil,626.929mil)(1672mil,626.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C17-1(1650mil,645mil) on L1 And Track (1672mil,626.929mil)(1672mil,696.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C17-2(1650mil,678.858mil) on L1 And Track (1628mil,626.929mil)(1628mil,696.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C17-2(1650mil,678.858mil) on L1 And Track (1628mil,696.929mil)(1672mil,696.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C17-2(1650mil,678.858mil) on L1 And Track (1672mil,626.929mil)(1672mil,696.929mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C2-1(745mil,575mil) on L1 And Track (693.071mil,553mil)(763.071mil,553mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C2-1(745mil,575mil) on L1 And Track (693.071mil,597mil)(763.071mil,597mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C2-1(745mil,575mil) on L1 And Track (763.071mil,553mil)(763.071mil,597mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C2-2(711.142mil,575mil) on L1 And Track (693.071mil,553mil)(693.071mil,597mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C2-2(711.142mil,575mil) on L1 And Track (693.071mil,553mil)(763.071mil,553mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C2-2(711.142mil,575mil) on L1 And Track (693.071mil,597mil)(763.071mil,597mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C3-1(745mil,625mil) on L1 And Track (693.071mil,603mil)(763.071mil,603mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C3-1(745mil,625mil) on L1 And Track (693.071mil,647mil)(763.071mil,647mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C3-1(745mil,625mil) on L1 And Track (763.071mil,603mil)(763.071mil,647mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C3-2(711.142mil,625mil) on L1 And Track (693.071mil,603mil)(693.071mil,647mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C3-2(711.142mil,625mil) on L1 And Track (693.071mil,603mil)(763.071mil,603mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C3-2(711.142mil,625mil) on L1 And Track (693.071mil,647mil)(763.071mil,647mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C4-1(2672.929mil,860mil) on L1 And Track (2621mil,838mil)(2691mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C4-1(2672.929mil,860mil) on L1 And Track (2621mil,882mil)(2691mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C4-1(2672.929mil,860mil) on L1 And Track (2691mil,838mil)(2691mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C4-2(2639.071mil,860mil) on L1 And Track (2621mil,838mil)(2621mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C4-2(2639.071mil,860mil) on L1 And Track (2621mil,838mil)(2691mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C4-2(2639.071mil,860mil) on L1 And Track (2621mil,882mil)(2691mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C5-1(2638.071mil,145mil) on L1 And Track (2620mil,123mil)(2620mil,167mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C5-1(2638.071mil,145mil) on L1 And Track (2620mil,123mil)(2690mil,123mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C5-1(2638.071mil,145mil) on L1 And Track (2620mil,167mil)(2690mil,167mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C5-2(2671.929mil,145mil) on L1 And Track (2620mil,123mil)(2690mil,123mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C5-2(2671.929mil,145mil) on L1 And Track (2620mil,167mil)(2690mil,167mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C5-2(2671.929mil,145mil) on L1 And Track (2690mil,123mil)(2690mil,167mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C6-1(906.929mil,790mil) on L1 And Track (855mil,768mil)(925mil,768mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C6-1(906.929mil,790mil) on L1 And Track (855mil,812mil)(925mil,812mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C6-1(906.929mil,790mil) on L1 And Track (925mil,768mil)(925mil,812mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C6-2(873.071mil,790mil) on L1 And Track (855mil,768mil)(855mil,812mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C6-2(873.071mil,790mil) on L1 And Track (855mil,768mil)(925mil,768mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C6-2(873.071mil,790mil) on L1 And Track (855mil,812mil)(925mil,812mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C7-1(635mil,598.071mil) on L1 And Track (613mil,580mil)(613mil,650mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C7-1(635mil,598.071mil) on L1 And Track (613mil,580mil)(657mil,580mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C7-1(635mil,598.071mil) on L1 And Track (657mil,580mil)(657mil,650mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C7-2(635mil,631.929mil) on L1 And Track (613mil,580mil)(613mil,650mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C7-2(635mil,631.929mil) on L1 And Track (613mil,650mil)(657mil,650mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C7-2(635mil,631.929mil) on L1 And Track (657mil,580mil)(657mil,650mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C8-1(498.071mil,692mil) on L1 And Track (480mil,670mil)(480mil,714mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C8-1(498.071mil,692mil) on L1 And Track (480mil,670mil)(550mil,670mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C8-1(498.071mil,692mil) on L1 And Track (480mil,714mil)(550mil,714mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C8-2(531.929mil,692mil) on L1 And Track (480mil,670mil)(550mil,670mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C8-2(531.929mil,692mil) on L1 And Track (480mil,714mil)(550mil,714mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C8-2(531.929mil,692mil) on L1 And Track (550mil,670mil)(550mil,714mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C9-1(498.142mil,856mil) on L1 And Track (480.071mil,834mil)(480.071mil,878mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C9-1(498.142mil,856mil) on L1 And Track (480.071mil,834mil)(550.071mil,834mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C9-1(498.142mil,856mil) on L1 And Track (480.071mil,878mil)(550.071mil,878mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C9-2(532mil,856mil) on L1 And Track (480.071mil,834mil)(550.071mil,834mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.185mil < 10mil) Between Pad C9-2(532mil,856mil) on L1 And Track (480.071mil,878mil)(550.071mil,878mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.185mil]
   Violation between Silk To Solder Mask Clearance Constraint: (4.437mil < 10mil) Between Pad C9-2(532mil,856mil) on L1 And Track (550.071mil,834mil)(550.071mil,878mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.437mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D1-1(334.409mil,630mil) on L1 And Track (317.205mil,608mil)(317.205mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D1-1(334.409mil,630mil) on L1 And Track (317.205mil,608mil)(377.205mil,608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D1-1(334.409mil,630mil) on L1 And Track (317.205mil,652mil)(377.205mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D1-2(360mil,630mil) on L1 And Track (317.205mil,608mil)(377.205mil,608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D1-2(360mil,630mil) on L1 And Track (317.205mil,652mil)(377.205mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D1-2(360mil,630mil) on L1 And Track (377.205mil,608mil)(377.205mil,652mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D2-1(340mil,715mil) on L1 And Track (318mil,697.795mil)(318mil,757.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D2-1(340mil,715mil) on L1 And Track (318mil,697.795mil)(362mil,697.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D2-1(340mil,715mil) on L1 And Track (362mil,697.795mil)(362mil,757.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D2-2(340mil,740.591mil) on L1 And Track (318mil,697.795mil)(318mil,757.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D2-2(340mil,740.591mil) on L1 And Track (318mil,757.795mil)(362mil,757.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D2-2(340mil,740.591mil) on L1 And Track (362mil,697.795mil)(362mil,757.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D3-1(340mil,850mil) on L1 And Track (318mil,807.205mil)(318mil,867.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D3-1(340mil,850mil) on L1 And Track (318mil,867.205mil)(362mil,867.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D3-1(340mil,850mil) on L1 And Track (362mil,807.205mil)(362mil,867.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D3-2(340mil,824.409mil) on L1 And Track (318mil,807.205mil)(318mil,867.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D3-2(340mil,824.409mil) on L1 And Track (318mil,807.205mil)(362mil,807.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D3-2(340mil,824.409mil) on L1 And Track (362mil,807.205mil)(362mil,867.205mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.221mil < 10mil) Between Pad D4-1(1755mil,201.299mil) on L1 And Track (1731mil,178mil)(1731mil,262mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (8.488mil < 10mil) Between Pad D4-1(1755mil,201.299mil) on L1 And Track (1731mil,178mil)(1778mil,178mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.488mil]
   Violation between Silk To Solder Mask Clearance Constraint: (6.221mil < 10mil) Between Pad D4-1(1755mil,201.299mil) on L1 And Track (1778mil,178mil)(1778mil,262mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.221mil < 10mil) Between Pad D4-2(1755mil,238.701mil) on L1 And Track (1731mil,178mil)(1731mil,262mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (8.488mil < 10mil) Between Pad D4-2(1755mil,238.701mil) on L1 And Track (1731mil,262mil)(1778mil,262mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.488mil]
   Violation between Silk To Solder Mask Clearance Constraint: (6.221mil < 10mil) Between Pad D4-2(1755mil,238.701mil) on L1 And Track (1778mil,178mil)(1778mil,262mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (6.221mil < 10mil) Between Pad D5-1(1755mil,818.701mil) on L1 And Track (1732mil,758mil)(1732mil,842mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (8.488mil < 10mil) Between Pad D5-1(1755mil,818.701mil) on L1 And Track (1732mil,842mil)(1779mil,842mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.488mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.221mil < 10mil) Between Pad D5-1(1755mil,818.701mil) on L1 And Track (1779mil,758mil)(1779mil,842mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (6.221mil < 10mil) Between Pad D5-2(1755mil,781.299mil) on L1 And Track (1732mil,758mil)(1732mil,842mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (8.488mil < 10mil) Between Pad D5-2(1755mil,781.299mil) on L1 And Track (1732mil,758mil)(1779mil,758mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.488mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.221mil < 10mil) Between Pad D5-2(1755mil,781.299mil) on L1 And Track (1779mil,758mil)(1779mil,842mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.221mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D6-1(327.205mil,360mil) on L1 And Track (310mil,338mil)(310mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D6-1(327.205mil,360mil) on L1 And Track (310mil,338mil)(370mil,338mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D6-1(327.205mil,360mil) on L1 And Track (310mil,382mil)(370mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D6-2(352.795mil,360mil) on L1 And Track (310mil,338mil)(370mil,338mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D6-2(352.795mil,360mil) on L1 And Track (310mil,382mil)(370mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D6-2(352.795mil,360mil) on L1 And Track (370mil,338mil)(370mil,382mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D7-1(345mil,155mil) on L1 And Track (323mil,137.795mil)(323mil,197.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D7-1(345mil,155mil) on L1 And Track (323mil,137.795mil)(367mil,137.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D7-1(345mil,155mil) on L1 And Track (367mil,137.795mil)(367mil,197.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D7-2(345mil,180.591mil) on L1 And Track (323mil,137.795mil)(323mil,197.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D7-2(345mil,180.591mil) on L1 And Track (323mil,197.795mil)(367mil,197.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D7-2(345mil,180.591mil) on L1 And Track (367mil,137.795mil)(367mil,197.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D8-1(345mil,255.591mil) on L1 And Track (323mil,212.795mil)(323mil,272.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D8-1(345mil,255.591mil) on L1 And Track (323mil,272.795mil)(367mil,272.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D8-1(345mil,255.591mil) on L1 And Track (367mil,212.795mil)(367mil,272.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D8-2(345mil,230mil) on L1 And Track (323mil,212.795mil)(323mil,272.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.315mil < 10mil) Between Pad D8-2(345mil,230mil) on L1 And Track (323mil,212.795mil)(367mil,212.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.315mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad D8-2(345mil,230mil) on L1 And Track (367mil,212.795mil)(367mil,272.795mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-1(1375mil,500mil) on Multi-Layer And Text "DESIGNED BY AMEER ALWADIYA" (2300mil,435mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-2(1425mil,500mil) on Multi-Layer And Text "DESIGNED BY AMEER ALWADIYA" (2300mil,435mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.687mil < 10mil) Between Pad Q1-1(1077.577mil,692.402mil) on L1 And Track (1115mil,712.087mil)(1140.591mil,712.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.687mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.687mil < 10mil) Between Pad Q2-1(1077.577mil,842.402mil) on L1 And Track (1115mil,862.087mil)(1140.591mil,862.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.687mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R10-1(410mil,737.008mil) on L1 And Track (388mil,682mil)(388mil,757mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R10-1(410mil,737.008mil) on L1 And Track (389mil,758mil)(432mil,758mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R10-1(410mil,737.008mil) on L1 And Track (432mil,683mil)(432mil,758mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R10-2(410mil,702.992mil) on L1 And Track (388mil,682mil)(388mil,757mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R10-2(410mil,702.992mil) on L1 And Track (388mil,682mil)(431mil,682mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R10-2(410mil,702.992mil) on L1 And Track (432mil,683mil)(432mil,758mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Track (654.008mil,499mil)(654.008mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Track (654.008mil,542mil)(729.008mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Track (655.008mil,498mil)(730.008mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.37mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Track (694mil,499mil)(694mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.43mil < 10mil) Between Pad R1-1(675mil,520mil) on L1 And Track (694mil,499mil)(695mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.43mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R11-1(410mil,827.992mil) on L1 And Track (388mil,807mil)(388mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R11-1(410mil,827.992mil) on L1 And Track (388mil,807mil)(431mil,807mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R11-1(410mil,827.992mil) on L1 And Track (432mil,808mil)(432mil,883mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R11-2(410mil,862.008mil) on L1 And Track (388mil,807mil)(388mil,882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R11-2(410mil,862.008mil) on L1 And Track (389mil,883mil)(432mil,883mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R11-2(410mil,862.008mil) on L1 And Track (432mil,808mil)(432mil,883mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (654.008mil,542mil)(729.008mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (655.008mil,498mil)(730.008mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.386mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (694mil,499mil)(694mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.182mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (694mil,499mil)(695mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.182mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (694mil,542mil)(769mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (695mil,498mil)(770mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R1-2(709.016mil,520mil) on L1 And Track (730.008mil,498mil)(730.008mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R12-1(1820mil,240mil) on L1 And Track (1798mil,219.008mil)(1798mil,294.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R12-1(1820mil,240mil) on L1 And Track (1798mil,219.008mil)(1841mil,219.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R12-1(1820mil,240mil) on L1 And Track (1842mil,220.008mil)(1842mil,295.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R12-2(1820mil,274.016mil) on L1 And Track (1798mil,219.008mil)(1798mil,294.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R12-2(1820mil,274.016mil) on L1 And Track (1799mil,295.008mil)(1842mil,295.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R12-2(1820mil,274.016mil) on L1 And Track (1842mil,220.008mil)(1842mil,295.008mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R13-1(1815mil,817.008mil) on L1 And Track (1793mil,762mil)(1793mil,837mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R13-1(1815mil,817.008mil) on L1 And Track (1794mil,838mil)(1837mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R13-1(1815mil,817.008mil) on L1 And Track (1837mil,763mil)(1837mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R13-2(1815mil,782.992mil) on L1 And Track (1793mil,762mil)(1793mil,837mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R13-2(1815mil,782.992mil) on L1 And Track (1793mil,762mil)(1836mil,762mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R13-2(1815mil,782.992mil) on L1 And Track (1837mil,763mil)(1837mil,838mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R14-1(430mil,177.008mil) on L1 And Track (408mil,122mil)(408mil,197mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R14-1(430mil,177.008mil) on L1 And Track (409mil,198mil)(452mil,198mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R14-1(430mil,177.008mil) on L1 And Track (452mil,123mil)(452mil,198mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R14-2(430mil,142.992mil) on L1 And Track (408mil,122mil)(408mil,197mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R14-2(430mil,142.992mil) on L1 And Track (408mil,122mil)(451mil,122mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R14-2(430mil,142.992mil) on L1 And Track (452mil,123mil)(452mil,198mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R15-1(430mil,242.992mil) on L1 And Track (408mil,222mil)(408mil,297mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R15-1(430mil,242.992mil) on L1 And Track (408mil,222mil)(451mil,222mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R15-1(430mil,242.992mil) on L1 And Track (452mil,223mil)(452mil,298mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R15-2(430mil,277.008mil) on L1 And Track (408mil,222mil)(408mil,297mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R15-2(430mil,277.008mil) on L1 And Track (409mil,298mil)(452mil,298mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R15-2(430mil,277.008mil) on L1 And Track (452mil,223mil)(452mil,298mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R16-1(1655mil,272.992mil) on L1 And Track (1633mil,252mil)(1633mil,327mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R16-1(1655mil,272.992mil) on L1 And Track (1633mil,252mil)(1676mil,252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R16-1(1655mil,272.992mil) on L1 And Track (1677mil,253mil)(1677mil,328mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R16-2(1655mil,307.008mil) on L1 And Track (1633mil,252mil)(1633mil,327mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R16-2(1655mil,307.008mil) on L1 And Track (1634mil,328mil)(1677mil,328mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R16-2(1655mil,307.008mil) on L1 And Track (1677mil,253mil)(1677mil,328mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R17-1(1005mil,607.992mil) on L1 And Track (1027mil,588mil)(1027mil,663mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R17-1(1005mil,607.992mil) on L1 And Track (983mil,587mil)(1026mil,587mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R17-1(1005mil,607.992mil) on L1 And Track (983mil,587mil)(983mil,662mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R17-2(1005mil,642.008mil) on L1 And Track (1027mil,588mil)(1027mil,663mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R17-2(1005mil,642.008mil) on L1 And Track (983mil,587mil)(983mil,662mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R17-2(1005mil,642.008mil) on L1 And Track (984mil,663mil)(1027mil,663mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R18-1(1968.984mil,833mil) on L1 And Track (1947.992mil,812mil)(1947.992mil,855mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R18-1(1968.984mil,833mil) on L1 And Track (1947.992mil,855mil)(2022.992mil,855mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R18-1(1968.984mil,833mil) on L1 And Track (1948.992mil,811mil)(2023.992mil,811mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R18-2(2003mil,833mil) on L1 And Track (1947.992mil,855mil)(2022.992mil,855mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R18-2(2003mil,833mil) on L1 And Track (1948.992mil,811mil)(2023.992mil,811mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R18-2(2003mil,833mil) on L1 And Track (2023.992mil,811mil)(2023.992mil,854mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R19-1(2079.016mil,150mil) on L1 And Track (2024.008mil,172mil)(2099.008mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R19-1(2079.016mil,150mil) on L1 And Track (2025.008mil,128mil)(2100.008mil,128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R19-1(2079.016mil,150mil) on L1 And Track (2100.008mil,128mil)(2100.008mil,171mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R19-2(2045mil,150mil) on L1 And Track (2024.008mil,129mil)(2024.008mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R19-2(2045mil,150mil) on L1 And Track (2024.008mil,172mil)(2099.008mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R19-2(2045mil,150mil) on L1 And Track (2025.008mil,128mil)(2100.008mil,128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R20-1(1967.984mil,781mil) on L1 And Track (1946.992mil,760mil)(1946.992mil,803mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R20-1(1967.984mil,781mil) on L1 And Track (1946.992mil,803mil)(2021.992mil,803mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R20-1(1967.984mil,781mil) on L1 And Track (1947.992mil,759mil)(2022.992mil,759mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R20-2(2002mil,781mil) on L1 And Track (1946.992mil,803mil)(2021.992mil,803mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R20-2(2002mil,781mil) on L1 And Track (1947.992mil,759mil)(2022.992mil,759mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R20-2(2002mil,781mil) on L1 And Track (2022.992mil,759mil)(2022.992mil,802mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Track (694mil,542mil)(769mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Track (695mil,498mil)(770mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.43mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Track (729.008mil,542mil)(730.008mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.43mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.37mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Track (730.008mil,498mil)(730.008mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R2-1(749.008mil,520mil) on L1 And Track (770mil,498mil)(770mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R21-1(2175mil,150mil) on L1 And Track (2119.992mil,172mil)(2194.992mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R21-1(2175mil,150mil) on L1 And Track (2120.992mil,128mil)(2195.992mil,128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R21-1(2175mil,150mil) on L1 And Track (2195.992mil,128mil)(2195.992mil,171mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R21-2(2140.984mil,150mil) on L1 And Track (2119.992mil,129mil)(2119.992mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R21-2(2140.984mil,150mil) on L1 And Track (2119.992mil,172mil)(2194.992mil,172mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R21-2(2140.984mil,150mil) on L1 And Track (2120.992mil,128mil)(2195.992mil,128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (654.008mil,542mil)(729.008mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (655.008mil,498mil)(730.008mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (694mil,499mil)(694mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (694mil,542mil)(769mil,542mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (695mil,498mil)(770mil,498mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.182mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (729.008mil,542mil)(730.008mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.182mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.386mil < 10mil) Between Pad R2-2(714.992mil,520mil) on L1 And Track (730.008mil,498mil)(730.008mil,541mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R22-1(1005mil,852.008mil) on L1 And Track (1027mil,798mil)(1027mil,873mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R22-1(1005mil,852.008mil) on L1 And Track (983mil,797mil)(983mil,872mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R22-1(1005mil,852.008mil) on L1 And Track (984mil,873mil)(1027mil,873mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R22-2(1005mil,817.992mil) on L1 And Track (1027mil,798mil)(1027mil,873mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R22-2(1005mil,817.992mil) on L1 And Track (983mil,797mil)(1026mil,797mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R22-2(1005mil,817.992mil) on L1 And Track (983mil,797mil)(983mil,872mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Track (1904.992mil,494mil)(1904.992mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Track (1904.992mil,537mil)(1979.992mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Track (1905.992mil,493mil)(1980.992mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.386mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Track (1945mil,494mil)(1945mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.44mil < 10mil) Between Pad R23-1(1925.984mil,515mil) on L1 And Track (1945mil,494mil)(1946mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.44mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1904.992mil,537mil)(1979.992mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1905.992mil,493mil)(1980.992mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.37mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1945mil,494mil)(1945mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.175mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1945mil,494mil)(1946mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.175mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1945mil,537mil)(2020mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1946mil,493mil)(2021mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R23-2(1960mil,515mil) on L1 And Track (1980.992mil,493mil)(1980.992mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Track (1904.984mil,429mil)(1904.984mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Track (1904.984mil,472mil)(1979.984mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Track (1905.984mil,428mil)(1980.984mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.386mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Track (1944.992mil,429mil)(1944.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.44mil < 10mil) Between Pad R24-1(1925.976mil,450mil) on L1 And Track (1944.992mil,429mil)(1945.992mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.44mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1904.984mil,472mil)(1979.984mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1905.984mil,428mil)(1980.984mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.37mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1944.992mil,429mil)(1944.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.175mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1944.992mil,429mil)(1945.992mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.175mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1944.992mil,472mil)(2019.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1945.992mil,428mil)(2020.992mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R24-2(1959.992mil,450mil) on L1 And Track (1980.984mil,428mil)(1980.984mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Track (1945mil,537mil)(2020mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Track (1946mil,493mil)(2021mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.44mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Track (1979.992mil,537mil)(1980.992mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.44mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.386mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Track (1980.992mil,493mil)(1980.992mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R25-1(2000.008mil,515mil) on L1 And Track (2021mil,493mil)(2021mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1904.992mil,537mil)(1979.992mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1905.992mil,493mil)(1980.992mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1945mil,494mil)(1945mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1945mil,537mil)(2020mil,537mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1946mil,493mil)(2021mil,493mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.175mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1979.992mil,537mil)(1980.992mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.175mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.37mil < 10mil) Between Pad R25-2(1965.992mil,515mil) on L1 And Track (1980.992mil,493mil)(1980.992mil,536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Track (1944.992mil,472mil)(2019.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Track (1945.992mil,428mil)(2020.992mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (9.44mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Track (1979.984mil,472mil)(1980.984mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.44mil]
   Violation between Silk To Solder Mask Clearance Constraint: (5.386mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Track (1980.984mil,428mil)(1980.984mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.386mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R26-1(2000mil,450mil) on L1 And Track (2020.992mil,428mil)(2020.992mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1904.984mil,472mil)(1979.984mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1905.984mil,428mil)(1980.984mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1944.992mil,429mil)(1944.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1944.992mil,472mil)(2019.992mil,472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1945.992mil,428mil)(2020.992mil,428mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.175mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1979.984mil,472mil)(1980.984mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.175mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.37mil < 10mil) Between Pad R26-2(1965.984mil,450mil) on L1 And Track (1980.984mil,428mil)(1980.984mil,471mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.37mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R3-1(908.016mil,847mil) on L1 And Track (853.008mil,869mil)(928.008mil,869mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R3-1(908.016mil,847mil) on L1 And Track (854.008mil,825mil)(929.008mil,825mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R3-1(908.016mil,847mil) on L1 And Track (929.008mil,825mil)(929.008mil,868mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R3-2(874mil,847mil) on L1 And Track (853.008mil,826mil)(853.008mil,869mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R3-2(874mil,847mil) on L1 And Track (853.008mil,869mil)(928.008mil,869mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R3-2(874mil,847mil) on L1 And Track (854.008mil,825mil)(929.008mil,825mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R4-1(500.984mil,745mil) on L1 And Track (479.992mil,724mil)(479.992mil,767mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R4-1(500.984mil,745mil) on L1 And Track (479.992mil,767mil)(554.992mil,767mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R4-1(500.984mil,745mil) on L1 And Track (480.992mil,723mil)(555.992mil,723mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R4-2(535mil,745mil) on L1 And Track (479.992mil,767mil)(554.992mil,767mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R4-2(535mil,745mil) on L1 And Track (480.992mil,723mil)(555.992mil,723mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R4-2(535mil,745mil) on L1 And Track (555.992mil,723mil)(555.992mil,766mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R5-1(500.992mil,798mil) on L1 And Track (480mil,777mil)(480mil,820mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R5-1(500.992mil,798mil) on L1 And Track (480mil,820mil)(555mil,820mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R5-1(500.992mil,798mil) on L1 And Track (481mil,776mil)(556mil,776mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R5-2(535.008mil,798mil) on L1 And Track (480mil,820mil)(555mil,820mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R5-2(535.008mil,798mil) on L1 And Track (481mil,776mil)(556mil,776mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R5-2(535.008mil,798mil) on L1 And Track (556mil,776mil)(556mil,819mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R6-1(580mil,595.984mil) on L1 And Track (558mil,574.992mil)(558mil,649.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R6-1(580mil,595.984mil) on L1 And Track (558mil,574.992mil)(601mil,574.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R6-1(580mil,595.984mil) on L1 And Track (602mil,575.992mil)(602mil,650.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R6-2(580mil,630mil) on L1 And Track (558mil,574.992mil)(558mil,649.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R6-2(580mil,630mil) on L1 And Track (559mil,650.992mil)(602mil,650.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R6-2(580mil,630mil) on L1 And Track (602mil,575.992mil)(602mil,650.992mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R7-1(897.008mil,535mil) on L1 And Track (842mil,557mil)(917mil,557mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R7-1(897.008mil,535mil) on L1 And Track (843mil,513mil)(918mil,513mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R7-1(897.008mil,535mil) on L1 And Track (918mil,513mil)(918mil,556mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R7-2(862.992mil,535mil) on L1 And Track (842mil,514mil)(842mil,557mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R7-2(862.992mil,535mil) on L1 And Track (842mil,557mil)(917mil,557mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R7-2(862.992mil,535mil) on L1 And Track (843mil,513mil)(918mil,513mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R8-1(862.992mil,645mil) on L1 And Track (842mil,624mil)(842mil,667mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R8-1(862.992mil,645mil) on L1 And Track (842mil,667mil)(917mil,667mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R8-1(862.992mil,645mil) on L1 And Track (843mil,623mil)(918mil,623mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R8-2(897.008mil,645mil) on L1 And Track (842mil,667mil)(917mil,667mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R8-2(897.008mil,645mil) on L1 And Track (843mil,623mil)(918mil,623mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R8-2(897.008mil,645mil) on L1 And Track (918mil,623mil)(918mil,666mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R9-1(897.008mil,590mil) on L1 And Track (842mil,612mil)(917mil,612mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R9-1(897.008mil,590mil) on L1 And Track (843mil,568mil)(918mil,568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R9-1(897.008mil,590mil) on L1 And Track (918mil,568mil)(918mil,611mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.362mil < 10mil) Between Pad R9-2(862.992mil,590mil) on L1 And Track (842mil,569mil)(842mil,612mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.362mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R9-2(862.992mil,590mil) on L1 And Track (842mil,612mil)(917mil,612mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.189mil < 10mil) Between Pad R9-2(862.992mil,590mil) on L1 And Track (843mil,568mil)(918mil,568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.189mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.87mil < 10mil) Between Pad SSU3-1(656.968mil,380.551mil) on L1 And Track (703.228mil,158.11mil)(703.228mil,421.89mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.87mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.87mil < 10mil) Between Pad SSU3-2(656.968mil,290mil) on L1 And Track (703.228mil,158.11mil)(703.228mil,421.89mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.87mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.87mil < 10mil) Between Pad SSU3-3(656.968mil,199.449mil) on L1 And Track (703.228mil,158.11mil)(703.228mil,421.89mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.87mil]
   Violation between Silk To Solder Mask Clearance Constraint: (7.87mil < 10mil) Between Pad SSU3-4(903.032mil,290mil) on L1 And Track (856.772mil,158.11mil)(856.772mil,421.89mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.87mil]
Rule Violations :353

Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Room USBC2 (Bounding Region = (7905mil, 9435mil, 8015mil, 9735mil) (False)
Rule Violations :0

Processing Rule : Room USBC1 (Bounding Region = (7925mil, 10010mil, 8025mil, 10300mil) (False)
Rule Violations :0

Processing Rule : Room FTDI (Bounding Region = (8330mil, 10020mil, 8570.788mil, 10250mil) (False)
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponent('R1')),(InComponent('R2')) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (All),(All) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponent('R24')),(InComponent('R26')) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponent('R23')),(InComponent('R25')) 
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 483
Waived Violations : 0
Time Elapsed        : 00:00:02