Libre Space Foundation / SIDLOC Transceiver - History

Add B2B connector

Fixes #62

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Fix net names, PN and add connector for FE

Fixes #57, #56, #58, #59, #52, #65

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Update BOM and create iBOM

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Fix TPS22950 footprint

Add the correct one for LSF-KiCAD library

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Add in-series resistors in FPGA-SPI

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Update in PCB from sidloc schematic

* Change SPI CLK of FPGA to L18
* Fixes #44 and #45

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Route power of FPGA and finalize I/Q connections

* Fixes #29 and #31
* Add TP in VIN 3.3V from external

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Add SPI routing of FPGA

* Route pull-up resistors of NOR flash
* Small fixes in AT86RF215, fixes #30
* Route pull-up and down resistors of JTAG

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Fix SPI_CLK connection

It had connected to CS

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Initial part placement

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>