Libre Space Foundation / SIDLOC Transceiver - History

Add more convinient test pads for RX clock LVDS

Fixes #74

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Expose TRX control pins to FPGA

Fixes #94

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Route FPGA pins to PQ9ish header

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Add load switch in PCB

Fixes #78

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Migrate to KiCAD 8

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Include in JTAG connector the debug pins

Fixes #72

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Route RX_IRQ to board to board connector

Fixes #70 and #75

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Migrate to KiCad 7, fixes #82

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Fix the position of B2B connector

* Small routing fixes in power section
* Remove wire to board connector from PCB

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>

Change FPGA 2V5 LDO to the bigger footprint variant.

Signed-off-by: Dimitrios Moustroufis <dimoustroufis@gmail.com>