Files
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded.PcbDoc
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded_panel.PcbDoc
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hardware / 1v0 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v0 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v0 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v0 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v0 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v0 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v0 / Schematics / 07_FPGA.SchDoc
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hardware / 1v0 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v0 / Schematics / 09_Misc.SchDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_panel.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_soldermask.PcbDoc
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hardware / 1v1 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v1 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v1 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v1 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v1 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v1 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v1 / Schematics / 07_FPGA.SchDoc
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hardware / 1v1 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v1 / Schematics / 09_Misc.SchDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded.PcbDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded_panel.PcbDoc
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hardware / 1v2 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v2 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v2 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v2 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v2 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v2 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v2 / Schematics / 07_FPGA.SchDoc
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hardware / 1v2 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v2 / Schematics / 09_Misc.SchDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_old.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_panel.PcbDoc
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hardware / 1v3 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v3 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v3 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v3 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v3 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v3 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v3 / Schematics / 07_FPGA.SchDoc
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hardware / 1v3 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v3 / Schematics / 09_Misc.SchDoc
Last update 1 year 7 months
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usama.bashir.cowlar@gmail.com
09_ExportGerbers.OutJob[OutputJobFile] Version=1.0 Caption= Description= VaultGUID= ItemGUID= ItemHRID= RevisionGUID= RevisionId= VaultHRID= AutoItemHRID= NextRevId= FolderGUID= LifeCycleDefinitionGUID= RevisionNamingSchemeGUID= [OutputGroup1] Name=ExportGerbers.OutJob Description= TargetOutputMedium=Folder Structure VariantName=[No Variations] VariantScope=1 CurrentConfigurationName= TargetPrinter=LBP6670 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 OutputMedium1=Print Job OutputMedium1_Type=Printer OutputMedium1_Printer= OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 OutputMedium2=PDF OutputMedium2_Type=Publish OutputMedium3=Folder Structure OutputMedium3_Type=GeneratedFiles OutputMedium4=Video OutputMedium4_Type=Multimedia OutputType1=Gerber OutputName1=Gerber Files OutputCategory1=Fabrication OutputDocumentPath1=LimeSDR_Mini_1v2_Rounded_panel.PcbDoc OutputVariantName1= OutputEnabled1=1 OutputEnabled1_OutputMedium1=0 OutputEnabled1_OutputMedium2=0 OutputEnabled1_OutputMedium3=1 OutputEnabled1_OutputMedium4=0 OutputDefault1=0 Configuration1_Name1=OutputConfigurationParameter1 Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmYSize=160000000|FilmXSize=200000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=True|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16777220~1,16777221~1,16777226~1,16777227~1,16777222~1,16777223~1,16777224~1,16777225~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908302~1,16908303~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False [PublishSettings] OutputFilePath2= ReleaseManaged2=1 OutputBasePath2=Project Outputs for LimeSDR_Mini_1v1 OutputPathMedia2= OutputPathMediaValue2= OutputPathOutputer2=[Output Type] OutputPathOutputerPrefix2= OutputPathOutputerValue2= OutputFileName2=ExportGerbers.PDF OutputFileNameMulti2= UseOutputNameForMulti2=1 OutputFileNameSpecial2= OpenOutput2=1 PromptOverwrite2=1 PublishMethod2=0 ZoomLevel2=50 FitSCHPrintSizeToDoc2=1 FitPCBPrintSizeToDoc2=1 GenerateNetsInfo2=1 MarkPins2=1 MarkNetLabels2=1 MarkPortsId2=1 GenerateTOC2=1 ShowComponentParameters2=1 GlobalBookmarks2=0 OutputFilePath3=E:\Saniok\Lime Micro\Lime PCBs\LimeSDR-PCIe_1v1\Altium Designer Design Files\Project Outputs for LimeSDR-PCIe_1v1\ ReleaseManaged3=1 OutputBasePath3=Project Outputs for LimeSDR_Mini_1v1 OutputPathMedia3= OutputPathMediaValue3= OutputPathOutputer3=[Output Type] OutputPathOutputerPrefix3= OutputPathOutputerValue3= OutputFileName3= OutputFileNameMulti3= UseOutputNameForMulti3=1 OutputFileNameSpecial3= OpenOutput3=1 OutputFilePath4= ReleaseManaged4=1 OutputBasePath4=Project Outputs for LimeSDR_Mini_1v1 OutputPathMedia4= OutputPathMediaValue4= OutputPathOutputer4=[Output Type] OutputPathOutputerPrefix4= OutputPathOutputerValue4= OutputFileName4= OutputFileNameMulti4= UseOutputNameForMulti4=1 OutputFileNameSpecial4= OpenOutput4=1 PromptOverwrite4=1 PublishMethod4=5 ZoomLevel4=50 FitSCHPrintSizeToDoc4=1 FitPCBPrintSizeToDoc4=1 GenerateNetsInfo4=1 MarkPins4=1 MarkNetLabels4=1 MarkPortsId4=1 MediaFormat4=Windows Media file (*.wmv,*.wma,*.asf) FixedDimensions4=1 Width4=352 Height4=288 MultiFile4=0 FramesPerSecond4=25 FramesPerSecondDenom4=1 AviPixelFormat4=7 AviCompression4=MP42 MS-MPEG4 V2 AviQuality4=100 FFmpegVideoCodecId4=13 FFmpegPixelFormat4=0 FFmpegQuality4=80 WmvVideoCodecName4=Windows Media Video V7 WmvQuality4=80 [GeneratedFilesSettings] RelativeOutputPath2= OpenOutputs2=1 RelativeOutputPath3=E:\Saniok\Lime Micro\Lime PCBs\LimeSDR-PCIe_1v1\Altium Designer Design Files\Project Outputs for LimeSDR-PCIe_1v1\ OpenOutputs3=1 AddToProject3=1 TimestampFolder3=0 UseOutputName3=0 OpenODBOutput3=0 OpenGerberOutput3=0 OpenNCDrillOutput3=0 OpenIPCOutput3=0 EnableReload3=0 RelativeOutputPath4= OpenOutputs4=1