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LPC43XX_Debugging.rst
LPC43XX_SGPIO_Configuration.rst
conf.py
enclosure_options.rst
expansion_interface.rst
external_clock_interface.rst
faq.rst
firmware_development_setup.rst
getting_help.rst
getting_started_hackrf_gnuradio.rst
hackrf_one.rst
hackrf_projects_mentions.rst
hackrf_sweep.rst
hackrfs_buttons.rst
hardware_components.rst
hardware_triggering.rst
index.rst
installing_hackrf_software.rst
jawbreaker.rst
libhackrf_api.rst
list_of_hardware_revisions.rst
opera_cake.rst
opera_cake_board_addressing.rst
opera_cake_faq.rst
opera_cake_hardware.rst
opera_cake_modes_of_operation.rst
opera_cake_port_configuration.rst
rf_shield_installation.rst
software_support.rst
tips_tricks.rst
troubleshooting.rst
updating_firmware.rst
opera_cake_hardware.rst
======== Hardware ======== Banks ~~~~~ The ports on Opera Cake are grouped in two banks (or "sides"), one on each end of the board. Bank A consists of ports A0 through A4 while bank B consists of ports B0 through B4. Ports ~~~~~ Opera Cake has two primary ports, A0 and B0, each of which can be switched to any of eight secondary ports, A1-A4 and B1-B4. Each primary port is always connected to one secondary port. By default, A0 is connected to A1, and B0 is connected to B1. It is not possible to connect both primary ports to secondary ports in the same bank at the same time. LEDs ~~~~ Port selections are indicated by LEDs next to each port's connector. Port A0 and the secondary port connected to A0 are indicated with a green LED. Port B0 and the secondary port connected to B0 are indicated with a yellow LED.
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