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raaannya
/ JaramilloAinara_SaadRanya_Grup5_Tardes_Portes - Circuit
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JaramilloAinara_SaadRanya_Grup5_Esquematic_Sessio2.kicad_pcb
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Revision
380c8e64
Layers
F.Cu
F.Adhes
F.Paste
F.SilkS
F.Mask
F.CrtYd
F.Fab
B.Cu
B.Adhes
B.Paste
B.SilkS
B.Mask
B.CrtYd
B.Fab
Dwgs.User
Cmts.User
Eco1.User
Eco2.User
Edge.Cuts
Margin
User.1
User.2
User.3
User.4
User.5
User.6
User.7
User.8
User.9
Footprints Front
Footprints Bottom
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Footprint Text Front
Footprint Text Back
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Pads Back
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