(WIP) Video memory concurrency - bank7 selector to address video or attribute RAM - found read and write data paths leading to video RAMs (F11, F12). - video RAMs CS generation.

(WIP) Other steps in video generation - Some notes regarding video attributes. - Found some stuck-at inputs.

(WIP) A long job in analog video output ! Read comments inside video_memory_management sheet for more informations. - Completed path between dot pattern output of character shift register and beam output transistor. - Found behavior of video attribute signals: blink, underline, stretch, hide. - Completed wiring of 28L22 ROM, which is involved in video attributes. - TODO: video_memory_management must be cleaned up, since schematics has grown outside sheet.

Discovered bank 0 + fixed wrong signals in video gen

Notes and minor fixes

DRAM: row/column mux, parity generator (partial), memory ICs

Missing signal in DRAM logic

Partial signal renaming

RAM addressing, including DRAM ras and cas

Z80 halt controls the RUN LED