Giulio / ceda-schematics - History

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    parallel port, which is absolutely not a centronic...
    by giuliof 2 years 2 months
    parallel port, which is absolutely not a centronics port
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    4b0dc395
    Found vsync frame signal for z80 + minors
    by giuliof 2 years 2 months
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    327238ba
    Added FDC sheet (WIP), added partial parallel port...
    by giuliof 2 years 3 months
    Added FDC sheet (WIP), added partial parallel port inout
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    e3d520d4
    IO addressing space multiplexing and small IO desc...
    by giuliof 2 years 4 months
    IO addressing space multiplexing and small IO description
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    48986839
    Reset circuit
    by giuliof 2 years 4 months
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    2caeed19
    Added some missing labels and references
    by giuliof 2 years 4 months
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    a4622d3b
    Video memory concurrency
    by giuliof 2 years 5 months
    Video memory concurrency

    - bank7 selector to address video or attribute RAM
    - found read and write data paths leading to video RAMs (F11, F12).
    - video RAMs CS generation.
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    ad45fbf9
    Upgraded to kicad 7
    by giuliof 2 years 7 months
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    4b1f0ec2
    Video memory bus and connections to Z80
    by giuliof 2 years 8 months
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    85ed74cb
    Some steps in bank switching and crtc circuits
    by giuliof 2 years 9 months
    Some steps in bank switching and crtc circuits

    - crtc pixel clock generator
    - 2k ram, enabling logic (heavily incomplete)
    - other 2k ram, annotation regarding data bus
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    a0055860
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