Create a project on CADLAB.io
Upload PCB design files
View schematics and board layouts
Visual schematic and layout diff
Design annotations
Organizations and project members
GitHub integration
GitHub Chrome extension
Giulio
/
ceda-schematics - History
Create Account
or
Sign In
Files
Branches
Tags
Releases
Discussions
Close Menu
Help
Scroll
Schematics refactoring:
by
giuliof
1 year 9 months
Schematics refactoring:
- New sheet reserved to video memory.
- Removed video memory parts inside video_generation.
- Removed video memory parts inside GPIO.
- Generic cleanup to keep all circuits inside each sheet.
Changes
Files
View circuit
997dae69
Discovered WE and OE signals for video memories, p...
by
giuliof
1 year 9 months
Discovered WE and OE signals for video memories, plus others
Changes
Files
View circuit
fd5dd944
CTC, serial clock and main clock
by
giuliof
1 year 9 months
Changes
Files
View circuit
7945c48c
parallel port, which is absolutely not a centronic...
by
giuliof
1 year 9 months
parallel port, which is absolutely not a centronics port
Changes
Files
View circuit
4b0dc395
Found vsync frame signal for z80 + minors
by
giuliof
1 year 9 months
Changes
Files
View circuit
327238ba
Added FDC sheet (WIP), added partial parallel port...
by
giuliof
1 year 10 months
Added FDC sheet (WIP), added partial parallel port inout
Changes
Files
View circuit
e3d520d4
IO addressing space multiplexing and small IO desc...
by
giuliof
1 year 11 months
IO addressing space multiplexing and small IO description
Changes
Files
View circuit
48986839
Reset circuit
by
giuliof
1 year 11 months
Changes
Files
View circuit
2caeed19
Added some missing labels and references
by
giuliof
1 year 11 months
Changes
Files
View circuit
a4622d3b
Video memory concurrency
by
giuliof
2 years 1 week
Video memory concurrency
- bank7 selector to address video or attribute RAM
- found read and write data paths leading to video RAMs (F11, F12).
- video RAMs CS generation.
Changes
Files
View circuit
ad45fbf9
1 of 100
››
Report a bug