Schematics refactoring: - New sheet reserved to video memory. - Removed video memory parts inside video_generation. - Removed video memory parts inside GPIO. - Generic cleanup to keep all circuits inside each sheet.

Discovered WE and OE signals for video memories, plus others

CTC, serial clock and main clock

parallel port, which is absolutely not a centronics port

Found vsync frame signal for z80 + minors

Added FDC sheet (WIP), added partial parallel port inout

IO addressing space multiplexing and small IO description

Reset circuit

Added some missing labels and references

Video memory concurrency - bank7 selector to address video or attribute RAM - found read and write data paths leading to video RAMs (F11, F12). - video RAMs CS generation.