Removed some dangling notes

Schematics refactoring: - New sheet reserved to video memory. - Removed video memory parts inside video_generation. - Removed video memory parts inside GPIO. - Generic cleanup to keep all circuits inside each sheet.

Discovered WE and OE signals for video memories, plus others

Something else in video generation sheet

CTC, serial clock and main clock

parallel port, which is absolutely not a centronics port

Found vsync frame signal for z80 + minors

Added FDC sheet (WIP), added partial parallel port inout

Serial communication interface

IO addressing space multiplexing and small IO description