Optimised Product Design / Test - History

fixes for edge clearance issue in v6...
...moved 'Margin' line to Eco2 layer
...(Margin interferes with copper in v6)
...changed Margin layer text from "Board Edge Placement Margin"
...now text "Board Edge Copper Margin"
changed schematic DRCs rules to reduce number...
...changed library symbol from warning to ignore (too many)
updated library ref for latest

changed to 0.20/0.20mm track/gap design rules match F.Fab text
...though F.Fab text previously had gap less than design rules
...picked new sensible based on Qucs studio calc 89.3ohm Zdiff

updated/changed settings for v6...
...project, schematic & pcb
...page settings, board setup, schematic setup & preferences
...includes setting new stackup feature to match F.Fab text
...fixed pcb F.Fab stackup text dimensions
...deleted pcb duplicate layer alignment target
...other misc sensible changes

updated footprints in from library
updated fp-lib-table for v6
updated library ref for updated footprints

converted kicad PCB layout to v6.0.0 (open and re-save)...
...re-annotated schematic, re-imported netlist to PCB
...NOTE: netlist import message "Remove H1 'exclude from BOM' fabrication attribute" for holes etc
pinned all of my symbol and footprint libs (new v6.0.0 feature)
updated library ref for updated v6.0.0 & 2022 titleblocks

added LOGO1 for optimised silkscreen logo
corrected titleblock reference, was still kbconsulting
re-imported to PCB and placed optimised logo
deleted silkscreen optimised text

modified template KiCAD project to use new OptimisedPD titleblock
changed PCB silkscreen text from KBconsulting to OptimisedPD
updated library ref to use new OptimisedPD titleblock

added Signal/GND/PWR names on layer stackup F.Fab drawing

added simple PCB stackup drawing on F.Fab layer
added dimensions on Dwgs.User as example, updated fab text to match

added fabrication PCB specification text to F.Fab layer
moved board, origins etc to give more space