test.sch-bak
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L pspice:R R1
U 1 1 5E481CFD
P 4550 2850
F 0 "R1" V 4345 2850 50  0000 C CNN
F 1 "100" V 4436 2850 50  0000 C CNN
F 2 "" H 4550 2850 50  0001 C CNN
F 3 "~" H 4550 2850 50  0001 C CNN
F 4 "R" H 4550 2850 50  0001 C CNN "Spice_Primitive"
F 5 "100" H 4550 2850 50  0001 C CNN "Spice_Model"
F 6 "Y" H 4550 2850 50  0001 C CNN "Spice_Netlist_Enabled"
	1    4550 2850
	0    1    1    0   
$EndComp
Wire Wire Line
	4300 2900 4300 2850
Wire Wire Line
	4800 2850 4950 2850
Wire Wire Line
	4950 3550 4950 2850
Connection ~ 4950 2850
Wire Wire Line
	4950 2850 5100 2850
Wire Wire Line
	5650 2950 5700 2950
Wire Wire Line
	5700 2950 5700 2750
Wire Wire Line
	5300 1700 5300 2450
$Comp
L pspice:0 #GND?
U 1 1 5E48C6C9
P 4800 2600
F 0 "#GND?" H 4800 2500 50  0001 C CNN
F 1 "0" H 4800 2689 50  0000 C CNN
F 2 "" H 4800 2600 50  0001 C CNN
F 3 "~" H 4800 2600 50  0001 C CNN
	1    4800 2600
	1    0    0    -1  
$EndComp
Wire Wire Line
	5100 2650 5100 2550
Wire Wire Line
	5100 2550 4800 2550
Wire Wire Line
	4800 2550 4800 2600
Text GLabel 4700 4050 1    50   Input ~ 0
in-
Text GLabel 5200 3300 0    50   Input ~ 0
in-
$Comp
L pspice:R R2
U 1 1 5E487A0A
P 5550 3550
F 0 "R2" V 5345 3550 50  0000 C CNN
F 1 "1k" V 5436 3550 50  0000 C CNN
F 2 "" H 5550 3550 50  0001 C CNN
F 3 "~" H 5550 3550 50  0001 C CNN
F 4 "R" H 5550 3550 50  0001 C CNN "Spice_Primitive"
F 5 "1k" H 5550 3550 50  0001 C CNN "Spice_Model"
F 6 "Y" H 5550 3550 50  0001 C CNN "Spice_Netlist_Enabled"
	1    5550 3550
	0    1    1    0   
$EndComp
Wire Wire Line
	4950 3550 5300 3550
Wire Wire Line
	5650 3100 5650 2950
$Comp
L Simulation_SPICE:OPAMP U1
U 1 1 5E4811F7
P 6350 1500
F 0 "U1" H 6694 1546 50  0000 L CNN
F 1 "OPAMP" H 6694 1455 50  0000 L CNN
F 2 "" H 6350 1500 50  0001 C CNN
F 3 "~" H 6350 1500 50  0001 C CNN
F 4 "Y" H 6350 1500 50  0001 L CNN "Spice_Netlist_Enabled"
F 5 "X" H 6350 1500 50  0001 L CNN "Spice_Primitive"
F 6 "TL084" H 6350 1500 50  0001 C CNN "Spice_Model"
F 7 "/home/thetheos/Downloads/TL084.301" H 6350 1500 50  0001 C CNN "Spice_Lib_File"
F 8 "1 2 4 5 3" H 6350 1500 50  0001 C CNN "Spice_Node_Sequence"
	1    6350 1500
	1    0    0    -1  
$EndComp
Wire Wire Line
	5200 3300 5300 3300
Wire Wire Line
	5300 3050 5300 3300
Wire Wire Line
	5650 3100 5800 3100
Wire Wire Line
	5800 3100 5800 3550
$Comp
L pspice:VSOURCE V2
U 1 1 5E49DB9F
P 3650 4450
F 0 "V2" H 3878 4496 50  0000 L CNN
F 1 "VSOURCE" H 3878 4405 50  0000 L CNN
F 2 "" H 3650 4450 50  0001 C CNN
F 3 "~" H 3650 4450 50  0001 C CNN
F 4 "V" H 3650 4450 50  0001 C CNN "Spice_Primitive"
F 5 "dc 15" H 3650 4450 50  0001 C CNN "Spice_Model"
F 6 "Y" H 3650 4450 50  0001 C CNN "Spice_Netlist_Enabled"
	1    3650 4450
	1    0    0    -1  
$EndComp
$Comp
L pspice:0 #GND?
U 1 1 5E49E4FB
P 3650 4950
F 0 "#GND?" H 3650 4850 50  0001 C CNN
F 1 "0" H 3650 5039 50  0000 C CNN
F 2 "" H 3650 4950 50  0001 C CNN
F 3 "~" H 3650 4950 50  0001 C CNN
	1    3650 4950
	1    0    0    -1  
$EndComp
Wire Wire Line
	3650 4950 3650 4750
$Comp
L pspice:VSOURCE V3
U 1 1 5E4A76FC
P 4700 4450
F 0 "V3" H 4928 4496 50  0000 L CNN
F 1 "VSOURCE" H 4928 4405 50  0000 L CNN
F 2 "" H 4700 4450 50  0001 C CNN
F 3 "~" H 4700 4450 50  0001 C CNN
F 4 "V" H 4700 4450 50  0001 C CNN "Spice_Primitive"
F 5 "dc -15" H 4700 4450 50  0001 C CNN "Spice_Model"
F 6 "Y" H 4700 4450 50  0001 C CNN "Spice_Netlist_Enabled"
	1    4700 4450
	1    0    0    -1  
$EndComp
$Comp
L pspice:0 #GND?
U 1 1 5E4A7702
P 4700 4950
F 0 "#GND?" H 4700 4850 50  0001 C CNN
F 1 "0" H 4700 5039 50  0000 C CNN
F 2 "" H 4700 4950 50  0001 C CNN
F 3 "~" H 4700 4950 50  0001 C CNN
	1    4700 4950
	1    0    0    -1  
$EndComp
Wire Wire Line
	4700 4950 4700 4750
$Comp
L pspice:VSOURCE V1
U 1 1 5E4A7F94
P 2350 4450
F 0 "V1" H 2578 4496 50  0000 L CNN
F 1 "VSOURCE" H 2578 4405 50  0000 L CNN
F 2 "" H 2350 4450 50  0001 C CNN
F 3 "~" H 2350 4450 50  0001 C CNN
F 4 "V" H 2350 4450 50  0001 C CNN "Spice_Primitive"
F 5 "sin(0 1 1k)" H 2350 4450 50  0001 C CNN "Spice_Model"
F 6 "Y" H 2350 4450 50  0001 C CNN "Spice_Netlist_Enabled"
	1    2350 4450
	1    0    0    -1  
$EndComp
$Comp
L pspice:0 #GND?
U 1 1 5E4A7F9A
P 2350 4950
F 0 "#GND?" H 2350 4850 50  0001 C CNN
F 1 "0" H 2350 5039 50  0000 C CNN
F 2 "" H 2350 4950 50  0001 C CNN
F 3 "~" H 2350 4950 50  0001 C CNN
	1    2350 4950
	1    0    0    -1  
$EndComp
Wire Wire Line
	2350 4950 2350 4750
Wire Wire Line
	4700 4150 4700 4050
Text GLabel 3650 4050 1    50   Input ~ 0
in+
Wire Wire Line
	3650 4150 3650 4050
Text GLabel 5300 1700 1    50   Input ~ 0
in+
Wire Wire Line
	2350 2900 2350 4150
Wire Wire Line
	2350 2900 4300 2900
$Comp
L Simulation_SPICE:OPAMP U?
U 1 1 5E4AF3DD
P 5400 2750
F 0 "U?" H 5744 2796 50  0000 L CNN
F 1 "OPAMP" H 5744 2705 50  0000 L CNN
F 2 "" H 5400 2750 50  0001 C CNN
F 3 "~" H 5400 2750 50  0001 C CNN
F 4 "Y" H 5400 2750 50  0001 L CNN "Spice_Netlist_Enabled"
F 5 "X" H 5400 2750 50  0001 L CNN "Spice_Primitive"
F 6 "TL084" H 5400 2750 50  0001 C CNN "Spice_Model"
F 7 "1 2 4 5 3" H 5400 2750 50  0001 C CNN "Spice_Node_Sequence"
F 8 "/home/thetheos/Downloads/TL084.301" H 5400 2750 50  0001 C CNN "Spice_Lib_File"
	1    5400 2750
	1    0    0    -1  
$EndComp
$EndSCHEMATC