Files
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PCB ESP32 / bak / PCB1.PcbDoc
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PCB ESP32 / bak / Sheet1.SchDoc
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PCB ESP32 / bak / Sheet2.SchDoc
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PCB ESP32 / Control_Board / Conns.SchDoc
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PCB ESP32 / Control_Board / Control_Board.PcbDoc
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PCB ESP32 / Control_Board / PCB2.PcbDoc
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PCB ESP32 / Control_Board / Circuit Maker / Control_Board.PcbDoc
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PCB ESP32 / Main / PCB2.PcbDoc
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PCB ESP32 / Main / Sheet1.SchDoc
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PCB ESP32 / Main / Sheet2.SchDoc
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PCB ESP32 / Main / Sheet3.SchDoc
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PCB ESP32 / Main / Sheet4.SchDoc
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PCB ESP32 / Main / Sheet4_Matrix.SchDoc
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PCB ESP32 / Matrix / PCB1.PcbDoc
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PCB ESP32 / Matrix2 / PCB2.PcbDoc
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PCB ESP32 / Panel / panel.PcbDoc
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PCB ESP32 / refs / OnOnfre_DevBoard_rev4.sch
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PCB ESP32 / Resistor Patch / 1 / ResistorPatch1.PcbDoc
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PCB ESP32 / Resistor Patch / 1 / ResistorPatch1.SchDoc
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PCB ESP32 / Resistor Patch / 2 / ResistorPatch2.PcbDoc
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PCB ESP32 / Resistor Patch / 2 / ResistorPatch2.SchDoc
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PCB ESP32 / SOT223 Patch / PCB1.PcbDoc
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PCB ESP32 / SOT223 Patch / Sheet1.SchDoc
Last update 4 years 4 months
by
Afonso Muralha
| FilesPCB ESP32Control_BoardProject Outputs for Control_Board | |
|---|---|
| .. | |
| Control_Board.nsx | |
| Control_Board.sim | |
| Design Rule Check - Control_Board.drc | |
| Design Rule Check - Control_Board.html | |
| Status Report.Txt |
Status Report.TxtOutput: Mixed Sim Type : AdvSimNetlist From : Project [Control_Board.PrjPcb] Generated File[Control_Board.nsx] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 00:38:19 On 26/01/2019