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Last update 4 years 5 months by Afonso Muralha
FilesPCB ESP32Control_BoardProject Outputs for Control_Board
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Control_Board.nsx
Control_Board.sim
Design Rule Check - Control_Board.drc
Design Rule Check - Control_Board.html
Status Report.Txt
Control_Board.nsx
Control_Board *SPICE Netlist generated by Advanced Sim server on 26/01/2019 00:38:18 *Schematic Netlist: R1 0 NetR1_2 100k R2 0 NetR2_2 10k R3 NetR3_1 Vbat 100k R4 0 NetR3_1 100k R5 VBus 0 10k R6 0 SDB 100k R7 NetC8_2 0 1k R8 VCC3V3 RESET 10k R9 RTS NetQ1_1 10k R10 DTR NetQ2_1 10k R11 0 NetR11_2 4.7k R12 VCC3V3 SCL_ESP 4.7k R13 ESP_SW3 VCC3V3 10k R14 NetR14_1 NetC12_2 1k R15 ESP_SW2 VCC3V3 10k R16 VCC3V3 SDA_ESP 4.7k R17 NetC13_2 0 1k R18 NetC14_2 0 1k R19 NetC15_2 0 1k R20 NetC16_2 0 1k R21 ESP_SW1 VCC3V3 10k R22 NetR22_1 NetAMS1117_3 1k .SAVE 0 DTR ESP_SW1 ESP_SW2 ESP_SW3 NetAMS1117_3 NetC12_2 NetC13_2 NetC14_2 .SAVE NetC15_2 NetC16_2 NetC8_2 NetQ1_1 NetQ2_1 NetR1_2 NetR11_2 NetR14_1 NetR2_2 .SAVE NetR22_1 NetR3_1 RESET RTS SCL_ESP SDA_ESP SDB Vbat VBus VCC3V3 @R1[i] @R10[i] .SAVE @R11[i] @R12[i] @R13[i] @R14[i] @R15[i] @R16[i] @R17[i] @R18[i] @R19[i] @R2[i] .SAVE @R20[i] @R21[i] @R22[i] @R3[i] @R4[i] @R5[i] @R6[i] @R7[i] @R8[i] @R9[i] @R1[p] .SAVE @R10[p] @R11[p] @R12[p] @R13[p] @R14[p] @R15[p] @R16[p] @R17[p] @R18[p] @R19[p] .SAVE @R2[p] @R20[p] @R21[p] @R22[p] @R3[p] @R4[p] @R5[p] @R6[p] @R7[p] @R8[p] @R9[p] .PROBE TRAN NetR22_1 .PROBE OP NetR22_1 *Selected Circuit Analyses: .TRAN 2E-8 5E-6 0 2E-8 .OP .END
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