Files

Hedgehog.pro
update=Mon 13 Mai 2019 00:28:18 CEST version=1 last_client=kicad [cvpcb] version=1 NetIExt=net [general] version=1 [eeschema] version=1 LibDir= [pcbnew] version=1 PageLayoutDescrFile=pageLayout.kicad_wks LastNetListRead= CopperLayerCount=4 BoardThickness=1.6 AllowMicroVias=0 AllowBlindVias=0 RequireCourtyardDefinitions=0 ProhibitOverlappingCourtyards=0 MinTrackWidth=0.2 MinViaDiameter=0.3 MinViaDrill=0.3 MinMicroViaDiameter=0.2 MinMicroViaDrill=0.09999999999999999 MinHoleToHole=0.2 TrackWidth1=0.2 TrackWidth2=0.3 TrackWidth3=0.5 TrackWidth4=1 TrackWidth5=2 ViaDiameter1=0.6 ViaDrill1=0.4 dPairWidth1=0.2 dPairGap1=0.25 dPairViaGap1=0.25 SilkLineWidth=0.15 SilkTextSizeV=1 SilkTextSizeH=1 SilkTextSizeThickness=0.15 SilkTextItalic=0 SilkTextUpright=1 CopperLineWidth=0.2 CopperTextSizeV=1.5 CopperTextSizeH=1.5 CopperTextThickness=0.3 CopperTextItalic=0 CopperTextUpright=1 EdgeCutLineWidth=0.15 CourtyardLineWidth=0.05 OthersLineWidth=0.15 OthersTextSizeV=1 OthersTextSizeH=1 OthersTextSizeThickness=0.15 OthersTextItalic=0 OthersTextUpright=1 SolderMaskClearance=0.05 SolderMaskMinWidth=0.05 SolderPasteClearance=0 SolderPasteRatio=-0 [pcbnew/Layer.F.Cu] Name=F.Cu Type=2 [pcbnew/Layer.In1.Cu] Name=In1.Cu Type=2 [pcbnew/Layer.In2.Cu] Name=In2.Cu Type=2 [pcbnew/Layer.B.Cu] Name=B.Cu Type=2 [schematic_editor] version=1 PageLayoutDescrFile=pageLayout.kicad_wks PlotDirectoryName= SubpartIdSeparator=0 SubpartFirstId=65 NetFmtName= SpiceAjustPassiveValues=0 LabSize=60 ERC_TestSimilarLabels=1

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Hedgehog.kicad_pcb
3a3eee28
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