Design Rule Check - powerPCB.drc
Protel Design System Design Rule Check
PCB File : C:\Users\Dylan\Desktop\opbots\Opbots-Ryan-135e40c805ce92f78853d1e4837bdf91bd48c00b\Opbots-Ryan-135e40c805ce92f78853d1e4837bdf91bd48c00b\ARM_POWER\powerPCB.PcbDoc
Date     : 7/19/2021
Time     : 4:59:32 PM

Processing Rule : Clearance Constraint (Gap=8mil) (OnLayer('Top Layer')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (OnLayer('Bottom Layer')),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=3.5mil) (Max=100mil) (Preferred=15mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=3mil) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=7.874mil) (Max=248.031mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=3.937mil) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=3.937mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Board Clearance Constraint (Gap=0mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:02