Capstone Team / Transceiver - History

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    Added gbr zip file and vias underneath exposed pads for CDR, Laser Driver, and Clock Generator
    by alexg-jpg 4 years 2 weeks
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    0b8caacf
    Connected all remaining unconnected nets
    by alexg-jpg 4 years 2 weeks
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    3ce81f2c
    Power routes finished
    by Yinxin He 4 years 2 weeks
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    a5993f8a
    microcontroller connected
    by Yinxin He 4 years 2 weeks
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    75f642c5
    backup before update
    by Yinxin He 4 years 2 weeks
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    ca002dee
    layout
    by Yinxin He 4 years 2 weeks
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    ea7b85f1
    add first draft of digital layout
    by 李明月 4 years 2 weeks
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    0d8ea0ce
    Added missing caps in schematic. Regenerated netlist. Completed first iteration of layout for analog/optical
    by alexg-jpg 4 years 2 weeks
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    56ce1788
    Updated microcontroler connection
    by Yinxin He 4 years 3 weeks
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    b7890e8f
    VEE regulator added
    by Yinxin He 4 years 3 weeks
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    d92abc48
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