Glasgow Embedded / Glasgow - History

gateware.boneless: nicer naming for memory signals. NFC.

gateware.boneless: split JAL and JR handling (-1 LUT).

gateware.boneless: ensure sensible names in Verilog output.

gateware.boneless: use non-transparent read port (-47 LUT, -17 DFF).

Before:
Number of wires: 462
Number of wire bits: 899
Number of public wires: 44
Number of public wire bits: 386
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 717
SB_CARRY 93
SB_DFF 1
SB_DFFE 1
SB_DFFESR 80
SB_DFFSR 36
SB_LUT4 505
SB_RAM40_4K 1

After:
Number of wires: 416
Number of wire bits: 868
Number of public wires: 45
Number of public wire bits: 402
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 670
SB_CARRY 93
SB_DFF 1
SB_DFFE 1
SB_DFFESR 80
SB_DFFSR 19
SB_LUT4 475
SB_RAM40_4K 1

gateware.boneless: use split memory ports, if any (-20 LUT).

Before:
Number of wires: 475
Number of wire bits: 919
Number of public wires: 44
Number of public wire bits: 386
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 737
SB_CARRY 93
SB_DFF 9
SB_DFFE 1
SB_DFFESR 80
SB_DFFSR 36
SB_LUT4 517
SB_RAM40_4K 1

After:
Number of wires: 462
Number of wire bits: 899
Number of public wires: 44
Number of public wire bits: 386
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 717
SB_CARRY 93
SB_DFF 1
SB_DFFE 1
SB_DFFESR 80
SB_DFFSR 36
SB_LUT4 505
SB_RAM40_4K 1

gateware.boneless: allow selecting external bus or GPOs for export.

iCE40UP5K doesn't have enough pins for the external bus.

revC: minor beauty tweaks to routing, redo USB 2.0 diffpairs

I used the same specs as for LVDS (even though those are 100Ω and USB
2.0 is supposed to be 90Ω, it's short enough it won't matter and we're
not doing tight enough fab control for it to make a difference)