Glasgow Embedded / Glasgow - History

revC: minor nudging and tweaking to improve silkscreen around reg area

revC: reposition fiducials, add a third corner, add more for FX2, FPGA

revC: simplify VUSB routing, move input cap to top layer, double vias

revC: remove additional I/O port silkscreen markings

revC: connect Port A 4,6 to extra FPGA I/Os as well as GBUFs

This allows flexibility in using the PLL with or without the pins as
clock inputs.

arch.boneless: clarify when C/O flags end up in undefined state.