Glasgow Embedded / Glasgow - History

revC1: note 10/12-bit ADC/DACs as alternates

Also minor positioning adjustment to the schematic

Closes: #104

revC0: export production files

Closes: #98

revC1: make Sync pull-up 1K

Closes: #102

revC1: fix old value/datasheet for PCA6408, style fixes

revC1: replace pulls with PCA6408A and remove shifters

applet.audio.yamaha_opl: implement WAV export.

This also makes the applet more efficient by performing the unsigned-
to-signed conversion with numpy, or avoiding a roundtrip, in case
libsamplerate is used.

Revert "gateware.fx2: re-register FX2 outputs. (UPDATE FIRMWARE.)"

This reverts commit 684e45808f4627d91b31a3d32bb18c1bc05b06a4.

That commit broke the audio-yamaha-opl3 applet *badly*. It is not
clear exactly what the issue is but the correct fix is likely to
stop relying on flags to detect a buffer full condition and instead
use a local counter on the FPGA side, and use flags only to detect
the out of buffers condition.

target.hardware: fix system clock constraint.

Something changed in Yosys and/or nextpnr and now they look for
the constraint on por_clk, not sys_clk, and silently ignore the one
on sys_clk. We need to fix that as well sometime...