gateware.boneless: allow selecting external bus or GPOs for export. iCE40UP5K doesn't have enough pins for the external bus.

gateware.boneless: add Verilog export.

gateware.boneless: add tests for C-class opcodes.

revC: minor beauty tweaks to routing, redo USB 2.0 diffpairs I used the same specs as for LVDS (even though those are 100Ω and USB 2.0 is supposed to be 90Ω, it's short enough it won't matter and we're not doing tight enough fab control for it to make a difference)

revC: remove spurious square in F.Paste

gateware.boneless: implement JAL and JR.

gateware.boneless: implement LDI and STI.

gateware.boneless: implement ADDI.

gateware.boneless: implement MOVH, MOVL and MOVA.

Move three refspecs 0.1mm for symmetry against other side.