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    revC: connect Port A 4,6 to extra FPGA I/Os as wel...
    by Hector Martin 6 years 6 months
    revC: connect Port A 4,6 to extra FPGA I/Os as well as GBUFs

    This allows flexibility in using the PLL with or without the pins as
    clock inputs.
    Changes
    Files
    3489eb26
    revC: update incorrect comment re: Vbus threshold
    by Hector Martin 6 years 6 months
    Changes
    Files
    6423d6e7
    arch.boneless: add ROL alias and ROR pseudo.
    by whitequark 6 years 6 months
    Changes
    Files
    226f6cbd
    arch.boneless: clarify when C/O flags end up in un...
    by whitequark 6 years 6 months
    arch.boneless: clarify when C/O flags end up in undefined state.
    Changes
    Files
    9ac4020d
    gateware.boneless: nicer naming for memory signals...
    by whitequark 6 years 6 months
    gateware.boneless: nicer naming for memory signals. NFC.
    Changes
    Files
    b922f7ef
    gateware.boneless: split JAL and JR handling (-1 L...
    by whitequark 6 years 6 months
    gateware.boneless: split JAL and JR handling (-1 LUT).
    Changes
    Files
    2d0123c6
    gateware.boneless: fix indentation. NFC.
    by whitequark 6 years 6 months
    Changes
    Files
    157f613f
    gateware.boneless: ensure sensible names in Verilo...
    by whitequark 6 years 6 months
    gateware.boneless: ensure sensible names in Verilog output.
    Changes
    Files
    b6ef81b6
    gateware.boneless: use non-transparent read port (...
    by whitequark 6 years 6 months
    gateware.boneless: use non-transparent read port (-47 LUT, -17 DFF).

    Before:
    Number of wires: 462
    Number of wire bits: 899
    Number of public wires: 44
    Number of public wire bits: 386
    Number of memories: 0
    Number of memory bits: 0
    Number of processes: 0
    Number of cells: 717
    SB_CARRY 93
    SB_DFF 1
    SB_DFFE 1
    SB_DFFESR 80
    SB_DFFSR 36
    SB_LUT4 505
    SB_RAM40_4K 1

    After:
    Number of wires: 416
    Number of wire bits: 868
    Number of public wires: 45
    Number of public wire bits: 402
    Number of memories: 0
    Number of memory bits: 0
    Number of processes: 0
    Number of cells: 670
    SB_CARRY 93
    SB_DFF 1
    SB_DFFE 1
    SB_DFFESR 80
    SB_DFFSR 19
    SB_LUT4 475
    SB_RAM40_4K 1
    Changes
    Files
    cb4b55b9
    gateware.boneless: use split memory ports, if any ...
    by whitequark 6 years 6 months
    gateware.boneless: use split memory ports, if any (-20 LUT).

    Before:
    Number of wires: 475
    Number of wire bits: 919
    Number of public wires: 44
    Number of public wire bits: 386
    Number of memories: 0
    Number of memory bits: 0
    Number of processes: 0
    Number of cells: 737
    SB_CARRY 93
    SB_DFF 9
    SB_DFFE 1
    SB_DFFESR 80
    SB_DFFSR 36
    SB_LUT4 517
    SB_RAM40_4K 1

    After:
    Number of wires: 462
    Number of wire bits: 899
    Number of public wires: 44
    Number of public wire bits: 386
    Number of memories: 0
    Number of memory bits: 0
    Number of processes: 0
    Number of cells: 717
    SB_CARRY 93
    SB_DFF 1
    SB_DFFE 1
    SB_DFFESR 80
    SB_DFFSR 36
    SB_LUT4 505
    SB_RAM40_4K 1
    Changes
    Files
    b8c49398
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