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    Minor silkscreen cleanups.
    by awygle 7 years 5 days
    Changes
    Files
    6cb4f997
    Add edge-rate control resistors on FPGA side.
    by awygle 7 years 5 days
    Changes
    Files
    7c3203c1
    Add USB protection IC.
    by awygle 7 years 3 weeks
    Changes
    Files
    369968e5
    Rename FIFO parameter early_in to streaming and fu...
    by whitequark 7 years 1 month
    Rename FIFO parameter early_in to streaming and fully disable pktend.
    Changes
    Files
    a89f5a22
    Fix data corruption writing last byte available in...
    by whitequark 7 years 1 month
    Fix data corruption writing last byte available in an FX2 IN FIFO.
    Changes
    Files
    8f572d80
    Add early_in parameter to get_in_fifo to disable a...
    by whitequark 7 years 1 month
    Add early_in parameter to get_in_fifo to disable automatic OUTPKTEND.

    Also fix a typo.
    Changes
    Files
    e6c33901
    Allow applets to request FIFOs instead of hardcodi...
    by whitequark 7 years 1 month
    Allow applets to request FIFOs instead of hardcoding count and depth.

    This also makes asynchronous FIFOs actually work.

    Fixes #58.
    Changes
    Files
    9dff8520
    Add `--force` argument to `glasgow run` to force l...
    by whitequark 7 years 1 month
    Add `--force` argument to `glasgow run` to force load bitstream.

    This helps if the bitstream is hung. Ideally we should reuse CDONE
    as design reset and reset the applet, but that would make timings
    worse and is much more complex.
    Changes
    Files
    009bf0d1
    Add `--type verilog` to `glasgow build`.
    by whitequark 7 years 1 month
    Changes
    Files
    daeed950
    Allow retargeting applets to different port and pi...
    by whitequark 7 years 1 month
    Allow retargeting applets to different port and pins.

    Fixes #57.
    Changes
    Files
    7b10caa7
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