Minor silkscreen cleanups.

Add edge-rate control resistors on FPGA side.

Add USB protection IC.

Rename FIFO parameter early_in to streaming and fully disable pktend.

Fix data corruption writing last byte available in an FX2 IN FIFO.

Add early_in parameter to get_in_fifo to disable automatic OUTPKTEND. Also fix a typo.

Allow applets to request FIFOs instead of hardcoding count and depth. This also makes asynchronous FIFOs actually work. Fixes #58.

Add `--force` argument to `glasgow run` to force load bitstream. This helps if the bitstream is hung. Ideally we should reuse CDONE as design reset and reset the applet, but that would make timings worse and is much more complex.

Add `--type verilog` to `glasgow build`.

Allow retargeting applets to different port and pins. Fixes #57.