Add fabrication outputs for revB. This also fixes bad positioning on fab layers and wrong 3D package for the Cypress chip. Resistor network MPN is still TBD.

Update MPN on schematic.

Update revision on schematic.

Implement an UART applet.

Implement asynchronous USB I/O via get_port(async=True).

Use upstream QFN footprint for Cypress part Closes #61.

Reduce SYNC pull-up value to 390 Ohms. Closes #51.

Use upstream FPGA symbol

Add a TRACE log level and log all port and USB I/O using it.

Update libfx2.