manual: intro: add link to `memory-24x`.
by whitequark 2 days 1 hour
a321f69a
applet.interface.swd_probe: add API docs to manual...
by whitequark 2 days 1 hour
applet.interface.swd_probe: add API docs to manual.
28216bdd
applet.interface.swd_probe: add DPv2 JTAG-to-SWD s...
by whitequark 2 days 1 hour
applet.interface.swd_probe: add DPv2 JTAG-to-SWD switching sequence.
797986e4
Revert "applet.bridge.probe_rs: support included i...
by whitequark 2 days 2 hours
Revert "applet.bridge.probe_rs: support included in probe-rs release!"

This reverts commit 96c2a7fb8f3622af8c7d4dff8102ed278535587f.
b49d9c5f
applet.bridge.probe_rs: support included in probe-...
by whitequark 2 days 3 hours
applet.bridge.probe_rs: support included in probe-rs release!
96c2a7fb
applet.sensor.sen5x: add delay before I2C reads
by Mike Walters 2 days 13 hours
applet.sensor.sen5x: add delay before I2C reads

The datasheet lists a worst-case command execution time of 20 ms for all
read commands, but doesn't clearly explain what to do with that information.

However, the device NACKs an I2C read if it's issued too soon after the
command-address write. So, this delays all reads by that execution time
and seems to be stable now.
8dc447f5
applet.sensor.sen5x: set @miek as code owner.
by whitequark 2 days 17 hours
b014a4b2
applet.sensor.sen5x: migrate to V2 API and add tes...
by whitequark 4 days 12 hours
applet.sensor.sen5x: migrate to V2 API and add test.
e353846f
applet.sensor.scd30: remove unreachable code.
by whitequark 4 days 12 hours
b38b4fb5
gateware.fx2_crossbar: flush IN FIFO once per micr...
by whitequark 4 days 2 hours
gateware.fx2_crossbar: flush IN FIFO once per microframe.

This eliminates a common pitfall for applet authors, where by default
the IN FIFO is flushed too often, and very small packets clog the FX2
buffers, causing buffer overflows and data loss. With this change, so
long as the host polls the device once per microframe (with XHCI hosts,
this can happen even more than once), there will never be a case where
an FX2 buffer isn't available, unless the bus is very heavily loaded
with other traffic.

There are two cases where more control over flushing is desired.

First, in request/response style protocols, it is useful to flush
the IN FIFO once the OUT FIFO is empty, since this reduces time spent
waiting for responses. This can significantly improve `probe-rs`
throughput, and is still used in that applet.

Second, an applet that produces a stream of data quickly enough that it
would be sent as a sequence of maximum-length packets may still need
this data to arrive at the host promptly. This can be an issue with
`uart` applet at high baud rates and duty cycles. It is not fixed in
this commit.

The throughput and latency when configured to flush implicitly, as
measured by the `benchmark` applet, are essentially unchanged;
the latency should be worse by ~125 µs (worst case), but this change
is comparable to noise.

All of the V2 applets that used to use explicit flush have been updated
to use autoflush where applicable; only `probe-rs` continues to use
explicit flush.

Fixes #263.
Fixes #794.
73a91184
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