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Last update 3 years 10 months
by
Benjamin Maxwell
Voltage Sensing Bank.PrjPCBStructureRecord=TopLevelDocument|FileName=Voltage Sensing Bank Block Diagram.SchDoc Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=ADC Buffer|SchDesignator=ADC Buffer|FileName=File Name|SymbolType=Normal|RawFileName=File Name|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=ADC Module|SchDesignator=ADC Module|FileName=ADAR7251.SchDoc|SymbolType=Normal|RawFileName=ADAR7251.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=Ethernet to SPI interface|SchDesignator=Ethernet to SPI interface|FileName=File Name|SymbolType=Normal|RawFileName=File Name|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=Gain Control (VGA)|SchDesignator=Gain Control (VGA)|FileName=File Name|SymbolType=Normal|RawFileName=File Name|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=POE |SchDesignator=POE |FileName=File Name|SymbolType=Normal|RawFileName=File Name|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=Voltage Sensing Bank Block Diagram.SchDoc|Designator=Voltage Input Pins|SchDesignator=Voltage Input Pins|FileName=File Name|SymbolType=Normal|RawFileName=File Name|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=