Files

copied
Last update 3 years 8 months by X3N0
FilesIVL_Watch
..
BC847BV,315
DRV8838DSGR
ESwitch.pretty
EVP-BB0AAB000
OPT3001DNPRQ1
VFD.pretty
footprint_L80RE
x3n0.pretty
._045138008100858_.lib
._IVL_Watch.pro
._MAX98357AETE_T.lib
._TBL005A-500-02GY-2WT.lib
._USB4085-GF-A_REVA.lib
045138008100858_.dcm
045138008100858_.lib
Audio.bak
Audio.sch
Audio.sch-bak
IVL_Watch
IVL_Watch-cache.lib
IVL_Watch-rescue.dcm
IVL_Watch-rescue.lib
IVL_Watch.bak
IVL_Watch.kicad_pcb
IVL_Watch.kicad_pcb-bak
IVL_Watch.net
IVL_Watch.pdf
IVL_Watch.pro
IVL_Watch.sch
IVL_Watch.sch-bak
IVL_Watch.xml
L80RE-M37.lib
MAX98357AETE_T.dcm
MAX98357AETE_T.lib
RTC.sch
RTC.sch-bak
TBL005A-500-02GY-2WT.dcm
TBL005A-500-02GY-2WT.lib
USB4085-GF-A_REVA.dcm
USB4085-GF-A_REVA.lib
VFD.lib
VFD_Display.bak
VFD_Display.sch
VFD_Display.sch-bak
_autosave-IVL_Watch.sch
file5EFECD14.sch
file5EFECD14.sch-bak
fp-info-cache
fp-lib-table
sym-lib-table
x3n0_Lib.bck
x3n0_Lib.dcm
x3n0_Lib.lib
IVL_Watch.pro
update=Do 25 Feb 2021 15:45:49 CET version=1 last_client=kicad [general] version=1 RootSch= BoardNm= [cvpcb] version=1 NetIExt=net [eeschema] version=1 LibDir= [eeschema/libraries] [schematic_editor] version=1 PageLayoutDescrFile= PlotDirectoryName= SubpartIdSeparator=0 SubpartFirstId=65 NetFmtName=Pcbnew SpiceAjustPassiveValues=0 LabSize=50 ERC_TestSimilarLabels=1 [pcbnew] version=1 PageLayoutDescrFile= LastNetListRead=IVL_Watch.net CopperLayerCount=2 BoardThickness=1.6002 AllowMicroVias=0 AllowBlindVias=0 RequireCourtyardDefinitions=0 ProhibitOverlappingCourtyards=1 MinTrackWidth=0.09999999999999999 MinViaDiameter=0.45 MinViaDrill=0.2 MinMicroViaDiameter=0.2 MinMicroViaDrill=0.09999999999999999 MinHoleToHole=0.2 TrackWidth1=0.25 TrackWidth2=0.1 TrackWidth3=0.2 TrackWidth4=0.5 ViaDiameter1=0.8 ViaDrill1=0.4 ViaDiameter2=0.45 ViaDrill2=0.2 ViaDiameter3=0.8 ViaDrill3=0.4 dPairWidth1=0.25 dPairGap1=0.25 dPairViaGap1=0.25 SilkLineWidth=0.12 SilkTextSizeV=1 SilkTextSizeH=1 SilkTextSizeThickness=0.15 SilkTextItalic=0 SilkTextUpright=1 CopperLineWidth=0.2 CopperTextSizeV=1.5 CopperTextSizeH=1.5 CopperTextThickness=0.3 CopperTextItalic=0 CopperTextUpright=1 EdgeCutLineWidth=0.05 CourtyardLineWidth=0.05 OthersLineWidth=0.15 OthersTextSizeV=1 OthersTextSizeH=1 OthersTextSizeThickness=0.15 OthersTextItalic=0 OthersTextUpright=1 SolderMaskClearance=0 SolderMaskMinWidth=0.09999999999999999 SolderPasteClearance=0 SolderPasteRatio=-0 [pcbnew/Layer.F.Cu] Name=Front Type=0 Enabled=1 [pcbnew/Layer.In1.Cu] Name=In1.Cu Type=0 Enabled=0 [pcbnew/Layer.In2.Cu] Name=In2.Cu Type=0 Enabled=0 [pcbnew/Layer.In3.Cu] Name=In3.Cu Type=0 Enabled=0 [pcbnew/Layer.In4.Cu] Name=In4.Cu Type=0 Enabled=0 [pcbnew/Layer.In5.Cu] Name=In5.Cu Type=0 Enabled=0 [pcbnew/Layer.In6.Cu] Name=In6.Cu Type=0 Enabled=0 [pcbnew/Layer.In7.Cu] Name=In7.Cu Type=0 Enabled=0 [pcbnew/Layer.In8.Cu] Name=In8.Cu Type=0 Enabled=0 [pcbnew/Layer.In9.Cu] Name=In9.Cu Type=0 Enabled=0 [pcbnew/Layer.In10.Cu] Name=In10.Cu Type=0 Enabled=0 [pcbnew/Layer.In11.Cu] Name=In11.Cu Type=0 Enabled=0 [pcbnew/Layer.In12.Cu] Name=In12.Cu Type=0 Enabled=0 [pcbnew/Layer.In13.Cu] Name=In13.Cu Type=0 Enabled=0 [pcbnew/Layer.In14.Cu] Name=In14.Cu Type=0 Enabled=0 [pcbnew/Layer.In15.Cu] Name=In15.Cu Type=0 Enabled=0 [pcbnew/Layer.In16.Cu] Name=In16.Cu Type=0 Enabled=0 [pcbnew/Layer.In17.Cu] Name=In17.Cu Type=0 Enabled=0 [pcbnew/Layer.In18.Cu] Name=In18.Cu Type=0 Enabled=0 [pcbnew/Layer.In19.Cu] Name=In19.Cu Type=0 Enabled=0 [pcbnew/Layer.In20.Cu] Name=In20.Cu Type=0 Enabled=0 [pcbnew/Layer.In21.Cu] Name=In21.Cu Type=0 Enabled=0 [pcbnew/Layer.In22.Cu] Name=In22.Cu Type=0 Enabled=0 [pcbnew/Layer.In23.Cu] Name=In23.Cu Type=0 Enabled=0 [pcbnew/Layer.In24.Cu] Name=In24.Cu Type=0 Enabled=0 [pcbnew/Layer.In25.Cu] Name=In25.Cu Type=0 Enabled=0 [pcbnew/Layer.In26.Cu] Name=In26.Cu Type=0 Enabled=0 [pcbnew/Layer.In27.Cu] Name=In27.Cu Type=0 Enabled=0 [pcbnew/Layer.In28.Cu] Name=In28.Cu Type=0 Enabled=0 [pcbnew/Layer.In29.Cu] Name=In29.Cu Type=0 Enabled=0 [pcbnew/Layer.In30.Cu] Name=In30.Cu Type=0 Enabled=0 [pcbnew/Layer.B.Cu] Name=Back Type=0 Enabled=1 [pcbnew/Layer.B.Adhes] Enabled=0 [pcbnew/Layer.F.Adhes] Enabled=0 [pcbnew/Layer.B.Paste] Enabled=1 [pcbnew/Layer.F.Paste] Enabled=1 [pcbnew/Layer.B.SilkS] Enabled=1 [pcbnew/Layer.F.SilkS] Enabled=1 [pcbnew/Layer.B.Mask] Enabled=1 [pcbnew/Layer.F.Mask] Enabled=1 [pcbnew/Layer.Dwgs.User] Enabled=0 [pcbnew/Layer.Cmts.User] Enabled=0 [pcbnew/Layer.Eco1.User] Enabled=0 [pcbnew/Layer.Eco2.User] Enabled=0 [pcbnew/Layer.Edge.Cuts] Enabled=1 [pcbnew/Layer.Margin] Enabled=1 [pcbnew/Layer.B.CrtYd] Enabled=1 [pcbnew/Layer.F.CrtYd] Enabled=1 [pcbnew/Layer.B.Fab] Enabled=0 [pcbnew/Layer.F.Fab] Enabled=1 [pcbnew/Layer.Rescue] Enabled=0 [pcbnew/Netclasses] [pcbnew/Netclasses/Default] Name=Default Clearance=0.25 TrackWidth=0.25 ViaDiameter=0.8 ViaDrill=0.4 uViaDiameter=0.8 uViaDrill=0.4 dPairWidth=0.25 dPairGap=0.25 dPairViaGap=0.25 [pcbnew/Netclasses/1] Name=Min Clearance=0.1 TrackWidth=0.1 ViaDiameter=0.45 ViaDrill=0.2 uViaDiameter=0.45 uViaDrill=0.2 dPairWidth=0.12 dPairGap=0.12 dPairViaGap=0.25
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