Files
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/ LMB.kicad_pcb
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/ LMB.sch
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/ trigger_laser.sch
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sch / ADC.sch
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sch / ADC_1280.sch
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sch / ADC_160.sch
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sch / ADC_power.sch
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sch / clock.sch
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sch / Convert.sch
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sch / FE_connect.sch
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sch / FPGA_Gb.sch
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sch / FPGA_power.sch
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sch / GPIO.sch
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sch / power.sch
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sch / prog.sch
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sch / SB_power.sch
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sch / SFP.sch
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sch / Spy_box.sch
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sch / VFE_connect.sch
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sch / VFE_power.sch
Last update 4 years 9 months
by
Dejardin
clock.bakEESchema Schematic File Version 4 LIBS:LMB-cache EELAYER 26 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 10 11 Title "" Date "" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr $Comp L power:GNDD #PWR0903 U 1 1 5BAC498E P 4575 2900 F 0 "#PWR0903" H 4575 2650 50 0001 C CNN F 1 "GNDD" H 4575 2750 50 0000 C CNN F 2 "" H 4575 2900 50 0000 C CNN F 3 "" H 4575 2900 50 0000 C CNN 1 4575 2900 1 0 0 -1 $EndComp Wire Wire Line 3500 2600 3925 2600 Connection ~ 3925 2600 $Comp L power:GNDD #PWR0902 U 1 1 5BAC4996 P 4125 3850 F 0 "#PWR0902" H 4125 3600 50 0001 C CNN F 1 "GNDD" H 4125 3700 50 0000 C CNN F 2 "" H 4125 3850 50 0000 C CNN F 3 "" H 4125 3850 50 0000 C CNN 1 4125 3850 1 0 0 -1 $EndComp $Comp L Device:R R901 U 1 1 5BAC499C P 3500 2975 F 0 "R901" V 3580 2975 50 0000 C CNN F 1 "DNP" V 3500 2975 50 0000 C CNN F 2 "Resistor_SMD:R_0402_1005Metric" H 3500 2975 50 0001 C CNN F 3 "" H 3500 2975 50 0000 C CNN 1 3500 2975 1 0 0 -1 $EndComp $Comp L Device:R R902 U 1 1 5BAC49A3 P 3500 3425 F 0 "R902" V 3580 3425 50 0000 C CNN F 1 "DNP" V 3500 3425 50 0000 C CNN F 2 "Resistor_SMD:R_0402_1005Metric" H 3500 3425 50 0001 C CNN F 3 "" H 3500 3425 50 0000 C CNN 1 3500 3425 1 0 0 -1 $EndComp Wire Wire Line 4125 3800 3500 3800 Wire Wire Line 3500 3125 3500 3200 Wire Wire Line 3500 3200 3575 3200 Connection ~ 3500 3200 Wire Wire Line 4125 3750 4125 3800 Connection ~ 4125 3800 $Comp L MDJ_compo:VccO #PWR0901 U 1 1 5BAC49B2 P 3925 2550 F 0 "#PWR0901" H 3925 2400 50 0001 C CNN F 1 "VccO" H 3925 2700 50 0000 C CNN F 2 "" H 3925 2550 50 0000 C CNN F 3 "" H 3925 2550 50 0000 C CNN 1 3925 2550 1 0 0 -1 $EndComp Wire Wire Line 3925 2600 3925 2550 Wire Wire Line 4125 2650 4125 2600 Connection ~ 4125 2600 Wire Wire Line 3925 2600 4125 2600 Wire Wire Line 3500 3200 3500 3275 Wire Wire Line 4125 3800 4125 3850 Wire Wire Line 4125 2600 4575 2600 $Comp L MDJ_compo:SI590B U901 U 1 1 5BAD4CA7 P 4125 3200 F 0 "U901" H 3900 3450 60 0000 C CNN F 1 "SI590B" H 3950 3550 60 0000 C CNN F 2 "MDJ_mod:Si590" H 4125 3200 60 0001 C CNN F 3 "" H 4125 3200 60 0001 C CNN 1 4125 3200 1 0 0 -1 $EndComp $Comp L Device:C C901 U 1 1 5BADE5E1 P 4575 2750 F 0 "C901" H 4600 2825 50 0000 L CNN F 1 "100nF" H 4375 2675 50 0000 L CNN F 2 "Capacitor_SMD:C_0201_0603Metric" H 4613 2600 50 0001 C CNN F 3 "~" H 4575 2750 50 0001 C CNN 1 4575 2750 1 0 0 -1 $EndComp Wire Wire Line 3500 2600 3500 2825 Wire Wire Line 3500 3575 3500 3800 $Comp L Device:R R903 U 1 1 5C5858F4 P 5375 3150 F 0 "R903" V 5450 3150 50 0000 C CNN F 1 "100" V 5375 3150 50 0000 C CNN F 2 "Resistor_SMD:R_0201_0603Metric" H 5375 3150 50 0001 C CNN F 3 "" H 5375 3150 50 0000 C CNN 1 5375 3150 0 -1 -1 0 $EndComp Text HLabel 8475 3800 2 39 Output ~ 0 CLK_to_VFE+ Text HLabel 8475 3900 2 39 Output ~ 0 CLK_to_VFE- NoConn ~ 7600 3400 NoConn ~ 7600 3300 NoConn ~ 7600 3650 NoConn ~ 7600 3550 Wire Wire Line 6950 4200 6850 4200 $Comp L power:GNDD #PWR0904 U 1 1 5D10D3B0 P 6850 4200 F 0 "#PWR0904" H 6850 3950 50 0001 C CNN F 1 "GNDD" H 6850 4050 50 0000 C CNN F 2 "" H 6850 4200 50 0000 C CNN F 3 "" H 6850 4200 50 0000 C CNN 1 6850 4200 1 0 0 -1 $EndComp $Comp L MDJ_compo:VccO #PWR0905 U 1 1 5D10D38D P 6900 2750 F 0 "#PWR0905" H 6900 2600 50 0001 C CNN F 1 "VccO" H 6900 2900 50 0000 C CNN F 2 "" H 6900 2750 50 0000 C CNN F 3 "" H 6900 2750 50 0000 C CNN 1 6900 2750 1 0 0 -1 $EndComp Wire Wire Line 7600 3150 8475 3150 Text Label 5750 3250 0 39 ~ 0 loc_CLK- Text Label 5750 3150 0 39 ~ 0 loc_CLK+ Wire Wire Line 5750 3250 6200 3250 Wire Wire Line 5750 3150 6200 3150 $Comp L MDJ_compo:SI53340 U902 U 1 1 5D0D747D P 6900 3450 F 0 "U902" H 6900 3375 50 0000 C CNN F 1 "SI53340" H 6900 3450 50 0000 C CNN F 2 "MDJ_mod:QFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm_4Gnd" H 7950 2450 50 0001 C CNN F 3 "https://www.silabs.com/documents/public/data-sheets/Si5330.pdf" H 6400 3950 50 0001 C CNN 1 6900 3450 1 0 0 -1 $EndComp $Comp L Device:C C902 U 1 1 5D18C75B P 7050 2750 F 0 "C902" V 6925 2800 50 0000 L CNN F 1 "10uF" V 7000 2800 50 0000 L CNN F 2 "Capacitor_SMD:C_0402_1005Metric" H 7088 2600 50 0001 C CNN F 3 "~" H 7050 2750 50 0001 C CNN 1 7050 2750 0 1 1 0 $EndComp $Comp L power:GNDD #PWR0906 U 1 1 5D18C761 P 7200 2750 F 0 "#PWR0906" H 7200 2500 50 0001 C CNN F 1 "GNDD" H 7200 2600 50 0000 C CNN F 2 "" H 7200 2750 50 0000 C CNN F 3 "" H 7200 2750 50 0000 C CNN 1 7200 2750 1 0 0 -1 $EndComp Text HLabel 8475 3050 2 39 Output ~ 0 CLK_to_FPGA- Text HLabel 8475 3150 2 39 Output ~ 0 CLK_to_FPGA+ Wire Wire Line 7600 3800 8475 3800 Wire Wire Line 7600 3900 8475 3900 Wire Wire Line 4675 3150 5225 3150 Wire Wire Line 7600 3050 8475 3050 Wire Wire Line 4675 3250 5525 3250 Wire Wire Line 5525 3250 5525 3150 Text Label 4725 3150 0 39 ~ 0 loc_CLK- Text Label 4725 3250 0 39 ~ 0 loc_CLK+ Wire Wire Line 6200 3750 6200 4200 Wire Wire Line 6200 4200 6850 4200 Connection ~ 6850 4200 NoConn ~ 6200 3450 NoConn ~ 6200 3550 Connection ~ 6900 2750 $EndSCHEMATC