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Last update 5 years 1 month
by matt0930
iMX6 Rex_V1I1_PCB.drcProtel Design System Design Rule Check PCB File : S:\FEDEVEL\iMX6 Rex\V1I1\iMX6 Rex_V1I1_PCB.PcbDoc Date : 27. 9. 2013 Time : 15:39:18 Processing Rule : Clearance Constraint (Gap=0.075mm) ((IsRegion AND (OnLayer('L2') OR OnLayer('L11')))),(IsVia AND (HoleSize <> 0.1)) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0.075mm) (IsRegion AND (OnLayer('L5 (PWR)') OR OnLayer('L6 (PWR)') OR OnLayer('L7 (PWR)') OR OnLayer('L8 (PWR)') )),(IsVia) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0.2mm) (IsRegion AND (OnLayer('L5 (PWR)') OR OnLayer('L6 (PWR)') OR OnLayer('L7 (PWR)') OR OnLayer('L8 (PWR)') )),(IsRegion) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0.2mm) ((InPadClass('NPTH'))),(All) Rule Violations :0 Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.22mm) (Preferred=0.1mm) (InDifferentialPairClass('DIFF100')) Rule Violations :0 Processing Rule : Matched Net Lengths(Tolerance=0.127mm) (InDifferentialPairClass('DIFF100')) Rule Violations :0 Processing Rule : Width Constraint (Min=0.085mm) (Max=0.1mm) (Preferred=0.1mm) (InDifferentialPairClass('DIFF100')) Rule Violations :0 Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.19mm) (Preferred=0.1mm) (InDifferentialPairClass('DIFF90')) Rule Violations :0 Processing Rule : Matched Net Lengths(Tolerance=0.127mm) (InDifferentialPairClass('DIFF90')) Rule Violations :0 Processing Rule : Width Constraint (Min=0.085mm) (Max=0.101mm) (Preferred=0.1mm) (InDifferentialPairClass('DIFF90')) Rule Violations :0 Processing Rule : Net Antennae (Tolerance=0mm) (All) Rule Violations :0 Processing Rule : Silk to Silk (Clearance=0.1mm) (All),(All) Rule Violations :0 Processing Rule : Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All) Rule Violations :0 Processing Rule : Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All) Rule Violations :0 Processing Rule : Hole To Hole Clearance (Gap=0.1mm) (All),(All) Rule Violations :0 Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.1mm) (Preferred=0.1mm) (All) Rule Violations :0 Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=6mm) (All) Rule Violations :0 Processing Rule : Pads and Vias to follow the Drill pairs settings Rule Violations :0 Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) Rule Violations :0 Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.1mm, Vertical Gap = 0.1mm ) (All),(All) Rule Violations :0 Processing Rule : Routing Via (MinHoleWidth=0.1mm) (MaxHoleWidth=0.6mm) (PreferredHoleWidth=0.2mm) (MinWidth=0mm) (MaxWidth=0.8mm) (PreferedWidth=0.45mm) (All) Rule Violations :0 Processing Rule : Routing Layers(All) Rule Violations :0 Processing Rule : Width Constraint (Min=0.08mm) (Max=4mm) (Preferred=0.1mm) (All) Rule Violations :0 Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.1mm) (Entries=4) (All) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All) Rule Violations :0 Processing Rule : Un-Routed Net Constraint ( (All) ) Rule Violations :0 Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) Rule Violations :0 Processing Rule : Width Constraint (Min=0.2mm) (Max=4mm) (Preferred=0.3mm) (InNet('+VIN') OR InNet('+1V2_ETH') OR InNet('+1V5_DDR') OR InNet('+1V375') OR InNet('+2V5') OR InNet('+3V3')) Rule Violations :0 Processing Rule : Width Constraint (Min=0.2mm) (Max=4mm) (Preferred=0.3mm) (InNet('GND')) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0.085mm) ((IsRegion AND (OnLayer('L2') OR OnLayer('L11')))),(All) Violation between Polygon Region (664 hole(s)) L2 and Via (22.8mm,38.2mm) L2 to L3 Violation between Polygon Region (664 hole(s)) L2 and Via (22.5mm,37.9mm) L1 to L2 Rule Violations :2 Violations Detected : 2 Time Elapsed : 00:00:08