Design Rule Check - PCB1.drc
Protel Design System Design Rule Check
PCB File : F:\projects\IR_LED\PCB1.PcbDoc
Date     : 10/04/2020
Time     : 02:00:50

Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.4mm) (InPoly),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=2mm) (Preferred=0.2mm) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=0.2mm) (Preferred=0.2mm) ((InNetClass('ETH_RXD') OR InNetClass('ETH_TXD')))
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=3.5mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0.01mm) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=0.2mm) (InNetClass('USB_CTRL_2'))
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:02