Design Rule Check - Pwr Board.drc
Protel Design System Design Rule Check
PCB File : C:\Users\mmatusek\Documents\Altium Projects\ELEG_312_Pwr_Board\Pwr Board.PcbDoc
Date     : 11/17/2019
Time     : 5:18:37 PM

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=52.323mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (Disabled)(All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Room Pwr Board (Bounding Region = (11766.26mil, 9917.52mil, 18485.669mil, 12404.075mil) (InComponentClass('Pwr Board'))
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01