Place the ETH_PHY's VDD33 and AVDD33 (3V3_P) vias ...
by Eric Kuzmenko 7 years 3 months
Place the ETH_PHY's VDD33 and AVDD33 (3V3_P) vias closer to their respective pins (4 & 16)
27c0e12a
Update the 1.8V inductor's footprint such that its...
by Eric Kuzmenko 7 years 3 months
Update the 1.8V inductor's footprint such that its solder mask does not have pointed ends and is a more uniform shape
c6c2d463
Add fiducial marking dots on the F.Fab and B.Fab l...
by Eric Kuzmenko 7 years 3 months
Add fiducial marking dots on the F.Fab and B.Fab layers
51d86a37
Add reference designators to all footprints on the...
by Eric Kuzmenko 7 years 3 months
Add reference designators to all footprints on the *.Fab layers
2ba86c33
Hide all values on the *.Fab layer
by Eric Kuzmenko 7 years 3 months
40ad69a2
Add *.Fab outlines to each footprint
by Eric Kuzmenko 7 years 3 months
2d984e61
Run the smartcard's IO trace on the top layer, awa...
by Eric Kuzmenko 7 years 3 months
Run the smartcard's IO trace on the top layer, away from the CLK line, the clock being surrounded by RST and SC1_C4 (unused)
b3611577
Separate the smartcard CLK and IO lines a bit fart...
by Eric Kuzmenko 7 years 3 months
Separate the smartcard CLK and IO lines a bit farther apart
ff43a543
Tune WIFI_CLK to 50mm such that each data signal i...
by Eric Kuzmenko 7 years 3 months
Tune WIFI_CLK to 50mm such that each data signal is <20ps (<3mm) skew from the clock
56116b48
Increase the trace width of the ETH PHY's AVDD33 n...
by Eric Kuzmenko 7 years 3 months
Increase the trace width of the ETH PHY's AVDD33 net
d1f534a4
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