Dennis Field / dvk-mx8m-bsb - History

Separate the smartcard CLK and IO lines a bit farther apart

Tune WIFI_CLK to 50mm such that each data signal is <20ps (<3mm) skew from the clock

Increase the trace width of the ETH PHY's AVDD33 net

Update the fabrication drawing file with more information

This file was created by exporting both the Cmts.User layer, as well as the NPTH&PTH drills into separate DXF files, then combining them in the footprint editor, finally, this new footprint made from both of these is imported into the layout and re-exported as a single DXF.

Update the BoM with all part numbers from the "purchasing" BoM in NextCloud, update all manufacturing-related files after the last few commits' changes (including new assembly & fabrication files as requested)

Move some of the traces away from under the inductors (traces on layers In2.Cu and B.Cu)

Make a few improvements to the 5V buck converter's layout after the pin number mistake was fixed

Fixed an erroneous pin swapping in U402 (MIC2876).
Corrected library entry.
New placement and wiring for resistors near U402 in layout.

The signal CLK02 (clock supply for ethernet PHY) was surrounded with GND traces to form a shield against the static field (25 Mhz present).
The same was done now with sigbal CLK01 (clock supply for camera)
.

Bring back the current version number (v0.1.0) on the back silkscreen by replacing the word "Preliminary" with it