In preperation for the final order, re-export all ...
by Eric Kuzmenko 6 years 3 months
In preperation for the final order, re-export all the manufacturing files using the current date and rev number v1.0.0

Add the fab's stackup, panel array working files, and their CPW calculations
Make the layer setup/3D render setting reflect the...
by Eric Kuzmenko 6 years 10 months
Make the layer setup/3D render setting reflect the fact that the board should now have a 1.10mm nominal thickness
Correctly state 1.10mm as the nominal thickess of ...
by Eric Kuzmenko 6 years 10 months
Correctly state 1.10mm as the nominal thickess of the board in the fabrication notes, make the wifi_bt_feed_janielectronics_microsctrip calculation screenshot show the most significant figure of the board height/thickness (+0.21mm of the prototype calculations)
Place a copyright notice on the silkscreen and re-...
by Eric Kuzmenko 6 years 10 months
Place a copyright notice on the silkscreen and re-lock all footprints & tracks
Modify the antennas' feedlines for a 1.1mm nominal...
by Eric Kuzmenko 6 years 10 months
Modify the antennas' feedlines for a 1.1mm nominal thickness board using a relat
ive permittivity of 4.1~4.11

The H parameter in the calculations was +0.21mm greater than the H used in the p
rototype calculations (1.1mm thick board instead of 0.89mm thick)

A DK value of 4.11 was used for the GNSS and WWAN antennae feedlines and a DK of 4.1 was used for the Wi-Fi/BT feedlines since the operating frequency of the GNSS and WWAN is generally a bit lower than Wi-Fi/BT.

The NANYA NP-180TL spec sheet is also included. The specific prepreg/core/substrate/dielectric used is NANYA NP-180**TL** which has a DK specified as 4.1-4.3 @ 1GHz.
Add a TXB0101 logic level translator to the LCD_RE...
by Eric Kuzmenko 6 years 10 months
Add a TXB0101 logic level translator to the LCD_RESET# signal, the VIH(max) if the LCD's reset pin is 1.8V so the voltage needs to be translated from 3.3V logic down to 1.8V logic

The active TXB0101 level translator is used so that the pin can continue to be externally pulled low by a 10k resistor. The behavior of having this pin supplied with a logic level exceed its maximum rating is unpredictable (could be fine but could also act in unexpected ways). The TXB0101 is already used in the design as U1302, so now there will be 2x of these per board. This also requires two additional 0402 X5R 10V 100nF caps (already have 87 per board of CL05A104MP5NNNC / EmCraft PN: E-CAP-003-01, will now be 89 per board).
Make the new M.2 footprint's value on the F.Fab la...
by Eric Kuzmenko 6 years 10 months
Make the new M.2 footprint's value on the F.Fab layer invisible in the layout
Re-lock everything in the layout
by Eric Kuzmenko 6 years 10 months
Move the M.2 mounting hole down 2.025 according to...
by Eric Kuzmenko 6 years 10 months
Move the M.2 mounting hole down 2.025 according to Amphenol in order for it to line up with the 2230 card's mounting hole
Remove a redundant 3V3_P via near the M.2 footprin...
by Eric Kuzmenko 6 years 10 months
Remove a redundant 3V3_P via near the M.2 footprint which is no longer being used
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